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path: root/drivers/clk/tegra/clk-tegra-super-gen4.c
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* clk: tegra: clk-super: Fix to enable PLLP branches to CPUSowjanya Komatineni2019-11-111-1/+6
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-301-12/+1
* clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko2018-03-121-3/+5
* clk: tegra: Mark APB clock as criticalJon Hunter2017-11-011-1/+1
* clk: tegra: Re-factor T210 PLLX registrationAlex Frid2017-08-231-2/+9
* clk: tegra: super: Fix sparse warnings for functions not declared as staticJon Hunter2016-02-021-3/+3
* clk: tegra: Add Super Gen5 LogicBill Huang2015-12-171-13/+129
* Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd2015-08-251-1/+3
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| * clk: tegra: Add the DFLL as a possible parent of the cclk_g clockTuomas Tynkkynen2015-07-161-1/+3
* | clk: tegra: Properly include clk.hStephen Boyd2015-07-201-1/+0
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* clk: tegra: cclk_lp has a pllx/2 dividerAndrew Bresticker2014-02-171-1/+1
* clk: tegra: introduce common gen4 super clockPeter De Schrijver2013-11-261-0/+149