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path: root/drivers/cxl/core/port.c
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* Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams2023-06-251-45/+105
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| * cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter2023-06-251-0/+11
| * cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter2023-06-251-0/+27
| * cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter2023-06-251-0/+7
| * cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter2023-06-251-1/+0
| * cxl: Rename 'uport' to 'uport_dev'Dan Williams2023-06-251-28/+33
| * cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter2023-06-251-10/+10
| * cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams2023-06-251-2/+2
| * cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter2023-06-251-5/+16
* | Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams2023-06-251-0/+2
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| * | cxl/pci: Find and register CXL PMU devicesJonathan Cameron2023-05-301-0/+2
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* | cxl/memdev: Formalize endpoint port linkageDan Williams2023-06-251-2/+3
* | cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams2023-06-251-3/+3
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* cxl/port: Fix NULL pointer access in devm_cxl_add_port()Robert Richter2023-05-191-4/+3
* Merge tag 'cxl-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds2023-04-301-1/+0
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| * cxl/core: Drop unused io-64-nonatomic-lo-hi.hDan Williams2023-04-181-1/+0
* | Merge tag 'driver-core-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds2023-04-271-1/+1
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| * driver core: bus: mark the struct bus_type for sysfs callbacks as constantGreg Kroah-Hartman2023-03-231-1/+1
* | cxl/port: Fix find_cxl_root() for RCDs and simplify itDan Williams2023-04-041-31/+7
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* Merge tag 'cxl-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds2023-02-251-40/+83
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| * Merge branch 'for-6.3/cxl-ram-region' into cxl/nextDan Williams2023-02-101-39/+53
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| | * cxl/dax: Create dax devices for CXL RAM regionsDan Williams2023-02-101-1/+3
| | * tools/testing/cxl: Define a fixed volatile configuration to parseDan Williams2023-02-101-0/+2
| | * cxl/region: Add region autodiscoveryDan Williams2023-02-101-0/+2
| | * cxl/region: Add volatile region creation supportDan Williams2023-02-101-1/+13
| | * cxl/region: Add a mode attribute for regionsDan Williams2023-02-101-11/+1
| | * cxl/memdev: Fix endpoint port removalDan Williams2023-02-101-26/+32
| * | cxl: fix spelling mistakesRandy Dunlap2023-01-261-1/+1
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| * cxl/port: Link the 'parent_dport' in portX/ and endpointX/ sysfsDan Williams2023-01-251-0/+29
* | driver core: make struct bus_type.uevent() take a const *Greg Kroah-Hartman2023-01-271-4/+4
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* Merge branch 'for-6.2/cxl-xor' into for-6.2/cxlDan Williams2022-12-051-3/+6
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| * cxl/acpi: Support CXL XOR Interleave Math (CXIMS)Alison Schofield2022-12-031-3/+6
* | Merge branch 'for-6.2/cxl-aer' into for-6.2/cxlDan Williams2022-12-051-1/+1
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| * | cxl/core/regs: Make cxl_map_{component, device}_regs() device genericDan Williams2022-12-031-1/+1
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* | cxl/port: Add RCD endpoint port enumerationDan Williams2022-12-051-0/+7
* | cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_memDan Williams2022-12-051-39/+0
* | cxl/acpi: Extract component registers of restricted hosts from RCRBRobert Richter2022-12-031-6/+47
* | cxl/acpi: Move rescan to the workqueueDan Williams2022-12-021-2/+17
* | cxl: Unify debug messages when calling devm_cxl_add_dport()Robert Richter2022-11-141-14/+34
* | cxl: Unify debug messages when calling devm_cxl_add_port()Robert Richter2022-11-141-12/+39
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* cxl/region: Fix 'distance' calculation with passthrough portsDan Williams2022-11-041-2/+9
* cxl/region: Delete 'region' attribute from root decodersDan Williams2022-08-011-1/+2
* cxl/region: Introduce cxl_pmem_region objectsDan Williams2022-07-261-0/+2
* cxl/region: Add region driver boiler plateDan Williams2022-07-261-0/+9
* cxl/hdm: Commit decoder state to hardwareDan Williams2022-07-251-0/+1
* cxl/region: Program target listsDan Williams2022-07-251-3/+1
* cxl/region: Attach endpoint decodersDan Williams2022-07-251-7/+3
* cxl/acpi: Add a host-bridge index lookup mechanismDan Williams2022-07-251-0/+16
* cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams2022-07-251-0/+9
* cxl/region: Add region creation supportBen Widawsky2022-07-211-0/+39
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