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path: root/drivers/gpu/drm/amd/display/dc/clk_mgr
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* drm/amd/display: Wake DMCUB before sending a commandNicholas Kazlauskas2023-12-195-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] We can hang in place trying to send commands when the DMCUB isn't powered on. [How] For functions that execute within a DC context or DC lock we can wrap the direct calls to dm_execute_dmub_cmd/list with code that exits idle power optimizations and reallows once we're done with the command submission on success. For DM direct submissions the DM will need to manage the enter/exit sequencing manually. We cannot invoke a DMCUB command directly within the DM execution helper or we can deadlock. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add function for dumping clk registersJohnson Chen2023-12-191-4/+3
| | | | | | | | | | | | | | [why] Allow devs to check raw clk register values by dumping them on the log [how] Add clk register dump implementation Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Johnson Chen <johnson.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: trivial comment changeAurabindo Pillai2023-12-131-1/+1
| | | | | | | | | FP guard is valid for all recent asics, not just RV, so fix the comment. Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix spelling mistake "SMC_MSG_AllowZstatesEntr" -> ↵Colin Ian King2023-12-131-4/+4
| | | | | | | | | "SMC_MSG_AllowZstatesEntry" There is a spelling mistake in a smu_print message. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix disable_otg_wa logicNicholas Susanto2023-12-061-8/+0
| | | | | | | | | | | | | | | | | | | | [Why] When switching to another HDMI mode, we are unnecesarilly disabling/enabling FIFO causing both HPO and DIG registers to be set at the same time when only HPO is supposed to be set. This can lead to a system hang the next time we change refresh rates as there are cases when we don't disable OTG/FIFO but FIFO is enabled when it isn't supposed to be. [How] Removing the enable/disable FIFO entirely. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Nicholas Susanto <nicholas.susanto@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Added delay to DPM logRelja Vojvodic2023-12-061-10/+16
| | | | | | | | | | | HW registers were being read to quickly, causing incorrect values to be logged after a clock frequency was changed Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Relja Vojvodic <relja.vojvodic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: revert removing otg toggle w/a back when no active displayCharlene Liu2023-12-062-9/+7
| | | | | | | | | | | | | | | | | | | w/a use case: - dual display, compliance, toggling between the displays - switching between 120Hz 420 -> 144Hz 444 and vice versa - switching between 144Hz -> 60Hz TMDS or vice versa It'd typically involve TMDS in some capacity since that's the only link signal we leave the OTG running but DIO/PHY off you can hit this in cases where you have multiple displays as well it syncs with the first active OTG, so if you had OTG[0] mapped and FIFO off you'd hit it even if OTG[1] was mapped and had FIFO Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: insert drv-pmfw log + rollback to new contextCharlene Liu2023-12-062-23/+47
| | | | | | | | | | | | Rollback to new context for active display: this was previous tested sequence. Avoid to do OTG master toggle is no active display at all, this w/a was for fifo err. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Chris Park <chris.park@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Allow DTBCLK disable for DCN35Nicholas Kazlauskas2023-11-291-15/+12
| | | | | | | | | | | | | | | | | | | | | | | | | [Why] DTBCLK is enabled on idle and it will burn power. [How] There's a few issues here: - Always enabling DTBCLK on clock manager init - Setting refclk when DTBCLK is supposed to be disabled - Not applying the correct calculated version refclk, but instead the base value which might be zero On dtbclk_en change we'll message PMFW to enable or disable the clock accordingly. The DTBDTO will be then based on refclk, but it will be set to the default fixed value if there was nothing calculated in DML despite the clock being considered enabled. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: update dcn315 lpddr pstate latencyDmytro Laktyushkin2023-11-291-4/+4
| | | | | | | | | | | [WHY/HOW] Increase the pstate latency to improve ac/dc transition Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix black screen on video playback with embedded panelSung Joon Kim2023-11-291-1/+0
| | | | | | | | | | | | | | | [why] We have dynamic power control in driver but should be ignored when power is forced on. [how] Bypass any power control when it's forced on. Cc: stable@vger.kernel.org Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Update DCN35 clock table policyNicholas Kazlauskas2023-11-291-26/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The new table doesn't have an implicit mapping between Fclk SOC voltage and MemClk and it currently builds the table off of number of Fclk states rather than DcfClock states. The DML table in use is not correct for functionality or power and does not align with our existing policies for DCN3x. [How] Build the table based on DcfClock with the following assumptions: 1. Raising Soc voltage is the most expensive operation, so assume that running at max DispClock or DppClock is preferable. 2. Assume that we can run at max Fclk / MemClk at any state, but restrict the maximum state to the very last entry in the table as the worst case scenario. 3. Assume that Fclk always has a 2x multiplier on DcfClock unless the table specifies something lower. Reviewed-by: Taimur Hassan <syed.hassan@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Do not read DPREFCLK spread info from LUT on DCN35Michael Strauss2023-11-291-22/+0
| | | | | | | | | | | | | [WHY] Currently DCN35 does not spread DPREFCLK [HOW] Remove hardcoded table with nonzero caps Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Update DCN35 watermarksNicholas Kazlauskas2023-11-291-16/+16
| | | | | | | | | | | [Why & How] Update to the new values per HW team request. Affects both stutter and z8. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add disable timeout optionDuncan Ma2023-11-171-0/+3
| | | | | | | | | | | | | | | | | | | [WHY] Driver continues running whenever there is is timeout from smu or dmcub. It is difficult to track failure state when dcn, dc or dmcub changes on root failure. [HOW] Add disable_timeout option to halt driver whenever there is a failure in response. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Negate IPS allow and commit bitsDuncan Ma2023-11-171-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | [WHY] On s0i3, IPS mask isn't saved and restored. It is reset to zero on exit. If it is cleared unexpectedly, driver will proceed operations while DCN is in IPS2 and cause a hang. [HOW] Negate the bit logic. Default value of zero indicates it is still in IPS2. Driver must poll for the bit to assert. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Disable OTG for mode timing switch on DCN35Ovidiu Bunea2023-11-071-1/+2
| | | | | | | | | | | | | | | [why] Doing a mode timing change causes a hang when OTG is not disabled. [how] Add link_enc null check in disable_otg_wa to cover this case. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Fix OTG disable workaround logicTaimur Hassan2023-11-071-4/+7
| | | | | | | | | | | | | | | | | [Why] DENTIST was hanging when performing DISPCLK update with OTG enabled, as OTG disable workaround was not executing. [How] Workaround was checking against current_state before running, but when called from optimize_bandwidth (safe_to_lower), we should be checking against context instead. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Enable more IPS optionsSung Joon Kim2023-11-071-3/+4
| | | | | | | | | | | | | | | | | [why] To help isolate static screen and video playback tests, we want to enable an IPS option to allow IPS only on D3 cycle. [how] Add DISABLE_DYNAMIC and DISABLE_ALL IPS disable flags for user control. Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Refactor HWSS into component folderMounika Adhuri2023-10-091-1/+1
| | | | | | | | | | | | | | | | | | | [why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Mounika Adhuri <moadhuri@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Update pmfw_driver_if new structureCharlene Liu2023-10-092-76/+174
| | | | | | | | | | | | | | [why] pmfw header file updated, need align with data structure. [How] Update the data structure. Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Modify SMU message logsSung Joon Kim2023-10-092-6/+7
| | | | | | | | | | | | | | | | | [why] It's important to make sure SMU messages are logged by default to improve debugging for power optimization use cases. [how] Change logs to warnings when SMU message returns non-success id. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Make driver backwards-compatible with non-IPS PMFWOvidiu Bunea2023-10-041-10/+18
| | | | | | | | | | | | | | [why] Driver needs to be compatible with PM FW that doesn't support IPS [how] Toggle internal control flag Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: apply edge-case DISPCLK WDIVIDER changes to master OTG ↵Samson Tam2023-10-042-4/+4
| | | | | | | | | | | | | | | | | | | | | pipes only [Why] The edge-case DISPCLK WDIVIDER changes call stream_enc functions. But with MPC pipes, downstream pipes have null stream_enc and will cause crash. [How] Only call stream_enc functions for pipes that are OTG master. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: switch DC over to the new DRM logging macrosHamza Mahfooz2023-09-261-2/+0
| | | | | | | | | | | | | | | | | | | | For multi-GPU systems it is difficult to tell which GPU a particular message is being printed for and that is undesirable because it complicates debugging efforts. Also, the new macros allow us to enable logging for particular parts of the codebase more selectively (since we no longer need to throw everything at DRM_DEBUG_KMS()). So, for the reasons outlined above we should switch to the new macros. We can accomplish this by using the existing DC_LOGGER code to pass around the relevant `struct drm_device` which will be fed to the new macros in logger_types.h. Also, we must get rid of all instances of the DC_LOG_.*() functions that are currently in amdgpu_dm since we don't use the DC logger there and we can simply refer to the macros directly there instead. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Improve x86 and dmub ips handshakeDuncan Ma2023-09-263-3/+52
| | | | | | | | | | | | | | | | | | | | | | | | [Why] There is a race condition between x86 and dmcub fw when attempting to exit IPS2. Scenarios including exiting IPS2 before IPS2 has been entered. This can cause unexpected hang when DMCUB attempt to exit while PMFW still tries to enter IPS2. [How] A new design has been introduced to remove race conditions and improve the handshake between x86 and DMCUB. An AON scratch register is borrowed from PMFW to determine whether DMCUB has committed to IPS entry or not. In the case when dmcub has committed IPS entry, x86 must poll until an exit event occurred either from DMCUB(IPS1) or PMFW(IPS2). x86 will wait upperbound of evaluation and IPS entry time to ensure IPS2 exit event has been sent to PMFW. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add IPS control flagSung Joon Kim2023-09-203-1/+31
| | | | | | | | | | | | | | | | | | [why] Currently, driver is not aware if IPS is supported. After PMFW helps implement new message query functionality, driver will set IPS capability flag. [how] Create new SMU hook function to query IPS capability. Based on the cap, set appropriate flags to false for power-gating purposes. This will avoid keeping SMU busy and offloading tasks to DMUB/driver. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Correct z8 watermark maskCharlene Liu2023-09-201-2/+0
| | | | | | | | | | | Correct z8_watermark mask from 16bit to 20bit. Also, do not set dcn35 dprefclk in clk_mgr_construct. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add pointer check before function callSung Joon Kim2023-09-201-1/+3
| | | | | | | | | | | Call to immediate_disable_crtc was not checked before calling, exposing a potential null pointer hang. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Enable DCLK_DS from driver by defaultMuhammad Ahmed2023-09-201-3/+0
| | | | | | | | | | PMFW ungate this feature, this can be enabled now Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DCN35 case for dc_clk_mgr_createQingqing Zhuo2023-09-201-0/+13
| | | | | | | | | | Add DCN 35 case for dc_clk_mgr_create. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix some non-initialized register mask and settingCharlene Liu2023-09-111-14/+42
| | | | | | | | | | | [why] fix some non-initialized register mask and update golden setting Reviewed-by: Duncan Ma <duncan.ma@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add new logs for AutoDPMTestEthan Bitnun2023-09-111-0/+36
| | | | | | | | | | | | | [Description] - Add new logs to be used by the AutoDPMTest - Enclose AutoDPMTest logs in settings - Add logging definition Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Ethan Bitnun <etbitnun@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: clean up some inconsistent indentingsYang Li2023-09-061-14/+14
| | | | | | | drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c:288 dcn35_update_clocks() warn: inconsistent indenting Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Remove duplicated include in dcn35_clk_mgr.cYang Li2023-09-061-1/+0
| | | | | | | ./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c: dcn35_clk_mgr.h is included more than once. Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DCN35 CLK_MGRQingqing Zhuo2023-08-306-0/+1710
| | | | | | | | | | | [Why & How] Add CLK_MGR handling for DCN35. v2: Drop stale SMU interfaces (Alex) Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add smu write msg id fail retry processFudong Wang2023-08-301-4/+16
| | | | | | | | | | | | | | | A benchmark stress test (12-40 machines x 48hours) found that DCN315 has cases where DC writes to an indirect register to set the smu clock msg id, but when we go to read the same indirect register the returned msg id doesn't match with what we just set it to. So, to fix this retry the write until the register's value matches with the requested value. Cc: stable@vger.kernel.org # 6.1+ Fixes: f94903996140 ("drm/amd/display: Add DCN315 CLK_MGR") Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Fudong Wang <fudong.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: add check for PMFW hard min request completeSamson Tam2023-08-302-3/+162
| | | | | | | | | | | | | | | | | [Why] When we issue hard min request to PMFW, the ack back does not guarantee the request has been fulfilled. [How] Add new PMFW message to check if the hard min request has been completed. Returned bit mask indicates which clock requests are completed. Check PMFW version before using message Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: PMFW to wait for DMCUB ack for FPO casesAlvin Lee2023-08-153-0/+13
| | | | | | | | | | | | [Description] We want PMFW to wait for DMCUB to ACK the MCLK end message for FPO cases as well. Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Update replay for clk_mgr optimizationsBhawanpreet Lakha2023-08-151-0/+3
| | | | | | | | Add Replay calls to clk_mgr updates (just like PSR) Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Clean up errors in dcn316_smu.cRan Sun2023-08-091-10/+8
| | | | | | | | | | Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line ERROR: code indent should use tabs where possible Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Clean up errors in dcn316_clk_mgr.cRan Sun2023-08-091-4/+2
| | | | | | | | | Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Clean up errors in dcn315_smu.cRan Sun2023-08-091-14/+12
| | | | | | | | | | Fix the following errors reported by checkpatch: ERROR: open brace '{' following struct go on the same line ERROR: code indent should use tabs where possible Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Use max memclk variable when setting max memclkAlvin Lee2023-08-071-1/+1
| | | | | | | | | | | | | | | [Description] In overclocking scenarios the max memclk could be higher than the DC mode limit. However, for configs that don't support MCLK switching we need to set the max memclk to the overclocked max instead of the DC mode max or we could result in underflow. Reviewed-by: Samson Tam <samson.tam@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Revert "drm/amd/display: Read down-spread percentage from ↵Leo Chen2023-08-072-38/+1
| | | | | | | | | | | | | | lut to adjust dprefclk." [Why & How] Revert commit 6917b0b71171 ("drm/amd/display: Read down-spread percentage from lut to adjust dprefclk.") This change was causing 240hz display to not light up after s0i3. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Read down-spread percentage from lut to adjust dprefclk.Martin Tsai2023-07-252-2/+38
| | | | | | | | | | | | | | | [Why] Panels show corruption with high refresh rate timings when ss is enabled. [How] Read down-spread percentage from lut to adjust dprefclk. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Martin Tsai <martin.tsai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Keep PHY active for DP displays on DCN31Nicholas Kazlauskas2023-07-181-0/+5
| | | | | | | | | | | | | | | | | [Why & How] Port of a change that went into DCN314 to keep the PHY enabled when we have a connected and active DP display. The PHY can hang if PHY refclk is disabled inadvertently. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Josip Pavic <josip.pavic@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Initialize necessary uninitialized variablesMeera Patel2023-07-181-1/+1
| | | | | | | | | | | This commit initializes uninitialized variables. For some compilers uninitialized variable warnings are treated as Error. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Meera Patel <meera.patel@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Hardcode vco_freq for dcn316Alan Liu2023-07-181-42/+2
| | | | | | | | | | | | There is no need to calculate the VCO frequency. In our internal branch we've hard-coded this for a while, so it's well-tested. This also allows us to remove the now unused code for calculating the VCO frequency. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Alan Liu <haoping.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Enable dc mode clock switching for DCN32xAlvin Lee2023-06-231-6/+37
| | | | | | | | | | | | | | | - DC mode clock switch interface was previously only executed for DCN303. Enable it for DCN32x so that the interface is called correctly - Assign function pointers for DCN32x that are used in the dc mode interface - Update the dc mode interface to work generically for each ASIC - In update_clocks, make sure to consider softmax if we're in DC mode Reviewed-by: Jun Lei <jun.lei@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 01:20:55 +0000