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| * drm/amdgpu: Update PSP TA unload functionCandice Li2021-09-231-10/+10
| | | | | | | | | | | | | | | | Update PSP TA unload function to use PSP TA context as input argument. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Conform ASD header/loading to generic TA systemsCandice Li2021-09-232-44/+26
| | | | | | | | | | | | | | | | | | Update asd_context structure and add asd_initialize function to conform ASD header/loading to generic TA systems. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/display: add a proper license to dc_link_dp.cAlex Deucher2021-09-231-1/+23
| | | | | | | | | | | | | | Was missing. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Fix white screen page fault for gpuvmNicholas Kazlauskas2021-09-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The "base_addr_is_mc_addr" field was added for dcn3.1 support but pa_config was never updated to set it to false. Uninitialized memory causes it to be set to true which results in address mistranslation and white screen. [How] Use memset to ensure all fields are initialized to 0 by default. Fixes: 64b1d0e8d500 ("drm/amd/display: Add DCN3.1 HWSEQ") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * amd/display: enable panel orientation quirksSimon Ser2021-09-231-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows panel orientation quirks from DRM core to be used. They attach a DRM connector property "panel orientation" which indicates in which direction the panel has been mounted. Some machines have the internal screen mounted with a rotation. Since the panel orientation quirks need the native mode from the EDID, check for it in amdgpu_dm_connector_ddc_get_modes. Signed-off-by: Simon Ser <contact@emersion.fr> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Demote TMZ unsupported log message from warning to infoPaul Menzel2021-09-231-1/+1
| | | | | | | | | | | | | | | | | | As the user cannot do anything about the unsupported Trusted Memory Zone (TMZ) feature, do not warn about it, but make it informational, so demote the log level from warning to info. Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Drop inline from amdgpu_ras_eeprom_max_record_countMichel Dänzer2021-09-232-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was unusual; normally, inline functions are declared static as well, and defined in a header file if used by multiple compilation units. The latter would be more involved in this case, so just drop the inline declaration for now. Fixes compile failure building for ppc64le on RHEL 8: In file included from ../drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h:32, from ../drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:33: ../drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function ‘amdgpu_ras_recovery_init’: ../drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:90:17: error: inlining failed in call to ‘always_inline’ ‘amdgpu_ras_eeprom_max_record_count’: function body not available 90 | inline uint32_t amdgpu_ras_eeprom_max_record_count(void); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1985:34: note: called from here 1985 | max_eeprom_records_len = amdgpu_ras_eeprom_max_record_count(); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: c84d46707ebb "drm/amdgpu: validate bad page threshold in ras(v3)" Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: pass drm dev radeon_agp_head_init directlyNirmoy Das2021-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | Pass drm dev directly as rdev->ddev gets initialized later on at radeon_device_init(). Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214375 Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/pm: fix runpm hang when amdgpu loaded prior to sound driverEvan Quan2021-09-234-4/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current RUNPM mechanism relies on PMFW to master the timing for BACO in/exit. And that needs cooperation from sound driver for dstate change notification for function 1(audio). Otherwise(on sound driver missing), BACO cannot be kicked in correctly and hang will be observed on RUNPM exit. By switching back to legacy message way on sound driver missing, we are able to fix the runpm hang observed for the scenario below: amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded Signed-off-by: Evan Quan <evan.quan@amd.com> Reported-and-tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Fix a race of IB testxinhui pan2021-09-141-2/+2
| | | | | | | | | | | | | | | | Direct IB submission should be exclusive. So use write lock. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: VCN avoid memory allocation during IB testxinhui pan2021-09-141-53/+44
| | | | | | | | | | | | | | | | alloc extra msg from direct IB pool. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: VCE avoid memory allocation during IB testxinhui pan2021-09-141-14/+13
| | | | | | | | | | | | | | | | alloc extra msg from direct IB pool. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: UVD avoid memory allocation during IB testxinhui pan2021-09-144-53/+74
| | | | | | | | | | | | | | | | move BO allocation in sw_init. Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Unify PSP TA contextCandice Li2021-09-148-118/+141
| | | | | | | | | | | | | | | | | | Remove all TA binary structures and add the specific binary structure in struct ta_context. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: move iommu_resume before ip init/resumeJames Zhu2021-09-141-0/+12
| | | | | | | | | | | | | | | | | | | | Separate iommu_resume from kfd_resume, and move it before other amdgpu ip init/resume. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211277 Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: add amdgpu_amdkfd_resume_iommuJames Zhu2021-09-142-0/+11
| | | | | | | | | | | | | | | | | | Add amdgpu_amdkfd_resume_iommu for amdgpu. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211277 Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdkfd: separate kfd_iommu_resume from kfd_resumeJames Zhu2021-09-142-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | Separate kfd_iommu_resume from kfd_resume for fine-tuning of amdgpu device init/resume/reset/recovery sequence. v2: squash in fix for !CONFIG_HSA_AMD Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211277 Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Get atomicOps info from Host for sriov setupshaoyunl2021-09-142-12/+16
| | | | | | | | | | | | | | | | | | | | | | The AtomicOp Requester Enable bit is reserved in VFs and the PF value applies to all associated VFs. so guest driver can not directly enable the atomicOps for VF, it depends on PF to enable it. In current design, amdgpu driver will get the enabled atomicOps bits through private pf2vf data Signed-off-by: shaoyunl <shaoyun.liu@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Enable mem low power control for DCN3.1 sub-IP blocksMichael Strauss2021-09-141-8/+8
| | | | | | | | | | | | | | | | | | | | | | [WHY] Sequences to handle powering down these sub-IP blocks are now ready for use Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: remove force_enable_edp_fec param.Ian Chen2021-09-142-4/+2
| | | | | | | | | | | | | | | | Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Add VPG and AFMT low power support for DCN3.1Michael Strauss2021-09-1415-29/+593
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] Power down VPG and AFMT blocks when not in use [HOW] Create afmt31 and vpg31 structs and add necessary fields to reg list Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Revert adding degamma coefficientsJaehyun Chung2021-09-141-39/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Degamma coefficients are calculated in our degamma formula using the regamma coefficients. We do not need to add separate degamma coefficients. [How] Remove the change to add separate degamma coefficients. Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Link training retry fix for abort caseMeenakshikumar Somasundaram2021-09-141-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] If link training is aborted, it shall be retried if sink is present. [How] Check hpd status to find out whether sink is present or not. If sink is present, then link training shall be tried again with same settings. Otherwise, link training shall be aborted. Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Fix unstable HPCP compliance on Chrome BarceloQingqing Zhuo2021-09-141-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Intermittently, there presents two occurrences of 0 stream commits in a single HPD event. Current HDCP sequence does not consider such scenerio, and will thus disable HDCP. [How] Add condition check to include stream remove and re-enable case for HDCP enable. Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: 3.2.152Aric Cyr2021-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | * Correct degamma coefficients * Optimize bandwidth on following fast update * Fix multiple memory leaks reported by coverity * Get backlight from PWM if DMCU is not initialized Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Correct degamma coefficientsJaehyun Chung2021-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | [Why] Some incorrect coefficients were being used Reviewed-by: Michael Strauss <michael.strauss@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: [FW Promotion] Release 0.0.82Anthony Koo2021-09-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | * PSR SMU optimizations * MST dock fixes Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Add periodic detection when zstate is enabledEric Yang2021-09-1413-6/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] When system is in Z10 HPD interrupts cannot fire, we may miss display configuration changes. [How] When Zstate is enabled, if DMUB indicate DCN has lost power, do a complete detection periodically. Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: dsc mst 2 4K displays go dark with 2 lane HBR3Hersen Wu2021-09-143-17/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] call stack of amdgpu dsc mst pbn, slot num calculation is as below: -compute_bpp_x16_from_target_bandwidth -decide_dsc_target_bpp_x16 -setup_dsc_config -dc_dsc_compute_bandwidth_range -compute_mst_dsc_configs_for_link -compute_mst_dsc_configs_for_state from pbn -> dsc target bpp_x16 bpp_x16 is calulated by compute_bpp_x16_from_target_bandwidth. Beside pixel clock and bpp, num_slices_h and bpp_increment_div will also affect bpp_x16. from dsc target bpp_x16 -> pbn within dm_update_mst_vcpi_slots_for_dsc, pbn = drm_dp_calc_pbn_mode(clock, bpp_x16, true); drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) { return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006), 8 * 54 * 1000 * 1000); } bpp / 16 trunc digits after decimal point. This will cause calculation delta. drm_dp_calc_pbn_mode does not have other informations, like num_slices_h, bpp_increment_div. therefore, it does not do revese calcuation properly from bpp_x16 to pbn. pbn from drm_dp_calc_pbn_mode is less than pbn from compute_mst_dsc_configs_for_state. This cause not enough mst slot allocated to display. display could not visually light up. [How] pass pbn from compute_mst_dsc_configs_for_state to dm_update_mst_vcpi_slots_for_dsc Cc: stable@vger.kernel.org Reviewed-by: Scott Foster <Scott.Foster@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Hersen Wu <hersenwu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Refine condition of cursor visibility for pipe-splitDale Zhao2021-09-141-19/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] In some scenarios like fullscreen game, major plane is scaled. Then if a upper layer owns the cursor, cursor is invisiable in the majority of the screen. [How] Instead assuming upper plane handles cursor, summing up upper split planes on the same layer. If whole upper plane covers current half/whole pipe plane, disable cursor. Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Dale Zhao <dale.zhao@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Optimize bandwidth on following fast updateNicholas Kazlauskas2021-09-141-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The current call to optimize_bandwidth never occurs because flip is always pending from the FULL and FAST updates. [How] Optimize on the following flip when it's a FAST update and we know we aren't going to be modifying the clocks again. Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Apply w/a for hard hang on HPDQingqing Zhuo2021-09-145-2/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] HPD disable and enable sequences are not mutually exclusive on Linux. For HPDs that spans under 1s (i.e. HPD low = 1s), part of the disable sequence (specifically, a request to SMU to lower refclk) could come right before the call to PHY enablement, causing DMUB to access an irresponsive PHY and thus a hard hang on the system. [How] Disable 48mhz refclk off when there is any HPD status in connected state. Reviewed-by: Hersen Wu <hersenwu@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Add regamma/degamma coefficients and set sRGB when TF is BT709Jaehyun Chung2021-09-141-20/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] In YUV case, need to set the input TF to sRGB instead of BT709, even though the input TF type is distributed. SRGB was not being used because pixel format was not being set in the surface update sequence. Also, we were using the same coefficients for degamma and regamma formula, causing the cutoff point of the linear section of the curve to be incorrect. [How] Set pixel format in the surface update sequence. Add separate coefficient arrays for regamma and degamma. Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Revert "Directly retrain link from debugfs"Anson Jacob2021-09-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit f5b6a20c7ef40599095c796b0500d842ffdbc639. This patch broke new settings from taking effect. Hotplug is required for new settings to take effect. Reviewed-by: Mikita Lipski <mikita.lipski@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Get backlight from PWM if DMCU is not initializedHarry Wentland2021-09-142-14/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Carrizo/Stoney systems we set backlight through panel_cntl, i.e. directly via the PWM registers, if DMCU is not initialized. We always read it back through ABM registers which leads to a mismatch and forces atomic_commit to program the backlight each time. Instead make sure we use the same logic for backlight readback, i.e. read it from panel_cntl if DMCU is not initialized. We also need to remove some extraneous and incorrect calculations at the end of dce_get_16_bit_backlight_from_pwm. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1666 Cc: stable@vger.kernel.org Reviewed-by: Josip Pavic <josip.pavic@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Fix multiple memory leaks reported by coverityAnson Jacob2021-09-144-5/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | coccinelle patch used: @@ expression enc1,vpg,afmt; @@ - if (!enc1 || !vpg || !afmt) + if (!enc1 || !vpg || !afmt) { + kfree(enc1); + kfree(vpg); + kfree(afmt); return NULL; + } Addresses-Coverity-ID: 1466017: ("Resource leaks") Reviewed-by: Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: 3.2.151Aric Cyr2021-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | * coverity kernel memory leak fixes * NULL pointer dereference fixes * Add periodic detection when zstate is enabled * Fork thread to offload work of hpd_rx_irq Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Revert "dc: w/a for hard hang on HPD on native DP"Qingqing Zhuo2021-09-141-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit "drm/amd/display: w/a for hard hang on HPD on native DP". [How & Why] Revert change as it does not fix the hard hang in all cases. An alternative w/a will be submitted separately. Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: [FW Promotion] Release 0.0.81Anthony Koo2021-09-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | * PSR optimizations * add support for ABM when ODM is enabled * Z10 with PSR fixes * Increase trace buffer Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Fix for null pointer access for ddc pin and aux engine.Meenakshikumar Somasundaram2021-09-143-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Need a check for NULL pointer access for ddc pin and aux engine. [How] Adding a check for ddc pin and aux engine accesses. Reviewed-by: Jimmy Kizito <jimmy.kizito@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Fix false BAD_FREE warning from CoverityAnson Jacob2021-09-141-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an attempt to fix false warning raised by Coverity via multiple CID's. Addresses-Coverity-ID: 1487412 ("Free of address-of expression") Cc: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Wesley Chalmers <wesley.chalmers@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Fix dynamic link encoder access.Jimmy Kizito2021-09-1412-39/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Assuming DIG link encoders are statically mapped to links can cause system instability due to null pointer accesses. [How] - Add checks for non-null link encoder pointers before trying to access them. - When a hardware platform uses dynamic DIG assignment (i.e. resource function 'link_encs_assign' defined) and a link supports flexible mapping to DIGs, use the link_enc_cfg API to access the DIG assigned to a link or stream. Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Add flag to detect dpms force off during HPDAurabindo Pillai2021-09-143-10/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] When a connector is unplugged, dpms is forced off so that some connector allocations are cleared off. This is done outside the commit sequence from the userspace. This causes HUBP blank. Due to the blank hubp, a non blocking commit which queues flip will encounter a timeout waiting for the flip_done because prior to writing the surface flip address, hubp was in blank. [How] Add a marker to DM's crtc state and use this field to indicate whether dpms was forced off during an HPD. Check for this marker before queuing the flip. Reviewed-by: Anson Jacob <Anson.Jacob@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: unblock abm when odm is enabled only on configs that support itJosip Pavic2021-09-143-16/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] When ODM is enabled, ABM is blocked on dcn31 but unblocked on dcn30. Since the dcn31 firmware is now able to handle ABM interop with ODM, it is no longer necessary to block ABM when ODM is enabled. Since the dcn30 firmware does not handle ABM interop with ODM, leaving that combination unblocked can lead to one side of the screen appearing brighter than the other. [How] When ODM is enabled, unblock abm on dcn31 and block it on dcn30 Reviewed-by: Anthony Koo <anthony.koo@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Josip Pavic <Josip.Pavic@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Fork thread to offload work of hpd_rx_irqWayne Lin2021-09-144-48/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Currently, we will try to get dm.dc_lock in handle_hpd_rx_irq() when link lost happened, which is risky and could cause deadlock. e.g. If we are under procedure to enable MST streams and then monitor happens to toggle short hpd to notify link lost, then handle_hpd_rx_irq() will get blocked due to stream enabling flow has dc_lock. However, under MST, enabling streams involves communication with remote sinks which need to use handle_hpd_rx_irq() to handle sideband messages. Thus, we have deadlock here. [How] Target is to have handle_hpd_rx_irq() finished as soon as possilble. Hence we can react to interrupt quickly. Besides, we should avoid to grabe dm.dc_lock within handle_hpd_rx_irq() to avoid deadlock situation. Firstly, revert patches which introduced to use dm.dc_lock in handle_hpd_rx_irq(): * commit ("drm/amd/display: NULL pointer error during ") * commit ("drm/amd/display: Only one display lights up while using MST") * commit ("drm/amd/display: take dc_lock in short pulse handler only") Instead, create work to handle irq events which needs dm.dc_lock. Besides: * Create struct hpd_rx_irq_offload_work_queue for each link to handle its short hpd events * Avoid to handle link lost/ automated test if the link is disconnected * Defer dc_lock needed works in dc_link_handle_hpd_rx_irq(). This function should just handle simple stuff for us (e.g. DPCD R/W). However, deferred works should still be handled by the order that dc_link_handle_hpd_rx_irq() used to be. * Change function name dm_handle_hpd_rx_irq() to dm_handle_mst_sideband_msg() to be more specific Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Add option to defer works of hpd_rx_irqWayne Lin2021-09-142-32/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why & How] Due to some code flow constraints, we need to defer dc_lock needed works from dc_link_handle_hpd_rx_irq(). Thus, do following changes: * Change allow_hpd_rx_irq() from static to public * Change handle_automated_test() from static to public * Extract link lost handling flow out from dc_link_handle_hpd_rx_irq() and put those into a new function dc_link_dp_handle_link_loss() * Add one option parameter to decide whether defer works within dc_link_handle_hpd_rx_irq() Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: update conditions to do dfp cap ext validationWenjing Liu2021-09-141-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] According to DP specs dfp cap ext validation is only for branch device withou 128b/132b channel coding support and downstream of the branch device doesn't have compression. Therefore we are adding conditions to only do dfp cap extension validation for branch devcie supporting 8b/10b channel coding only and it has no DSC passthrough capability. Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: move bpp range decision in decide dsc bw range functionWenjing Liu2021-09-142-63/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Before get dsc bw range is used to compute DSC bw range based on the given fixed bpp min/max input. The new change will merge any specs, signal, timing specific bpp range decision into this function. So the function needs to make a decision with all aspects considered. Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Fix system hang at bootLeo (Hanghong) Ma2021-09-142-11/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] During DQE's promotion test, system hang issue is found on linux system; [How] 1. Add NULL pointor check for the link in the sequence trace function; 2. Get the right link for the stream encoder before blank DP stream; Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Add DPCD writes at key pointsLeo (Hanghong) Ma2021-09-1419-15/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit "Revert "Add DPCD writes at key points" ". The following patch will fix the system hang issue. v2: squash in indentation warning fix Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Acked-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-17 19:46:05 +0000