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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
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* drm/i915: Nuke intel_get_shared_dpll_id()Ville Syrjälä2022-09-261-3/+0
* drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.cJani Nikula2022-06-171-0/+5
* drm/i915: Split shared dpll .get_dplls() into compute and get phasesVille Syrjälä2022-05-311-0/+3
* drm/i915: Pass dev_priv to intel_shared_dpll_init()Ville Syrjälä2022-04-251-2/+1
* drm/i915: Make .get_dplls() return intVille Syrjälä2022-04-251-3/+3
* drm/i915/display/tgl+: Implement new PLL programming stepJosé Roberto de Souza2022-02-181-0/+3
* drm/i915/dpll: make intel_shared_dpll_funcs internal to intel_dpll_mgr.cJani Nikula2022-01-191-45/+1
* drm/i915: drop intel_display.h include from intel_dpll_mgr.hJani Nikula2021-11-191-1/+1
* drm/i915: Nuke intel_prepare_shared_dpll()Ville Syrjälä2021-08-251-11/+0
* drm/i915: replace random CNL commentsLucas De Marchi2021-07-301-2/+1
* drm/i915: Use pipes instead crtc indices in PLL state trackingVille Syrjälä2021-03-081-4/+4
* drm/i915: Do intel_dpll_readout_hw_state() after encoder readoutVille Syrjälä2021-03-081-0/+1
* drm/i915: Use actual readout results for .get_freq()Ville Syrjälä2020-11-161-3/+5
* drm/i915: Introduce intel_dpll_get_hw_state()Ville Syrjälä2020-11-161-0/+3
* drm/i915/dg1: Add DPLL macros for DG1Aditya Swarup2020-10-151-0/+17
* drm/i915: Fix documentation for intel_dpll_get_freq()Imre Deak2020-03-091-0/+6
* drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculationImre Deak2020-03-021-3/+5
* drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.cImre Deak2020-03-021-0/+2
* drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.cImre Deak2020-03-021-0/+2
* drm/i915/tgl: Fix doc not corresponding to codeAnna Karas2019-10-251-2/+2
* drm/i915: Describe structure member in documentationAnna Karas2019-10-251-0/+5
* drm/i915/tgl: Add new pll idsVandita Kulkarni2019-07-111-5/+18
* drm/i915: Polish intel_shared_dpll_swap_state()Ville Syrjälä2019-07-111-2/+1
* drm/i915/ehl: Add support for DPLL4 (v10)Vivek Kasireddy2019-07-051-0/+6
* drm/i915: Keep the TypeC port mode fixed when the port is activeImre Deak2019-07-011-0/+3
* drm/i915/icl: Reserve all required PLLs for TypeC portsImre Deak2019-07-011-0/+9
* drm/i915: Sanitize the shared DPLL reserve/release interfaceImre Deak2019-07-011-6/+7
* drm/i915: move modesetting core code under display/Jani Nikula2019-06-171-0/+351
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