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path: root/drivers/gpu/drm/i915/display/intel_drrs.c
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* drm/i915: Rename bigjoiner master/slave to bigjoiner primary/secondaryStanislav Lisovskiy2024-06-121-2/+2
* drm/i915: Rename all bigjoiner to joinerStanislav Lisovskiy2024-06-121-3/+3
* drm/i915: pass dev_priv explicitly to TRANSCONFJani Nikula2024-06-071-1/+1
* drm/i915/display/debugfs: Fix duplicate checks in i915_drrs_statusBhanuprakash Modem2024-03-071-3/+2
* drm/i915/drrs: Refactor CPU transcoder DRRS checkBhanuprakash Modem2024-03-071-0/+9
* drm/i915/display/debugfs: New entry "DRRS capable" to i915_drrs_statusBhanuprakash Modem2024-02-261-0/+6
* drm/i915: add minimal i915_gem_object_frontbuffer.hJani Nikula2023-08-311-0/+1
* drm/i915: add a dedicated workqueue inside drm_i915_privateLuca Coelho2023-06-101-1/+3
* drm/i915: s/PIPECONF/TRANSCONF/Ville Syrjälä2023-02-171-3/+3
* drm/i915/display/misc: use intel_de_rmw if possibleAndrzej Hajda2023-02-161-9/+3
* drm/i915/display: Avoid full proxy f_ops for DRRS debug attributesDeepak R Varma2023-01-131-4/+4
* drm/i915: stop including i915_irq.h from i915_trace.hJani Nikula2022-11-111-0/+1
* drm/i915: Clean up some namespacingVille Syrjälä2022-10-071-2/+2
* drm/i915: Fix locking in DRRS debugfsVille Syrjälä2022-10-031-2/+10
* drm/i915: Make DRRS debugfs per-crtc/connectorVille Syrjälä2022-10-031-70/+64
* drm/i915: Make the DRRS debugfs contents more consistentVille Syrjälä2022-10-031-5/+5
* drm/i915: Move DRRS debugfs next to the implementationVille Syrjälä2022-10-031-0/+106
* drm/i915/bios: Split VBT data into per-panel vs. global partsVille Syrjälä2022-05-271-3/+0
* drm/i915: Move intel_drrs_compute_config() into intel_dp.cVille Syrjälä2022-03-311-54/+0
* drm/i915: Nuke intel_drrs_init()Ville Syrjälä2022-03-311-24/+0
* drm/i915: Put fixed modes directly onto the panel's fixed_modes listVille Syrjälä2022-03-311-17/+5
* drm/i915: Extract intel_edp_has_drrs()Ville Syrjälä2022-03-311-24/+0
* drm/i915: s/enable/active/ for DRRSVille Syrjälä2022-03-221-10/+12
* drm/i915: Deal with bigjoiner vs. DRRSVille Syrjälä2022-03-161-1/+15
* drm/i915: Do DRRS disable/enable during pre/post_plane_update()Ville Syrjälä2022-03-161-36/+4
* drm/i915: Schedule DRRS work from intel_drrs_enable()Ville Syrjälä2022-03-161-2/+8
* drm/i915: Don't cancel/schedule drrs work if the pipe wasn't affectedVille Syrjälä2022-03-161-9/+8
* drm/i915: Determine DRRS frontbuffer_bits ahead of timeVille Syrjälä2022-03-161-1/+10
* drm/i915: Fix DRRS frontbuffer_bits handlingVille Syrjälä2022-03-161-2/+4
* drm/i915: Put the downclock_mode check back into can_enable_drrs()Ville Syrjälä2022-03-161-3/+5
* drm/i915: Implement static DRRSVille Syrjälä2022-03-151-1/+1
* drm/i915: Enable eDP DRRS on ilk/snb port AVille Syrjälä2022-03-151-4/+4
* drm/i915: Stash DRRS state under intel_crtcVille Syrjälä2022-03-151-153/+100
* drm/i915: Eliminate the intel_dp dependency from DRRSVille Syrjälä2022-03-151-48/+32
* drm/i915: Introduce intel_drrs_type_str()Ville Syrjälä2022-03-151-2/+17
* drm/i915: Introduce intel_panel_drrs_type()Ville Syrjälä2022-03-151-7/+3
* drm/i915: Introduce intel_panel_{fixed,downclock}_mode()Ville Syrjälä2022-03-151-4/+7
* drm/i915: Nuke dev_priv->drrs.typeVille Syrjälä2022-03-151-6/+4
* drm/i915: Rename PIPECONF refresh select bitsVille Syrjälä2022-03-101-2/+2
* drm/i915: Clean up DRRS refresh rate enumVille Syrjälä2022-03-101-24/+20
* drm/i915: Polish drrs type enumVille Syrjälä2022-03-101-5/+5
* drm/i915: Program MSA timing delay on ilk/snb/ivbVille Syrjälä2022-03-101-0/+3
* drm/i915: Pimp DRRS debugsVille Syrjälä2022-03-101-5/+13
* drm/i915: Constify intel_drrs_init() argsVille Syrjälä2022-03-101-1/+1
* drm/i915: Fix up some DRRS type checksVille Syrjälä2022-03-101-2/+2
* drm/i915: Clear DP M2/N2 when not doing DRRSVille Syrjälä2022-02-011-1/+5
* drm/i915: Extract can_enable_drrs()Ville Syrjälä2022-02-011-12/+19
* drm/i915: Disable DRRS on IVB/HSW port != AVille Syrjälä2022-02-011-0/+8
* drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n()Ville Syrjälä2022-02-011-1/+4
* drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variantsVille Syrjälä2022-02-011-3/+2
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