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* doc/soc/intel/xeon_sp: Add Xeon-SP coreboot community preview guideShuo Liu2023-11-073-0/+129
| | | | | | | | | | | | The community preview branch for coreboot on latest Xeon Scalable processor is opensource at: https://review.coreboot.org/plugins/gitiles/intel-dev-pub/. Change-Id: Ie2ffc1722a4a26d6039b6642efa95bf072d896ad Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* doc/soc/amd/psp: Fix indentation in rst tableNico Huber2023-08-211-3/+3
| | | | | | | | | | | | | | The indentation resulted in the following error: …/Documentation/soc/amd/psp_integration.md:22: ERROR: Unexpected indentation. Alas, the line number refers to the embedded rst. Change-Id: I9526d023af5207602c4a4cea7704b547ef1b7bf0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* Documentation: Document a Broadwell refcode modIru Cai2023-05-311-0/+19
| | | | | | | | | | | Document how to modify the Broadwell refcode to support the Intel GbE device. Change-Id: I4f4f1e1c4ec2d79b3eb9f9c35fdc0330208e8509 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75418 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree: Drop Intel Ice Lake supportFelix Singer2023-01-193-75/+0
| | | | | | | | | | | | | | | | | | | | | | | Intel Ice Lake is unmaintained and the only user of this platform ever was the Intel CRB (Customer Reference Board). As it looks like, it was never ready for production as only engineering sample CPUIDs are supported. As announced in the 4.19 release notes, remove support for Intel Icelake code and move any maintenance on the 4.19 branch. This affects the following components and their related code: * Intel Ice Lake SoC * Intel Ice Lake CRB mainboard * Documentation Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/psp_integration.md: Update infomation with latest documentZheng Bao2022-08-121-8/+27
| | | | | | | | | | | | Update coreboot.org PSP Firmware Documentation with current internal PSP documentation. Signed-off-by: Altamshali Hirani <al.hirani@amd.corp-partner.google.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Change-Id: I677f86614b0fdc6377fb2e27932ed3a8ded27102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Remove executable flag from source codes and text filesPetr Cvek2022-07-143-0/+0
| | | | | | | | | | | Markdown, definition file and sconfig source codes don't need to be executables. This patch fixes that. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: Ic97d684318c689259f7895e3dfbd552434c3882e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* treewide: Unify Google brandingJon Murphy2022-07-041-1/+1
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Doc/soc/intel/mp_init: Mark up Reference section title as titlePaul Menzel2022-06-201-1/+1
| | | | | | | | | | | It’s a section title, so mark it up as a title as it’s done similarily in other documents. Change-Id: If9d524afe6f80ae1b2704d11617786ee923814b2 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* Documentation: Add some notes about how to integrate FSPPatrick Georgi2021-11-191-0/+12
| | | | | | | | | | | | While we don't _want_ FSP, we can't get around it sometimes. But when using it, we can still try to establish best practices to make life easier for everybody. Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Documentation: Fix spelling errorsMartin Roth2021-10-051-1/+1
| | | | | | | | | | | | These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: add Intel BroadwellIru Cai2021-09-023-0/+49
| | | | | | | | Change-Id: I0b1c29162a64030b5c100368f2471702e22b8311 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sc7280: Provide initial SoC supportRavi Kumar Bokka2021-04-152-0/+18
| | | | | | | | | | | BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* Documentation: Fix toctree and remove dead linksPatrick Rudolph2021-01-122-6/+1
| | | | | | | | Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/picasso: Move APCB generation out of picassoRob Barnes2020-09-101-38/+3
| | | | | | | | | | | | | | | | | | Move APCB generation out of the picasso makefile and into the mainboard makefile. APCB generation tends to be mainboard specific and does not belong in the soc makefile. BUG=b:168099242 TEST=Build mandolin and check for APCB in coreboot binary Build and boot ezkinil Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Doc/soc/intel: Add info about microcode updatesAngel Pons2020-08-262-0/+137
| | | | | | | | | | | | Document a general overview of when and how microcode should be updated. Also explain what microcode updates are, and why they are required. Change-Id: I6dbe25122fa45a416ed64180ef1bfb11afe676ba Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44400 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/basecode: Implement CSE update flowRizwan Qureshi2020-07-264-0/+373
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are done in this patch: 1. Get the CSE partition info containing version of CSE RW using GET_BOOT_PARTITION_INFO HECI command 2. Get the me_rw.version from the currently selected RW slot. 3. If the versions from the above 2 locations don't match start the update - If CSE's current boot partition is not RO, then * Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. * Send global reset command to reset the system. - Enable HMRFPO (Host ME Region Flash Protection Override) operation mode using HMRFPO_ENABLE HECI command - Erase and Copy the CBFS CSE RW to CSE RW partition - Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command - Trigger global reset - The system should boot with the updated CSE RW partition. TEST=Verified basic update flows on hatch and helios. BUG=b:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDsRaul E Rangel2020-05-181-0/+45
| | | | | | | | | | | | | BUG=b:147042464 TEST=Boot trembyle to OS Signed-off-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ife48d5268230f70c6a6f4a56c1f0d05b6c924891 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41381 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Steal no memory for disabled IGDChristian Walter2020-04-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | Set IgdDvmt50PreAlloc to zero if InternalGfx is disabled. It's 'correct' to do it like this, otherwise the FSP would always allocate memory for the IGD even if it is disabled. In addition the FSP enables the graphics panel power even if no IGD is present which leads to a crashing FSP. Thus, if no IGD is present we switch off the panel via UPDs. Refer to this issue on IntelFSP for details: https://github.com/IntelFsp/FSP/issues/49 Tested on: * CFL platform with IGD * CFL platform without IGD Change-Id: I6f9e0f9855224614471d8ed23bf2a9786386ddca Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Documentation: soc/amd/psp: Use real table markupEvgeny Zinoviev2020-02-191-129/+136
| | | | | | | | | | | | Currently, tables on this page are formatted as code blocks with ASCII tables. Make it real beautiful tables. Change-Id: I3c46477352b8151f3b0fb0616f909531a0a15c34 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
* treewide: capitalize 'BIOS'Elyes HAOUAS2020-02-171-1/+1
| | | | | | | | | | Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'. Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Documentation/soc/amd/family17: Update to match current designMarshall Dawson2020-02-111-46/+71
| | | | | | | | | | | | | The Picasso no longer intends to implement a hybrid romstage, opting instead for a more traditional bootblock/romstage/ramstage. Update the documentation to reflect this. Clarify additional details that have come to light since the last revision. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I6c98c007ddb8a4a05810f19e4215bde719de7bb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Documentation/soc/amd: Add PSP integration informationMarshall Dawson2020-02-114-9/+387
| | | | | | | | Change-Id: I05187365158eb5c055be0d4a32f41324d2653f71 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* docs: intel fsp: add memory retraining bug on SPS systemsMichael Niewöhner2019-11-191-0/+6
| | | | | | | | | | FSP2.0 forces MRC retraining on cold boot on Intel SPS systems. Change-Id: I3ce812309b46bdb580557916a775043fda63667f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation: Add amd_blobs license agreement textMarshall Dawson2019-10-302-0/+71
| | | | | | | | | | | | | | | | | AMD has generated a simpler and more flexible license agreement for using proprietary precompiled binary images. The new agreement is intended to cover all blobs in the directory structure below where the license resides and eliminates any unique agreements previously provided for individual products. Add a description of the repo, as well as the license agreement it contains. Change-Id: Ia3dbc1a5259a2512281ea87b7e55fb3134b3b3c5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* sc7180: Provide initial SoC supportT Michael Turney2019-10-213-0/+27
| | | | | | | | Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mainboard/ocp/monolake: Hide IIO root ports before memory initAndrey Petrov2019-10-161-0/+7
| | | | | | | | | | | | | | It turned on some SKUs FSP hangs in Notify stage if IIO root ports are disabled after MemoryInit. To address that hide IIO root ports earlier in romstage. TEST=the patch was ran on affected HW and success was reported Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* Documentation/soc/amd: Add Family 15hRichard Spiegel2019-10-012-0/+50
| | | | | | | | | | | | | Create documentation for AMD Family 15h. BUG=none. TEST=none. Change-Id: Iaab4edc431329a691283121494595f3797c566c6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* Documentation/soc/intel/fsp: Add link for external FSP2.1 specSubrata Banik2019-09-041-0/+2
| | | | | | | | Change-Id: I5d1abd6252bda2be09285cd878a483f055abcd7b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35238 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation: Add FSP bugsPatrick Rudolph2019-07-151-0/+43
| | | | | | | | | | | | | As Intel doesn't even document known bugs add a list of FSP bugs here. Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/block/cpu: remove unused USE_COREBOOT_NATIVE_MP_INITArthur Heymans2019-07-101-3/+3
| | | | | | | | | | | | | | | | Only CONFIG_USE_INTEL_FSP_MP_INIT makes a difference whether native MP init is used or not. Also make USE_INTEL_FSP_MP_INIT mutually exclusive with USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI as this option requires coreboot to set up AP and publish PPI based on it. Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33357 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* doc/mb/upsquared: Add documentationFelix Singer2019-06-174-0/+140
| | | | | | | | | | | This patch adds documentation about the UP² mainboard and the IFWI used by Apollolake platform. Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* Documentation/soc/amd: Add Family 17hMarshall Dawson2019-06-133-0/+233
| | | | | | | | | | | | Begin a directory for AMD soc devices and add an explanation of how Family 17h works. Newer AMD systems use a unique paradign for initializing the x86 processors. Change-Id: I7bd8649996add80747f6a60b9dfd35a94a560be1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* Documentation: Add FITPatrick Rudolph2019-04-304-0/+193
| | | | | | | | | | Describe the Firmware Interface Table and reference useful documentation. Change-Id: I00abc1fd13be7b48d56ba8cb65d2542ed07f9017 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Documentation/soc/intel: Add MP Initialization documentSubrata Banik2019-03-262-0/+57
| | | | | | | | | | | This patch provides documentation for MP initialization option available in coreboot. Change-Id: I055808e2ddf03663e1ec5d3d423054d1caa911cb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation/soc/intel/fsp: Move mp_service_ppi document in corrct directorySubrata Banik2019-03-194-4/+5
| | | | | | | | | | | | | This patch moves mp service ppi document from icelake/MultiProcesorInit.md to ppi/mp_service_ppi.c. Change-Id: I1bbaeb2644f219b5a1fda0c7c4b594184d53958c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31840 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPISubrata Banik2019-03-122-0/+13
| | | | | | | | | | | | Some new feature added into FSP specification to perform dispatching of external PPI service from boot firmware (coreboot) to FSP. Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31839 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/soc/intel: Add documentation for Intel FSPSubrata Banik2019-03-122-0/+14
| | | | | | | | | | | | This patch combines open source documentation for Intel FSP specification. Change-Id: I3a8bc0198a1e01ec019139b728834713978501ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31838 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Documentation/soc/intel/icelake: Fix references between documentsJonathan Neuschäfer2018-12-191-2/+2
| | | | | | | | Change-Id: Ifbdab15b1183998712f92d1f2f5340d2ad1451dc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
* Documentation/soc/intel/icelake: Fix indentation in numbered listJonathan Neuschäfer2018-12-191-12/+12
| | | | | | | | | | | Without this patch, the numbers restart at 1 at several points in the HTML output. Change-Id: Ie3634775ed9f993b1181785c58d72834183336e1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
* Documentation/../../icelake: Add Ice Lake coreboot development documentationSubrata Banik2018-11-272-0/+76
| | | | | | | | | | | | | | | | Add documentation for Ice Lake processor family coreboot development. Documented so far: * What is Ice Lake * Development Strategy * Create coreboot Image * Flashing coreboot Change-Id: Ief4df6ca11f95b75ecddeb560f7887bfadced086 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation: Fix markdown highlightingPatrick Rudolph2018-10-221-2/+2
| | | | | | | | | | | Fix some code blocks that use invalid Markdown syntax. Change-Id: I8cfe63b2c21ae93923f88bbf7ef4cfb8dccdb5ef Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/29207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Documentation: Add code_development_model.md to soc/intel/index.mdTom Hiller2018-07-241-0/+1
| | | | | | | | | | | Fixes Sphinx WARNING document isn't included in any toctree Change-Id: I956ed23d87c7cbd65383cc64a6af7161e90d6611 Signed-off-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-on: https://review.coreboot.org/27593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Documentation/soc/intel: Add common code design documentMaulik V Vaghela2018-06-302-0/+101
| | | | | | | | | | | | | | | | | | | Add common code design document support Intel SoCs such as Skylake, Cannonlake and Apollolake onwards. Documented items: *Introduction *Design Principle *Common code development and status *Common code structure *Benifits Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Documentation: Add cavium SoC and mainboardPatrick Rudolph2018-06-195-0/+147
| | | | | | | | | | | | | | | * Add documentation for CN81XX SoC * Add documentation for CN81XX EVB SFF mainboard * Add documentation for BDK * Add documentation for BOOTROM and BOOTBLOCK behaviour * Alphabetically sort vendors Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Documentation: Update index.md and move filesPhilipp Deppenwiese2018-05-305-0/+106
* Add more subdirectories and index.mds. * Move "getting started" and "lessons" into sub-directories. * Move "NativeRaminit" into northbridge/intel/sandybridge folder. * Move "MultiProcessorInit" into soc/intel/icelake folder. * Reference new files Change-Id: I78c3ec0e8bcc342686277ae141a88d0486680978 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26262 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-06 20:00:48 +0000