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* device/mdio: Provide helper functions for read and writeWerner Zeh2022-11-241-0/+3
| | | | | | | | | | | | | This patch provides helper functions to read or write a register via the MDIO bus. They can be used from drivers to easily access registers on the MDIO bus. Change-Id: I293d93435d27269a071b4b9b94a1b55307c575a7 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69611 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/device + util/sconfig: Introduce new device 'mdio'Mario Scheithauer2022-11-243-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the available device paths with a new device 'mdio'. MDIO is the 'Management Data Input/Output' called interface which is used to access an Ethernet PHY behind a MAC to change settings. The real payload data path is not handled by this interface. To address the PHY correctly on the MDIO bus, there is a 5 bit address needed, which often can be configured via pins on the mainboard. Therefore, the new introduced device has an 'addr' field to define its address. If one wants to use a MDIO device in devicetree, the syntax is straight forward (example): device mdio 0x2 on end As the MDIO interface is driven by the MAC, most likely this MDIO device will be hooked in as a child device of the (PCI attached) MAC device. With the new introduced ops_mdio a new interface is added to provide an API for read and write access over MDIO. Change-Id: I6691f92c4233bc30afc9029840b06f74bb1eb4b2 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69382 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/include: Remove unnecessary space after castsElyes Haouas2022-11-221-1/+1
| | | | | | | | Change-Id: Ie6def0dab9ac37c0938b73d27148a49531c6b17f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69802 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/pciexp: add pcie_find_dsn()Jonathan Zhang2022-11-201-0/+3
| | | | | | | | | | | Add pcie_find_dsn() to detect and match PCIe device serial number. In addition, vendor ID is matched when provided. Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* soc/intel/meteorlake: Add Meteor Lake MCH device IDSridhar Siricilla2022-11-181-0/+1
| | | | | | | | | | | | | | | | | Add Meteor Lake MCH device ID 0x7d15. TEST=Build and verify boot on MTL RVP With patch, coreboot log: `[DEBUG] MCH: device id 7d15 (rev 00) is Meteorlake P` Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel: Add Meteor Lake IGD device id 0x7d45Ravi Sarawadi2022-11-151-3/+4
| | | | | | | | | | | | | | Add new IGD device. Reference: EDS Vol 1 (640228) Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Change-Id: Iad69f547a981390ef3749256e9fd9bcfc106fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* inc/dev: Add definitions for Link Capability and Slot CapabilityTim Chu2022-11-131-0/+3
| | | | | | | | | | | Add definitions for Link Capability and Slot Capability and these definitions may be used in smbios type 9. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Id66710d5569a7247d998cab20c2e41f2e67712cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/69092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* device/xhci: Factor out `struct xhci_usb_info`Robert Zieba2022-11-091-0/+14
| | | | | | | | | | | | | | This commit factors out `struct xhci_usb_info` from intel specific code as it will be useful on other platforms. BUG=b:186792595 TEST=Builds for volteer Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* device/xhci: Factor out common PORTSC codeRobert Zieba2022-11-091-1/+37
| | | | | | | | | | | | | | This commit factors out some code for XHCI port status values. BUG=b:186792595 TEST=Built coreboot for volteer device Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* include/device/pci_def.h: Add some PCIe DPC/AER definitionsTim Chu2022-11-041-0/+19
| | | | | | | | | | | | | | * Add DPC related definitions which are defined in 7.9.14 of PCIe 6.0 spec. * Add AER related definitions which are defined in 7.8.4 of PCIe 6.0 spec. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ifb6722c326ef69ef1bf3b1c2c1d5bc0cb29d7c12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69106 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* treewide: Add 'IWYU pragma: export' commentElyes Haouas2022-11-034-9/+10
| | | | | | | | | | | This pragma says to IWYU (Include What You Use) that the current file is supposed to provide commented headers. Change-Id: I482c645f6b5f955e532ad94def1b2f74f15ca908 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* device/mmio: add clr/setbitsXp macrosMichael Niewöhner2022-11-021-0/+15
| | | | | | | | | | Add clr/setbits*p macros as pendant to read/write*p. Change-Id: I5b10ccab97c3a372051050b28ada854baec91d18 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68790 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Add Raptor Lake device IDsLawrence Chang2022-10-251-0/+1
| | | | | | | | | | | | | | | | Add system agent ID for RPL QDF# Q271 TEST=Tested by ODM and "MCH: device id a71b (rev 01) is Unknown" msg is gone Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com> Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* device: Drop unused ADL-N UFS PCI Device IDSubrata Banik2022-10-121-3/+0
| | | | | | | | | | | | | | | | This patch drops unused ADL-N UFS PCI Device ID macro `PCI_DID_INTEL_ADP_UFS`. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I24e4a1a871763473df4d610b13e8a3a754470233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/nivviks: Enable ISH driver and firmware nameMeera Ravindranath2022-10-111-0/+1
| | | | | | | | | | | | | | | BRANCH=none BUG=b:234776154 TEST=build and boot Nirwen UFS, copy ISH firmware to host file system /lib/firmware/intel/adln_ish.bin check "dmesg |grep ish", it should show: ish-loader: ISH firmware intel/adlnrvp_ish.bin loaded Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I89782b0b7dde1fca0130472a38628e72dfd5c26c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* include/device/device_util.c: add predicates for pci devicesFabio Aiuto2022-10-061-0/+3
| | | | | | | | | | | | | add functions to check whether a device is enabled pci device or a pci device on a specific bus number. TEST: compile and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I3257c8404017372f6cdd9f6cf9453502447343a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68101 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/gfx: Add missing CML-U IGD device IDsMichał Żygowski2022-10-061-0/+2
| | | | | | | | | | | | | | | | | | Intel Core i5-10210U can have the following IGD Device IDs 0x9B21/0x9B41/0x9BAC/0x9BCA/0x9BCC according to Intel ARK. Some of these IDs were not present in coreboot source nor hooked to the common graphics driver. Add the missing IDs so that the graphics driver will probe on the mentioned processor and detect the framebuffer. TEST=Boot Protectli VP4650 with i5-10210U and see framebuffer is detected when using FSP GOP and libgfxinit. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iee720a272367aead31c8c8fa712bade1b6e53948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67975 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/path.h: use functions for enabled cpu selectionFabio Aiuto2022-09-291-0/+2
| | | | | | | | | | | | | | Add function defs and prototypes of functions checking whether a device is {a cpu,an enabled cpu} TEST: compile test and qemu executed successfully with coreinfo payload Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: Iabc0e59d604ae4572921518a8dad47dc3d149f81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Revert "drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver"Subrata Banik2022-09-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 510a55d4eeaeb32047c17328ef238b55b89e7296. Reason for revert: Observed `missing read resource` issue for cnvi device BUG=b:244687646 TEST=No error seen in AP log while booting Google/rex Without this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [ERROR] GENERIC: 0.0 missing read_resources [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done With this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1e881313729f1088cffa7c161722ee79bb9acc49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67566 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* device: Clear lane error statusWilson Chou2022-09-121-0/+5
| | | | | | | | | | | | | | | | | | | | | Refer to PCI Express Base rev6.0 v1.0, 4.2.7 Link Training and Status State Rules, Lane Error Status is normal to record the error when link training. To make sure Lane Error Status is correct in OS runtime, add a Kconfig PCIEXP_LANE_ERR_STAT_CLEAR that clears the PCIe lane error status register at the end of PCIe link training. Test=On Crater Lake, lspci -vvv shows bb:01.0 PCI bridge: Intel Corporation Device 352a (rev 03) (prog-if 00 [Normal decode]) Capabilities: [a30 v1] Secondary PCI Express LnkCtl3: LnkEquIntrruptEn- PerformEqu- LaneErrStat: LaneErr at lane: 0 Signed-off-by: Wilson Chou <Wilson.Chou@quantatw.com> Change-Id: I6344223636409d8fc25e365a6375fc81e69f41a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* soc/intel/common/smbus: Add missing ID for GLKSean Rhodes2022-09-081-0/+1
| | | | | | | | | | PCI ID taken from Intel doc #569262. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I31d4b7edf3288794c86a6d2b78acdc4cf0ac611f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/commmon/fast_spi: Add missing ID for GLKSean Rhodes2022-09-081-0/+1
| | | | | | | | | | | PCI ID taken from Intel doc #569262. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5812e536f3e1c49a272a0b337cc69f3d8f30677f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67402 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* pciexp_device: Propagate above-4G flag to all hotplug devicesNico Huber2022-09-041-0/+4
| | | | | | | | | | | | | | | | The `IORESOURCE_ABOVE_4G` flag was only explicitly set for our dummy device that reserves resources behind a hotplug port. The current re- source allocator implicitly extends this to all devices below the port, including real ones. Let's make that explicit, so future changes to the allocator can't break this rule. Change-Id: Id4c90b60682cf5c8949cde25362d286625b3e953 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66719 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* device/i2c_bus: Add routines to read and write multiple bytesWerner Zeh2022-09-041-0/+14
| | | | | | | | | | | | | Some devices require that several bytes are written with a single I2C write command. Extend the i2c_bus interface functions and add both, read and write for more than one byte at a defined byte offset. Change-Id: I0eec2e1d4185170f02b4ab35aa6546dc69569303 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67098 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* device/dram: Add function to convert freq to MT/s for (LP)DDR5Matt DeVillier2022-08-251-0/+20
| | | | | | | | | | | | | | | | | As the frequency field in the SMBIOS type 17 table is deprecated, we need to provide the maximum and configured speed in MT/s. Add a method to convert from frequency to MT/s using a lookup table. BUG=b:239000826 TEST=Build and verify with other patches in train Change-Id: I0402b33a667f7d72918365a6a79b13c5b1719c0d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* pciexp_device: Introduce pciexp_find_ext_vendor_cap()Nico Huber2022-08-172-0/+3
| | | | | | | | | | | | Vendors can choose to add non-standard capabilities inside a Vendor-Specific Extended Capability. These are identified by the Extended Capability ID 0x0b. Change-Id: Idd6dd0e98bd53b19077afdd4c402114578bec966 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* pciexp_device: Join pciexp_find_(next_)extended_cap() APIsNico Huber2022-08-171-3/+2
| | | | | | | | | | | | | | | Move the `offset` parameter into pciexp_find_extended_cap(). If it's called with `0`, we start a new search. If it's an existing offset, we continue the search. This makes it easier to search for multiple occurences of a capa- bility in a single loop. Change-Id: I80115372a82523b90460d97f0fd0fa565c3f56cb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Fix Alder Lake and Raptor Lake Device ID'sMaximilian Brune2022-08-121-58/+44
| | | | | | | | | | | | | | - ADP_P_* -> RPP_S_* (got mixed up I guess) - Remove duplicates of ADP_S_ESPI_* - Add infix _ESPI_ to all ADP_S device ID's Document: 619362 Change-Id: Ic18ecbd420fc598f0ef6e3cf38e987ac3ae6067e Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66629 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add missing ADL-S device identificationMaximilian Brune2022-08-121-0/+3
| | | | | | | | | | | | | | R680E, Q670E, H610E are the ADL-S IoT variants TEST=Boot ADL-S RVP DDR5 and see silicon info is reported as PCH: AlderLake-S R680E Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I1804994b4b72f0484eabb15323736679d2668078 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* include: Add SPDX identifiers to files missing themMartin Roth2022-08-111-0/+2
| | | | | | | | | | | This adds SPDX identifiers to the remaining source files in the include directory that don't already have them. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I0dbf4c839eacf957eb6f272aa8bfa1eeedc0886f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66501 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* pci_device: Add a function to find PCI capability ID recursivelyBill XIE2022-08-071-0/+1
| | | | | | | | | | | | | Some PCI capabilities should only be enabled if it is available not only on a device, but also all bridge upstream of it. Checking only the device and the bridge just above it may not be enough. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I1237d3b4b86dd0ae5eb586e3c3c407362e6ca291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66383 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include: Add SPDX-License-Identifiers to files missing themMartin Roth2022-08-0112-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds SPDX-License-Identifiers to all of the files in src/include that are missing them or have unrecognized identifiers. Files that were written specifically for coreboot and don't have license information are licensed GPL-2.0-only, which is the license for the overall coreboot project. Files that were sourced from Linux are similarly GPL-2.0-only. The cpu/power files were committed with source that was licensed as GPL-2.0-or-later, so presumably that's the license for that entire commit. The final file, vbe.h gives a pointer to the BSD-2-Clause license at opensource.org. Change-Id: I3f8fd7848ce11c1a0060e05903fb17a7583b4725 Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* include/device/device.h: Remove unneeded blank line after '{'Elyes HAOUAS2022-07-171-1/+0
| | | | | | | | | Change-Id: I3e439a293c6b4a806cae7c6a56d28e61f7e57044 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61555 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* soc/intel/common/graphics: Add another Meteor Lake device IDWonkyu Kim2022-07-071-1/+2
| | | | | | | | | | | | | Add 0x7d55 as another ID for Meteor Lake graphics controllers. TEST=Boot with MTL silicon to check coreboot log for DID2 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
* soc/intel: Add Raptor Lake device IDszhixingma2022-06-281-1/+4
| | | | | | | | | | | | | | | | | | Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Booted to OS on adlrvp + rpl silicon Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Drop LOG_MEM/IO_RESOURCEKyösti Mälkki2022-06-261-17/+0
| | | | | | | | | | | | The only callsites in intel/xeon_sp were replaced with calls to log_resource() and functionality is provided with LOG_RESOURCE() now. Change-Id: Ie44694f7a0b119d10f1bef9158fa30e71c312a55 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55478 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* resource: Add helpers for memory resourcesKyösti Mälkki2022-06-261-0/+56
| | | | | | | | | | | These should help to make the reviews as platforms remove KiB scaling. Change-Id: I40644f873c0ea993353753c0ef40df4c83233355 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device: Add fixed_io_range_flags() and helpersKyösti Mälkki2022-06-261-6/+23
| | | | | | | | | | | | | | | | | Function fixed_io_resource() and alias io_resource() were previously unused. Unlike previously, IORESOURCE_STORED flag needs to be set by the caller, when necessary. For fixed resources, fields alignment, granularity and limit need not be initialised, as the resource cannot be moved. It is assumed the caller provides valid base and size parameters. Change-Id: I8fb4cf2dee4f5193e5652648b63c0ecba7b8bab2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device: Add fixed_mem_range_flags() and helpersKyösti Mälkki2022-06-261-3/+34
| | | | | | | | | | | | | | | | Unlike fixed_mem_resource_kb() the arguments are not in KiB. This allows coccinelle script to assign the base and size without applying the KiB division or 10 bit right-shift. Unlike with fixed_mem_resource_kb() the IORESOURCE_STORED flag is passed in the flags parameter until some inconsistencies in the tree get resolved. Change-Id: I2cc9ef94b60d62aaf4374f400b7e05b86e4664d2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel: Add Meteor Lake SA device IDSubrata Banik2022-06-221-0/+1
| | | | | | | | | | | | | | | Add Meteor Lake SA device ID 0x7d14 (4+8, 15W). BUG=b:224325352 TEST=Able to build MTL SoC and verified SA DID is now shown proper. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-221-13/+13
| | | | | | | | | | | | There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake/report_platform.c: Add ADL-S identificationMichał Żygowski2022-06-171-0/+15
| | | | | | | | | | | | | Based on DOC #619501, #619362 and #618427 TEST=Boot MSI PRO Z690-A DDR4 WIFI and see the silicon info is reported as ADL-S. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8051113515ef63fc4687f53d25140a3f55aadb6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driverSubrata Banik2022-06-031-4/+4
| | | | | | | | | | | | | | | | | | | | | This patch removes the MTL CNVi DIDs macros from IA common code and is added into the generic wifi driver. As per Intel Connectivity Platform BIOS Guide, Connectivity Controller IP for MTL-P is `Magnetar` and supported CRF is `Typhoon Peak 2`. Previously Garfield Peak DIDs for Alder Lake SoC also added similarly to generic wifi drivers. BUG=b:224325352 TEST=Able to build and boot on MTL emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib98762749c71f63df3e8d03be910539469359c68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
* dev/i2c_bus: Add declaration, implementation of i2c_dev_detect()Matt DeVillier2022-05-311-0/+5
| | | | | | | | | | | | | | | | | This patch adds the I2C equivalent of an SMBus quick write to an I2C device, which is used by some I2C drivers as a way to probe the existence (or absence) of a certain device on the bus, based on whether or not a 0-byte write to an I2C address is ACKed or NACKed. i2c_dev_detect() is implemented using the existing i2c bus ops transfer() function, so no further work is needed for existing controller drivers to utilize this functionality. Change-Id: I9b22bdc0343c846b235339f85d9f70b20f0f2bdd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* device: Add log_resource()Kyösti Mälkki2022-05-241-0/+9
| | | | | | | | | | | This will replace LOG_{MEM/IO}_RESOURCE macros once the new resource constructors are available. Change-Id: I21b030dc42dcb8e462b29f49499be5fd31ea38f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/ehl: Use defines for Ethernet controller IDsMario Scheithauer2022-05-201-0/+5
| | | | | | | | | | Use defines for a better reading of the code. Change-Id: I8e696240d649c0ea2341b8f04b62eebffebc1d57 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64519 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/wifi/generic: Add new device IDBora Guvendik2022-05-161-0/+1
| | | | | | | | | | New device id 0x51f1 is added. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I695309d529a117bad68fc89a7f136e69cecb95d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel: Add Raptor Lake device IDsBora Guvendik2022-05-161-3/+56
| | | | | | | | | | | | | | | | Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
* device/dram/common.h: Use C over CPPArthur Heymans2022-05-111-5/+5
| | | | | | | | | | | This fixes building with clang. Change-Id: Ia8511ab46184aa0d8ee3a79c3ef22614aeb61298 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* include/device/i2c_simple: add i2c_2ba_read_bytes functionFelix Held2022-04-271-0/+28
| | | | | | | | | | | | | | | | | To read data from an I2C EEPROM that uses 2 byte offsets or any other I2C device that uses 2 byte offsets, first the two offset bytes are sent to the device and then the data bytes are read from it. The main difference to the existing i2c_read_bytes is that that function will only send one offset byte to the I2C device. TEST=Reading the contents of an EEPROM on the AMD Chausie board works Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I224e434bb2654aabef6302c1525112e44c4b21fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/63791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-20 22:30:50 +0000