summaryrefslogtreecommitdiffstats
path: root/src/include/device
Commit message (Collapse)AuthorAgeFilesLines
* soc/intel/common: Add ADL_N ID 5 0x4618Sean Rhodes2024-02-191-0/+1
| | | | | | | | | | This patch adds ADL N 4-core MCH ID 0x4618. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I47bd8fa991a48d30be4975b7965f2c3c859836dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/80487 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device: drop unused soft_reserved_ram_resource macroFelix Held2024-02-141-3/+0
| | | | | | | | | | | | The unused soft_reserved_ram_resource expanded to the non-existent fixed_mem_resource function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b454175c6530e539aa24dffb771368b0aea6da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* include/device/azalia_device.h: Add enum for misc fieldNicholas Chin2024-02-131-2/+7
| | | | | | | | | | | | | | | | The HDA specification defines bits 11:8 of the Configuration Default register as a miscellaneous field for other jack information. Only bit 8 has a standard meaning, and indicates that the jack does not have presence detect capability. Add an enum for use in the AZALIA_PIN_DESC macro to indicate this field. Note that many vendor firmwares set bits 11:9 to non zero values despite them being reserved in the specification, and their meaning in these cases is not well known. Change-Id: I70cbfca8541828a1e0c7280887060c04e4c71721 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* drivers/wifi: Add MTCL function to ACPI SSDTDavid Ruth2024-02-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MTCL function provides a country list to the Linux kernel via an ACPI function in SSDT for MediaTek WiFi chipsets that are capable of operating on the 6GHz band. The country list is used to selectively disable 6GHz and 5.9GHz operation based on the country the device is operating in. The function needs to read a binary file and send it as a package via the MTCL method in SSDT for PCIe WiFi with MediaTek chipsets. Change Summary: * Add src/drivers/wifi/generic/mtcl.c to abstract functionaltity related to MTCL * Add write_mtcl_aml function to convert the byte data into the format expected by the MTCL functionality in the Linux kernel. * Add validate_mtcl function to validate that the byte data read in from a file is in the expected format. * Add write_mtcl_function function to read a binary file called "wifi_mtcl".bin" from cbfs, then call validate_mtcl to verify that it is in an expected format, and if so write the aml via acpigen * Add config flag DRIVERS_MTK_WIFI to src/drivers/wifi/generic in order to include MediaTek WiFi specific functionality * Add config flag USE_MTCL which depends on DRIVERS_MTK_WIFI and enables including the specific ACPI function defined in SSDT * Add config flag CONFIG_MTCL_CBFS_FILEPATH which depends on DRIVERS_MTK_WIFI which enables configuring the file to add as "wifi_mtcl.bin" * Add a call to write_mtcl_function to src/drivers/wifi/generic/acpi.c to include the MTCL function in SSDT for MTK WiFi devices when USE_MTCL is enabled. * Add MediaTek VID to src/include/device/pci_ids.h. BUG=b:295544553 TEST=Add Kconfig entry USE_MTCL for pujjo TEST=Add wifi_mtcl_defaults.bin blob to cbfs TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage` TEST=Verify that MTCL defined in the file is present: TEST=`acpidump -b` TEST=`iasl ssdt.dat` TEST=`less ssdt.dsl` TEST=Search for MTCL Signed-off-by: David Ruth <druth@chromium.org> Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80170 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* device/device.h: Rename busses for clarityArthur Heymans2024-01-312-11/+6
| | | | | | | | | | This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard2024-01-311-2/+0
| | | | | | | | | | | | | | | | | | | | | | | Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* device/device.h: Drop multiple linksArthur Heymans2024-01-291-4/+3
| | | | | | | | | | | | | | | | | | | | Multiple links are unused throughout the tree and make the code more confusing as an iteration over all busses is needed to get downstream devices. This also not done consistently e.g. the allocator does not care about multiple links on busses. A better way of dealing multiple links below a device is to feature dummy devices with each their respective bus. This drops the sconfig capability to declare the same device multiple times which was previously used to declare multiple links. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Reviewed-on: https://review.coreboot.org/c/coreboot/+/78328 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* device: Add a helper function to add a downstream busArthur Heymans2024-01-291-3/+3
| | | | | | | | | | | | Adding downstream busses at runtime is a common pattern so add a helper function. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ic898189b92997b93304fcbf47c73e2bb5ec09023 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel: Add Lunar Lake device IDsAppukuttan V K2024-01-241-0/+72
| | | | | | | | | | | | | | | | Added Lunar Lake specific CPU and PCIE device IDs Reference: Lunar Lake External Design Specification Volume 1 (734362) Change-Id: Ic0aae6fd7aa8ba3a6a794f8af5ecf3967509b704 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79899 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
* device/device_util: Add method to retrieve the domainPatrick Rudolph2024-01-241-0/+1
| | | | | | | | | | | | | | Add a function to return the PCI domain device for the specified device. On multi PCI domain platforms this function allows to determine which domain and thus which socket the PCI device belongs to. Change-Id: I0068b82e139fe7a35e6b1b91b7d386b750c80748 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80090 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* device: Add inline method to identify PATH_ROOTPatrick Rudolph2024-01-241-0/+9
| | | | | | | | | | | Add and use inline method to identify the root device. Change-Id: I394c8668245bcfea6414b8ca5f14ef8135897e59 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80169 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* device/device.h: Drop acpi_inject_dsdtArthur Heymans2024-01-221-1/+0
| | | | | | | | | | | | | This is now unused in the tree and filling SSDT should always be used. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iffefc865901b15fa299931b6ed4c27a9e3a1c330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* device_util: Drop unused function bus_pathArthur Heymans2024-01-211-1/+0
| | | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id23a291af20473c3b3e67178b66fcde920d49984 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* device/device.h: Fix outdated commentArthur Heymans2024-01-181-8/+1
| | | | | | | | | | | | | | LAPIC devices in devicetree is not possible any longer since commit 3eba665 "util/sconfig: Remove lapic devices from devicetree parsers". TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I02192c9a11c35d9625837a8a9f3ba798ff0ae611 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* device: Add support for multiple PCI segment groupsFelix Held2024-01-163-1/+16
| | | | | | | | | | | | | | | | | | Add initial support for multiple PCI segment groups. Instead of modifying secondary in the bus struct introduce a new segment_group struct element and keep existing common code. Since all platforms currently only use 1 segment this is not a functional change. On platforms that support more than 1 segment the segment has to be set when creating the PCI domain. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* include/device/pci_mmio_cfg: assert CONFIG_ECAM_MMCONF_BUS_NUMBER != 0Felix Held2024-01-151-0/+4
| | | | | | | | | | | | | Make sure that CONFIG_ECAM_MMCONF_BUS_NUMBER is non-zero when the ECAM_MMCONF_SUPPORT Kconfig option is selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic102b7dca9ffebb2d384a068a1fb1f4b6fb6c5f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79933 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb/intel/bd82x6x: Add defines for PCI IDsPatrick Rudolph2023-12-231-0/+44
| | | | | | | | | | Add and use defines for 6 series and 7 series PCH PCH IDs. Change-Id: I4de37d5817766b9bc4f5c2d4d472d3c456b14b29 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79546 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/ipmi to lib: Fix misspellings & capitalization issuesMartin Roth2023-12-133-3/+3
| | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I926ec4c1c00339209ef656995031026935e52558 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device: drop HAVE_ACPI_TABLES guardsFelix Held2023-11-171-2/+1
| | | | | | | | | | | There's no need to remove the corresponding fields from the device_operations struct when HAVE_ACPI_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iac20b6cdc44a5280566ee7003a5ef6fbe913b099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78990 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device: drop GENERATE_SMBIOS_TABLES guardsFelix Held2023-11-171-2/+2
| | | | | | | | | | | There's no need to remove the corresponding fields from the device_operations struct when GENERATE_SMBIOS_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa24d1fd211c263b788046e63de3dd5c54cba801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* include/device/dram: Add SPD lengths for DDR3 to DDR5Martin Roth2023-10-254-3/+12
| | | | | | | | | | | | | | DDR2 already had a define to specify the SPD length, but other memory types did not. This led to the value being coded into other locations. Unify the definition for DDR2 to DDR5 and put the value at the top of the respective header file. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id13b9c5d311984d4a98b831a8746d1659724aa96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* device/device.h: Rename pci_domain_scan_busArthur Heymans2023-10-201-1/+1
| | | | | | | | | | | | | | On all targets the domain works as a host bridge. Xeon-sp code intends to feature multiple host bridges below a domain, hence rename the function to pci_host_bridge_scan_bus. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
* device/pci_def.h: Add more bitsPatrick Rudolph2023-10-061-0/+5
| | | | | | | | | | | Add more fields for PCIe slots status and link control and slot capabilities. Change-Id: I64e40ea6bd731cd52ce006224b7c3091d5ef3aac Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* acpi: Add functions to declare ARM GIC V3 hardwareArthur Heymans2023-09-181-0/+9
| | | | | | | | | | | | | | | For GICD and GICR a SOC needs to implement 2 callbacks to get the base of those interrupt controllers. For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3 devices in a similar fashion to how x86 lapics are added. It's up to the SOC to add those devices to the tree. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Update Raptor Lake graphics device IDsBora Guvendik2023-09-181-3/+7
| | | | | | | | | | | | | | | | | | | Added Raptor Lake U graphics device ids. Renamed Raptor Lake U graphics device ids that were marked as Raptor Lake P. Added Raptor Lake P graphics device ids. References: RaptorLake External Design Specification Volume 1 (640555) TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I44734f927764f872b89e3805a47d16c1ffa28865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77898 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intelblocks/{pmc,p2sb}: Add missing RPL-S PCH IDs for PMC and P2SBMichał Żygowski2023-09-151-0/+2
| | | | | | | | | | | | The PMC and P2SB IDs for Raptor Lake-S PCH were missing. Add them based on doc 619362 rev 2.2. Change-Id: I5de00adf2d87cf50571abb02b28e7feebdc3911e Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77448 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* acpi/soundwire.[ch]: Fix dpn entry array overrunMartin Roth2023-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In soundwire.h, SOUNDWIRE_DPN MIN & MAX are set to 1 and 14. When creating the dpn array, the length was set to MAX - MIN or 13, numbered 0 to 12. When accessing the array, the code was bailing out if a value greater than MAX was trying to be accessed, so the array was able to be overrun by two structure lengths. Fix this problem by: 1) Not subtracting the MIN value when creating the array, which does waste a little space. If anyone wants to refactor the code to fix that, please feel free. 2) Breaking out of the loop when the port is equal to the MAX port number instead of just when it's greater than the max port number. Reported-by: Coverity (CID:1429766 & CID:1429771) Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0841bb8c9869fe9f53958f05614848785a98b766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* drivers/wifi: Add PCI ID for Misty Peak WLAN moduleSubrata Banik2023-09-051-0/+1
| | | | | | | | | | | | This patch adds support for Intel WIFI-7 series PCIe based WLAN module. Change-Id: Ia31fdb87e15b50471dc7664e42b1e2625ce1ac58 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* drivers/wifi: Avoid camel casing in macro definitionSubrata Banik2023-09-051-2/+2
| | | | | | | | | | | | | | | | | | | | Convert camel case macros to uppercase and underscore separated macros, such as: PCI_DID_CyP_6SERIES_WIFI -> PCI_DID_CP_6SERIES_WIFI PCI_DID_TyP_6SERIES_WIFI -> PCI_DID_TP_6SERIES_WIFI This makes the macros more consistent with the rest of the code and easier to read. Change-Id: I9c739aab93dc0d043a3c9d9ce799087952c1e20b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77644 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* device/dram: add DDR4 RCD I2C access functionsKrystian Hebel2023-08-211-0/+61
| | | | | | | | | | | | | | | | | | | | Registering Clock Driver (RCD) is responsible for driving address and control nets on RDIMM and LRDIMM applications. Its operation is configurable by a set of Register Control Words (RCWs). There are two ways of accessing RCWs: in-band on the memory channel as MRS commands ("MR7") or through I2C. Access through I2C is generic, while MRS commands are passed to memory controller registers in an implementation-specific way. See JESD82-31 JEDEC standard for full details. Change-Id: Ie4e6cfaeae16aba1853b33d527eddebadfbd3887 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* device/dram: add DDR4 MRS commandsKrystian Hebel2023-08-211-0/+303
| | | | | | | | | Change-Id: I9d4f048c859bc89897d50a5a07468c3375aa1dcf Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* include/device/device: drop unused alignment definesFelix Held2023-08-151-6/+0
| | | | | | | | | | | | The resource allocator's setup_resource_ranges will make sure that the memory resources are 4KiB-aligned. The resource allocator doesn't enforce any alignment requirements on IO regions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3c148ce2acbe284b40126e331d8f372839817e73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77167 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/resource: drop unused IORESOURCE_* definitionsFelix Held2023-08-101-3/+0
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I435557f636a227e2d8c6c413a4d928e58a471dec Reviewed-on: https://review.coreboot.org/c/coreboot/+/77111 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device: align comments in struct busFelix Held2023-08-101-6/+6
| | | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I20fe63e93121b3b791e6d475e948b6ada648293b Reviewed-on: https://review.coreboot.org/c/coreboot/+/77073 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* include/device/device: drop unused fields from struct busFelix Held2023-08-101-4/+0
| | | | | | | | | | | | Neither cap, hcdn_reg, disable_relaxed_ordering nor ht_link_up are used, so drop the fields from struct bus. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I655b028107da7ddcb5caa03dab55b022387e7cb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77072 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* ec/google/chromeec: Split wait-loop for DP and HPD flagsKapil Porwal2023-07-151-0/+9
| | | | | | | | | | | | | | | | | Split wait-loop for DP and HPD flags as below - - google_chromeec_wait_for_hpd - google_chromeec_wait_for_dp_mode_entry BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3e565d6134f6433930916071e94d56d92dc6cb06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76370 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/adl: Add Raptor Lake-HX definitionsTim Crawford2023-07-141-0/+12
| | | | | | | | | | | | Tested by booting System76 Adder WS 3 (addw3) and Serval WS 13 (serw13) to edk2 payload and then OS. Ref: Intel Raptor Lake EDS, Volume 1 (#640555, rev. 2.8) Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel: Replace number in RPL-S ESPI PCI IDs by chipset nameMichał Żygowski2023-07-121-3/+3
| | | | | | | | Change-Id: I68416e1633c3d67070790a9db2cd9a13a8981042 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel: Fix W790 chipset nameMichał Żygowski2023-07-121-1/+1
| | | | | | | | | | | | | | | In newer ADL/RPL PCH EDS 619362 revision 2.1 the ESPI ID 0x7A8A belongs to the W790 chipset. Earlier revisions had the chipset with ID 0x7A8A named W685, which was probably just a temporary name. Change the naming throughout the tree to W790, which is the real existing chipset. Change-Id: I87603298d655e9bf898b34acdd5b403f5affaee3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
* soc/intel/alderlake: Add support for Raptor Lake S CPUsMax Fritz2023-07-121-0/+9
| | | | | | | | | | | | | | | | | Add PCI IDs, default VR values and power limits for Raptor Lake S CPUs. Based on docs 639116 and 640555. TEST=Tested on a MSI PRO Z690-A (ms7d25) with i9-13900K with Ubuntu 22.10 and LinuxBoot (Linux + u-root). Also tested on MSI PRO Z790-P with i5-13600K (UEFI Payload) usign RPL-S IoT FSP and Ubuntu 22.04. Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Signed-off-by: Max Fritz <antischmock@googlemail.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69798 Reviewed-by: Tim Crawford <tcrawford@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
* soc/intel/jasperlake: Add per-SKU power limitsChia-Ling Hou2023-06-231-0/+1
| | | | | | | | | | | | | | | | Add JSL SKUs ID and add PLx from JSL PDG in project devicetree. BUG=b:281479111 TEST=emerge-dedede coreboot and read correct value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679 Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Super Ni <super.ni@intel.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* device/pci_rom: Add simple pci_rom_free()Grzegorz Bernacki2023-06-021-0/+6
| | | | | | | | | | | | | | | | | | | It adds simple function, which frees the memory which could be allocated by pci_rom_probe(). In the next step it will be modified to free only memory, which was mapped from CBFS. BUG=b:278264488 TEST=Build and run with additional debug prints added to confirm that data are correctly unmapped Change-Id: Ibc9aad34b6bf101a3a0c06b92ed2dc6f2d7b9b33 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74778 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Remove 'extern' from functions declarationElyes Haouas2023-05-261-1/+1
| | | | | | | | | | | "extern" is automatically implied with function declaration. Change-Id: Ic40218acab5a009621b6882faacfcac800aaf0b9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71890 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/intel/common: Add RPP-S PCI IDsJeremy Soller2023-05-231-0/+68
| | | | | | | | | | | | | Add PCI IDs to support Raptor Point PCH. Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2) Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/version: Move board identification stringsKyösti Mälkki2023-04-221-2/+0
| | | | | | | | | | | | | | | These strings are now only expanded in lib/identity.c. This improves ccache hit rates slightly, as one built object file lib/version.o is used for all variants of a board. Also one built object file lib/identity.o can become a ccache hit for successive builds of a variant, while the commit hash changes. Change-Id: Ia7d5454d95c8698ab1c1744e63ea4c04d615bb3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/sconfig: Remove unused ioapic and irq keywordsArthur Heymans2023-04-111-8/+0
| | | | | | | | | | | | | | | Ioapic information in the devicetree was only used to set up mptables but this generic driver was removed (ca5a793 drivers/generic/ioapic: Drop poor implementation). This removes the unused remainders from mainboard devicetrees. Remove ioapic setup from sconfig. Change-Id: Ib3fef0bf923ab3f02f3aeed2e55cf662a3dc3a1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* cpu/x86/topology: Add code to fill in topology on struct pathArthur Heymans2023-04-061-9/+0
| | | | | | | | | | | | | This is needed to generate MADT and SRAT where lapicid for threads need to be added last. When CPUID leaf '0xB' is not present assume some defaults that would result in identical ACPI code generation. Change-Id: I2210eb9b663dd90941a64132aa7154440dc7e5a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69222 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_pathArthur Heymans2023-04-061-0/+1
| | | | | | | | | | | | It's quite confusing to keep track of lapic ID inside the device struct and initial lapic ID inside an array. Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64342 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Add core_type member to 'struct apic_path'Sridhar Siricilla2023-03-311-0/+1
| | | | | | | | | | | | | | The patch adds new member 'core_type' to the 'struct apic_path' and updates core type information. TEST=Build the code for MTL Change-Id: I1d34068fd5ef43f8408301bf3effa9febf85f683 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74088 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/common: Add Intel Trace Hub driverPratikkumar Prajapati2023-03-291-0/+3
| | | | | | | | | | | | | | | | | | From Meteor Lake onwards Intel FSP will generate the Trace Hub related HOB if the Trace Hub is configured to save data in DRAM. This memory region is used by Trace Hub to store the traces for debugging purpose. This driver locates the HOB and marks the memory region reserved so that OS does not use it. Intel Trace Hub developer manual can be found via document #671536 on Intel's website. Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 11:52:42 +0000