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path: root/src/mainboard/google/brya/variants/ghost/gpio.c
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* mb/google/brya/var/ghost: Delete variantJack Rosenthal2022-09-041-423/+0
| | | | | | | | | | | | | | | This project concluded and the coreboot implementation is no longer required. BUG=b:244596639 BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Ie647dac7ad4879ec1b11baa0a8cb0990af56852f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67299 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/ghost: Enable NXP UWB SR150 chipJack Rosenthal2022-08-171-6/+6
| | | | | | | | | | | | | | | Add GPIO configuration and device tree to enable the chip. BUG=b:240607130 BRANCH=firmware-brya-14505.B TEST=Patch linux with NXP's pending drivers UWB device is probed and can respond to a simple hello packet Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I83be712d243c365a5cbfe6f69a6bd85440c5bec7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/ghost: update arbitrage gpio.c headerKevin Chowski2022-08-091-3/+6
| | | | | | | | | | | | This update follows suggestions from Martin Roth about the contents of the comment. Change-Id: Ic296bcd6a0fb250426f5d75aac69a3fa0f2aaf32 Signed-off-by: Kevin Chowski <chowski@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/ghost: Pull EN_PP3300_TCHSCR highJack Rosenthal2022-08-071-1/+1
| | | | | | | | | | | | | | | This gets the display working. BUG=b:240884260 BRANCH=firmware-brya-14505.B TEST=display works in both depthcharge and linux Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I03edac865d68ef48e86d47a04f27ed84894f2f7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66395 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* mb/google/brya/var/ghost: Enable AMP powerEric Lai2022-08-021-2/+2
| | | | | | | | | | | | | | | Follow latest schematic, GPP_A17 is used to enable AMP power. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=Check I2C scan can see the AMP return ACK. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ia6c52302a12ddec68303714ac07e96a65a8f8fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* mb/google/brya/var/ghost: Enable CS42L42 codecEric Lai2022-07-291-2/+2
| | | | | | | | | | | | | | | Add CS42L42 support in device tree. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=Check cs42l42 driver can probe successfully in kernel. cs42l42 i2c-10134242:00: Cirrus Logic CS42L42, Revision: B1 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I861f47c12f4cebb016a4cfbe225f97d34d55e233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* mb/google/brya/var/ghost: Correct CNVi pinsEric Lai2022-07-281-11/+11
| | | | | | | | | | | | | | | | GPP_F0 to GPP_F4 is for CNVi and should be NF1. GPP_F5 is for CNVi CLK_REQ, and should be NF3 CRF_XTAL_CLKREQ. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=CNVi wifi can get probed in kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ice3fde3a457f6f5c058c0a7d3ca2e63775bda96c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* mb/google/brya/var/ghost: Split ghost4adl into 3 variantsJack Rosenthal2022-07-221-0/+420
We plan to make 3 firmwares which differ only by Kconfig options and can share a common variant directory. ghost4adl: Board with an ADL chip. ghost4es: Board near identical but has RPL-ES chip. ghost: Will have final RPL silicon. Since they will only differ by Kconfig options and Intel binary blobs, let's not duplicate the variant directory but instead share it in common. BUG=b:239456576 BRANCH=firmware-brya-14505.B TEST="make menuconfig", verify layout of board selection Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I94f2048bbe6675a807f8eba986a1ded0a4167733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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