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path: root/src/mainboard/google/rex/variants/rex0/gpio.c
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* mb/google/rex: Do not power on FPMCU in ramstagePatryk Duda2024-02-171-2/+2
| | | | | | | | | | | | | | | | | | | | | When 'reset_gpio' and 'enable_gpio' properties are defined in overridetree.cb, the kernel will power on the FPMCU. If the device was previously enabled the kernel will reset it. To avoid situation in which the FPMCU is powered on and reset later we leave the FPMCU powered off in coreboot and started by the kernel. This is exactly what other boards do (e.g. brya). TEST=Boot the board (e.g. karis) and make sure the FPMCU was booted once (e.g. examine FPMCU console logs) Change-Id: I5df8d9385be2621c02ccee2d36511a4e80ab87d1 Signed-off-by: Patryk Duda <patrykd@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80457 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex/var/rex0: Toggle NVMe PWR pin to reset SSDWonkyu Kim2023-11-011-3/+8
| | | | | | | | | | | | | | | | | | During warm reboot, NVMe is not detected with non-serial image sometimes while there is no issue with serial image. This change toggles NVMe PWR pin as soon as in early stage to make NVMe ready sooner. BUG=b:260547988 BRANCH=None TEST= Build rex0 and try warm reboot from OS console. Check if the platform with Micron SSD boots to OS again without an issue. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I2f34e3f49e7fc388198ff85c8e119cb3f242a60e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/rex/var/rex0: Add HDMI GPIOs to early GPIO listAnil Kumar2023-08-311-0/+8
| | | | | | | | | | | | | | | Add HDMI GPIO configuration to early GPIO list to support VGA text o/p in Pre-RAM stage on HDMI. BUG=b:279173035 TEST=If CONFIG_UGOP_EARLY_GRAPHICS is set to y, check SOL text on HDMI during Pre-RAM boot stage. Change-Id: I13691850d09a442d5d5493a2b1dcf1145cf9797a Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/rex/var/rex0: Configure CNVi GPIO IO Standby StateJamie Ryu2023-07-111-6/+6
| | | | | | | | | | | | | | | | | | | | | This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi. Meteor Lake rex platform does not wake up from low power state by bluetooth keyboard and mouse properly. It is identified that IO Standby State needs to be configured as masked to function properly for CNVi. BUG=None TEST=Make rex platform suspend to s0ix state and press a key from bluetooth keyboard. Check the platform wakes up properly from s0ix. Change-Id: Ia98abde584699fa01acba47a9df4ef6332ac16fd Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76338 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edgeEran Mitrani2023-07-101-2/+0
| | | | | | | | | | | | | | This CL corrects the trigger for HID over SPI from Level to Edge. BUG:None TEST:Tested with I2C and SPI Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76116 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/rex,screebo: Update GPIO PAD IO Standby StateBora Guvendik2023-06-041-8/+16
| | | | | | | | | | | | | | | | | | | | Fix for the "Onboard Keyboard and Type-C ports are not working after resuming from powerd_dbus_suspend" issue. This issue was caused since FSP 3165 FSP was fixed and started skipping GpioConfigureIoStandbyState programming when GpioOverride UPD is enabled. This patch moves the IO Standby State programming that FSP was doing to coreboot. BUG=b:284264580 TEST=Boot to OS, compare gpio pins, verify keyboard / Type-C Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If96c1e71fdde784a55fe079875915ffa5a4f548a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75555 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Update GPIO PAD as per Proto 2 schematicsSubrata Banik2023-05-291-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:283477280 TEST=Able to build and boot google/rex as per Proto 2 schematics dated 05/16. +-----------------+------------------------------------+---------------------------+--------+ | GPIO | In Proto 1 | In Proto 2 | Impact | +-----------------+------------------------------------+---------------------------+--------+ | GPP_C01 | SOC_TCHSCR_RST_L | SOC_TCHSCR_RST_R_L | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_D19 | NC | EC_SOC_REC_SWITCH_ODL | Y | +-----------------+------------------------------------+---------------------------+--------+ | GPP_E04 | HPS_INT_L | SOC_PEN_DETECT | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_E17 | EN_HPS_PWR | EN_PP3300_SPARE_X | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_F13 | GSPI1_SOC_MISO | GSPI1_SOC_MISO_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_F21 | GPIO_F21_SPI_CS_L | SPI_SOC_CS_UWB_L_STRAP | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H00 | GPIO_H00_SPI_CLK_R | SPI_SOC_CLK_UWB_STRAP_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H01 | GPIO_H01_SPI_MOSI_R | SPI_SOC_DO_UWB_DI_STRAP_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H02 | GPIO_H02_SPI_MISO | SPI_SOC_DI_UWB_DO_STRAP | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S00 | UNNAMED_8_METEORLAKEU_I137_GPPS00 | SDW_HP_CLK_WLAN_PCM_CLK | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S01 | UNNAMED_8_METEORLAKEU_I137_GPPS01 | SDW_HP_DATA_WLAN_PCM_SYNC | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S02 | UNNAMED_8_METEORLAKEU_I137_GPPS02 | DMIC_SOC_CLK0_WLAN_PCM_OUT| N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S03 | UNNAMED_8_METEORLAKEU_I137_GPPS03 | DMIC_SOC_DATA0_WLAN_PCM_IN| N | +-----------------+------------------------------------+---------------------------+--------+ Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a8c43b0f845d3446188b7c926e482f91e5b45aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75407 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/rex: Enable stylus supportDinesh Gehlot2023-05-191-2/+2
| | | | | | | | | | | | | | | | This patch enables stylus support by configuring the "GPP_D08" irqs for rex SoC. This allows the SoC to detect a stylus device, when in use. However stylus is not a wake up source for the rex. BUG=b:282256460 Test=Stylus is detected on proto1 device. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I84a71aa664698e105b738f8680d0a4751ca1fc72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/rex: Set WWAN_RF_DISABLE_ODL to NCTarun Tuli2023-05-121-1/+1
| | | | | | | | | | | | | | | | This signal isn't functionally being used and is causing leakage during suspend. Set it to NC. BUG=b:279762779 TEST=builds. WWAN functional. Change-Id: I93f2b0a781e250678280b57e4ab1d80ef27ff460 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/rex: remove weak from cros gpioEric Lai2023-04-121-1/+1
| | | | | | | | | | | | | | No need for variant to use _weak. BUG=b:276818954 TEST=new_variant_fulltest.sh rex0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7ad904e06e5d83edf4bc11cafd5060ca409bd4ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74294 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/rex: Rename touchscreen signals as per latest Rex schematicsEran Mitrani2023-03-081-6/+6
| | | | | | | | | | | | | | Touchscreen signals were renamed for Rex schematics dated 21st Dec'22. This CL fixes the comments for those signals. BUG=b:263411413 TEST=None required (changed comments only) Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Ic40ef943d199d9f4a2bec9c0e6d4820224ef6adc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/rex: update touchscreen report EN pin settingIvy Jian2023-02-031-14/+1
| | | | | | | | | | | | | | | | | | | Removed workaround since the latest schematics fixed. Power Sequencing of ELAN6918 (in ACPI) after this patch `POWER enabled -> RESET deasserted -> Report EN enabled` BUG=b:247029304 TEST=Verified ELAN touch panel is working as expected after booting Google/rex device to ChromeOS. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I19629262776f7e0cccbdebb2285890d177a8a8a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72725 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOWSubrata Banik2023-01-041-2/+2
| | | | | | | | | | | | | | | This patch configures GPP_H15 (EN_DMIC_SOC_DATA) as GPO and put into safe state aka LOW/PD. BUG=b:263411621 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Use GPP_C15 as WWAN_DPR_SAR_ODLSubrata Banik2022-12-241-2/+2
| | | | | | | | | | | | | BUG=b:263413949 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I453fe8e1f4b4b8d4730ade259899d76aec949a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71231 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/rex: Rename GPP_D07 to FPMCU_UWB_MUX_SELSubrata Banik2022-12-241-2/+2
| | | | | | | | | | | | | BUG=b:263412235 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia444cc8e3666fe15479ece81d068f9e8f1d339ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/71228 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/rex: Modify the PIN name as per schematicsSubrata Banik2022-12-151-3/+3
| | | | | | | | | | | | | | | This patch updates the GPIO PIN name as per Proto 1 schematics dated 12/14/2022. TEST=Not code change, just updated the comment section. Change-Id: Ic076ab35689fd2afb7c18eff065a90b9464a6b1d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/google/rex: Add RTD3 support for discrete wifi moduleKapil Porwal2022-12-151-4/+4
| | | | | | | | | | | | BUG=none TEST=Build and boot to the OS on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2c5bac880e7dbc2ec14376c5cee3c13363bab377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70444 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Add PCIe based SD controllerSubrata Banik2022-12-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | This patch adds PCIe based SD controller at RP 7 (from RP 11) with Proto 1 schematics dated 11/30. Additionally, added the RTD3 entries for the SD controller. Finally, ensured that EN_PP3300_SD (GPP_D03) is configured in bootblock and SD_PERST_L (GPP_D02) is configured in romstage to meet the power cycle requirement. BUG=b:242917011 TEST=Able to build and boot Google/Rex. SD card detection is due for the Proto 1 hardware. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I23d53e4d61ec36d2145f9e5816d97d13eb5b219e Reviewed-on: https://review.coreboot.org/c/coreboot/+/70064 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/rex: Drop `board_id` check while configuring GPIOSubrata Banik2022-12-031-55/+9
| | | | | | | | | | | | | | | | | | | | | | | | | This patch drops the usage of reading `board_id()` while performing the GPIO configuration. The reason to drop the board_id check is to ensure that GPIO configuration for MLB (mainboard) would remain the same and the only GPIO PIN configuration that differs would be due to usage of having different DBs (daughter board) which will be taken care using CBI (and fw_config.c file) in coreboot. Additionally, drop unused early GPIO default configuration table. BUG=b:260804656 TEST=Able to perform the GPIO configuration and able to boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I96cafd1c904001cbf4199977e9e721afe5eab470 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/google/rex: Adding cros_gpios to rexIvy Jian2022-11-241-0/+1
| | | | | | | | | | | | | | Adding cros_gpios for crossystem to access WP GPIO BUG=b:258048687 TEST= run FAFT firmware_WriteProtect passed. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ieac1df805c6399aefdc13aae136630d496aacd58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69924 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Add Write Protect GPIO to cros_gpiosIvy Jian2022-11-121-1/+3
| | | | | | | | | | | | | | This will enable crossystem to access WP GPIO BUG=b:258048687 TEST= wpsw_cur in crossystem reads the correct gpio Change-Id: I67f4a57025064dbf8c691255b0abae9d3fa0dbd3 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69468 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Add fingerprint SPIEran Mitrani2022-11-091-1/+5
| | | | | | | | | | | | | | | | Add Fingerprint SPI, and power-off FPMCU during romstage. For reference see CL:66915 for a similar change to Brya's power sequence SHA: 2b523ce6316e5c5ec86fe812d739fe48ca81d83d ("Invoke power cycle of FPMCU on startup") TEST=Tested on Rex - setup and logged in using fingerprint Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/rex: Add ELAN6918 touchscreenSubrata Banik2022-09-191-2/+15
| | | | | | | | | | | | | | | | | | | | | | | ELAN6918 Power Sequencing seems not perfectly matching with the previous platforms and setting GPP_C06 to high prior to the power sequencing is actually makes it work. Ideally Power Sequencing should be as below for ELAN6918 (in ACPI) `POWER enabled -> RESET deasserted -> Report EN enabled` But below sequence is only working currently: `Report EN enabled (ramstage) -> POWER enabled (ACPI) -> RESET deasserted (ACPI)` BUG=b:247029304 TEST=Verified ELAN touch panel is working as expected after booting Google/rex device to ChromeOS. Change-Id: Ideaeb0faa882b8e603534bbface51ea76923d436 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/google/rex: Complete several remaining GPIO configsTarun Tuli2022-09-101-13/+13
| | | | | | | | | | | | | | | | | | | Lists of GPIO PINS being updated: SPKR_INT_L_R RST_HP_L SOC_HDMI_HPD_L SOCHOT_ODL SOC_FPMCU_INT_L EN_PP3300_WLAN BUG=b:24410269 TEST=Build and boot Google/Rex to ChromeOS. Change-Id: If2fb354f931217c09a6c1c81ca780cb121b24468 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67449 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Add WWAN poweron sequencingIvy Jian2022-09-081-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe WWAN module used on rex requires control over 4 signals to successfully power it on. It is desirable to do this before passing control to the payload, because the modem requires a ~10 seconds initialization phase before it can be used. The corrected sequence looks like: 1) Drive device into full reset and enable power in bootblock 2) Deassert FCPO in romstage, after power rails stabilize 3) Deassert WWAN_RST#, then WWAN_PERST# in ramstage BUG=b:244077118 TEST=FM350 could be enumerated via lspci Measured signals to check start-up Timing Sequence, tpr/ton1/ton2. Tpr = 572mS Ton1 = 6.3s Ton2 = 6.3+4.17ms Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I6cda9348ef7f54efe5ba2358040596a1c2da1b13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67332 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Correct GPSI0 muxing for pads requiring NF8Tarun Tuli2022-09-041-4/+4
| | | | | | | | | | | | | | | | | GSPI0 pads required muxing to NF8. Support for extended native functions was added in commit b6c32d7fe4ea98ba8b3a10cb5ce46448801855b8 BUG=b:244610269 TEST=build and booted on Rex Change-Id: Iab4e0bc6890cd8e976c513fe87dda0da9b5f2ee0 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
* mb/google/rex: Change GPP_A17 programmingTarun Tuli2022-08-301-4/+2
| | | | | | | | | | | | | | To match byra commit 7c2514fc072f95eed6483518811fb6c39f780f5b (mb/google/brya: Change GPP_F17 programming), update A17 pad configuration to the APIC only. TEST=Verified booting to OS on Google/Rex. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ie9f071dc4a2755dd1f396e2afe730ead66bb1dd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67183 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Configure GSC INT GPIO early in the bootKapil Porwal2022-08-251-0/+5
| | | | | | | | | | | | | | | | This patch configures GPP_E03 (GSC_SOC_INT_ODL) as GPI/APIC in early GPIO tables. BUG=b:243641061 TEST=Able to build rex image. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I4aa180c7105be3f356a0bbd5b92b4ced628c34fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/67017 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/rex: add arbitrage gpio.c headerKevin Chowski2022-08-241-0/+7
| | | | | | | | | | | | This comment header is necessary for supporting propagation of overrides to variants. Change-Id: Iee92fa4fbc4851c7032401cff99ea49f87717c7f Signed-off-by: Kevin Chowski <chowski@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/rex: Remove depedency on board id for early GPIO configTarun Tuli2022-08-071-5/+16
| | | | | | | | | | | | | | | | | | This adds a default early GPIO table in the case of us not being able to identify a valid board ID. Primarily, this is useful in the case of EC issues to ensure that debug interfaces (e.g. UART) are always up and available. BUG=b:238165977 TEST=Boots and no errors on simics Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I135dc6c29bc23195afe5c78eb79992691652d9e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66394 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/rex: Initial setup for ramstage/early gpio configTarun Tuli2022-07-281-19/+417
| | | | | | | | | | | | | | | This adds the initial gpio configuration for the rex initial variant. BUG=b:238165977 TEST=Boots and no errors on simics Change-Id: I55ab31c7943e22df9cec8db4a9f0c3ab6f065ae1 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65952 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/rex: Refactor baseboard/variant gpio pad configurationSubrata Banik2022-07-191-0/+52
This patch tries to simplify the baseboard/variant GPIO programming starting with Google/Rex. The idea is to let each variant maintain its own complete GPIO PAD configuration table instead of having a back-and-forth call between baseboard and variants. With this patch coreboot performing GPIO programming is now much simpler where the common code block calls into respective variants and gets the gpio table prior to the pad configuration. BUG=b:238165977 (Simplify baseboard/variant GPIO programming starting with Google/Rex) TEST=Able to build and boot the Google/Rex board. AP firmware log with DEBUG_GPIO kconfig lists the early GPIOs being configured from the `rex0` variant. gpio_padcfg [0xd3, 08] DW0 [0x44000300 : 0x40000400 : 0x40000400] gpio_padcfg [0xd3, 08] DW1 [0x00000020 : 0x00000000 : 0x00000020] gpio_padcfg [0xd3, 08] DW2 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 08] DW3 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 09] DW0 [0x44000300 : 0x40000400 : 0x40000400] gpio_padcfg [0xd3, 09] DW1 [0x00000021 : 0x00000000 : 0x00000021] gpio_padcfg [0xd3, 09] DW2 [0x00000000 : 0x00000000 : 0x00000000] gpio_padcfg [0xd3, 09] DW3 [0x00000000 : 0x00000000 : 0x00000000] Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8ec5c6991ec90a3884464e7f15f33327bfe4839a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-08 07:11:54 +0000