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* mb/google/zork: Set vw_irq_polarity from low to highRaul E Rangel2022-08-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | The EC used on zork uses a level high interrupt. This change configures the polarity correctly. The eSPI config is baked into RO verstage. The zork ToT build doesn't use signed verstage since it's incompatible with the ToT version of vboot. This means we can safely switch the keyboard IRQ polarity. NOTE: Do not cherry pick this into the Zork firmware branch! BUG=b:160595155 TEST=On morphius verify keyboard works as correctly and no spurious interrupts are thrown on S0i3 resume. Also verified keyboard and mouse work correctly in windows. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8d3195522f3bd5e477635494c7156683aae0ff0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/picasso/acpi: generate PPKG object in generate_cpu_entries callFelix Held2022-03-031-0/+2
| | | | | | | | | | | | | | | | | | Generate the PPKG object in the generate_cpu_entries function instead of generating the PCNT object that is the used in the PPKG method in cpu.asl to provide the PPKG object. This both simplifies the code and aligns Picasso with Cezanne and Sabrina. This will also make the code behave correctly in a case where the number of CPU cores/threads isn't a power of two. TEST=Mandolin still boots successfully to Linux desktop and dmesg doesn't show any any possibly related problems. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/zork/acpi: Use Printf() for debug printsFelix Singer2021-12-291-4/+2
| | | | | | | | Change-Id: I433b7138da84b57e45e816ab116f8ca874fdc0e0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* mb/google/zork: use full path of SoC's chip.hFelix Held2021-12-201-1/+1
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I50d8c45e711dc62afe6f80e0f66422bcc9924dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/zork,soc/amd/psp_verstage: Add verstage_mb_{tpm/espi}_initRaul E Rangel2021-12-081-0/+6
| | | | | | | | | | | | | | | | | These functions can't be weak, because they actually need to configure the GPIOs for eSPI and the TPM. With this change zork boots again. I also noticed that zork doesn't use the early table in bootblock. This means that zork will only boot if psp_verstage is enabled. BUG=b:209465425 TEST=boot zork to ramstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* src/mainboard to src/security: Fix spelling errorsMartin Roth2021-10-051-1/+1
| | | | | | | | | | | | These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/zork/var/shuboz: update USB OC pin mappingKane Chen2021-05-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | modify USB OC pin setting for Shuboz/Jelboz/Jelboz360 Shuboz/Jelboz: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_PIN_1" # USB A1 usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 Jelboz360: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 BUG=b:182879559 BRANCH=zork TEST=emerge-zork coreboot, validate the OC mapping. Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/zork: move include to the files where it's usedFelix Held2021-04-151-1/+0
| | | | | | | | | | | | | platform_descriptors.h is unrelated to the contents of baseboard/gpio.h where it was included, so move the includes to the files where it is actually needed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94e59b5aac2df834d956106ac953eebfc5cf6921 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52357 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: include amdblocks/gpio_defs.h in baseboard/gpio.hFelix Held2021-04-151-0/+1
| | | | | | | | | | | amdblocks/gpio_defs.h provides the definitions of GEVENT_x. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I65d398667e6777de6f1fa4e027cf1c75a3e235c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52356 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Use SOC defines instead of magic numbersMathew King2021-03-101-3/+3
| | | | | | | | | | | BUG=b:182269526 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I351fb4fc493bb92b31e2c8bc946dfb048045335c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/zork/var/vilboz: Add Mainboard Type for VCORE ICJohn Su2021-03-101-0/+2
| | | | | | | | | | | | | | | To define Mainboard Type config, use the fw_config bit[26]. Check MB Type to modify SDLE settings for different VCORE IC. BUG=b:177193131 BRANCH=zork Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/google/zork: add UPDM updating function before runing FSP-MChris Wang2021-03-101-0/+3
| | | | | | | | | | | | | | | Add the UPD updating hook in early stage for customization. BUG=b:117719313 BRANCH=zork TEST=build,check the hook function been executed. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I4954a438a51b29b086015624127e651fd06f971b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork/var/vilboz: Add WiFi SAR for VilbozFrank Wu2021-01-151-0/+2
| | | | | | | | | | | | | | | | | | | The fw_config field SPI_SPEED is not used for zork devices. To define SAR config, use the fw_config bit[23..26]. Then vilboz can loaded different WiFi SAR table for different SKUs. BUG=b:176858126, b:176751675, b:176538384 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/49296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/zork: enable wake on MKBP eventsPeter Marheine2021-01-051-1/+2
| | | | | | | | | | | | | | | | | | | | The EC generates EC_MKBP_EVENT_DP_ALT_MODE_ENTERED when USB-C connections enter DP alt mode, which should wake the system from S3. Configure S3 wake events to include MKBP so this actually wakes the system. BUG=b:174121852 BRANCH=zork TEST=Generating DP event on MKBP via EC console wakes morphius Change-Id: I8100c6253e8e5cae91586c4f2f45d66c15fecc6d Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/google/zork/var/vilboz: Add enable acp_i2s_use_external_48mhz_osc flagJohn Su2020-12-221-0/+2
| | | | | | | | | | | | | | | | Add enable acp_i2s_use_external_48mhz_osc flag and then WWAN sku will use external clock source at next build. BUG=b:174121847 BRANCH=zork TEST=build vilboz and check MISC_CLK_CNTL1. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ida747938373f648524b1e7f34bc69e372a69c4f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48556 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Remove unsused codeMathew King2020-12-101-1/+0
| | | | | | | | | | Remove unused code that appears to be left over from grunt. Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Id5bdb1c957342d55c5e6378c503b8d90da050601 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48505 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Init fingerprint GPIOs for boot vs resumeMartin Roth2020-11-161-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a function that initializes GPIOs based on the sleep type that the system is coming back from. This allows initialization of the fingerprint GPIOs which need to be handled differently between wake from S3 and boot from S5. On initial boot, the state of the FP sensor could be either enabled or disabled. Because of this, on boot, we power off the sensor for >200ms, to reset its state, then power it back on. In suspend/resume, the fingerprint sensor should remain powered the entire time. If fingerprint is disabled on the trembyle-based board, set the pins to no-connect. Dalboz doesn't have fingerprint and the GPIOS are configured differently due to the FT5 chip having fewer GPIOS than FP5, so nothing needs to be initialized there. There were also a couple of trivial comment clean ups regarding the FPMCU GPIOS. BUG=b:171837716 TEST=Boot & Check GPIO states. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/zork: Convert to ASL 2.0 syntaxElyes HAOUAS2020-10-131-10/+10
| | | | | | | | Change-Id: I71ee54116ade4d6826dffc31ee879a70d3fc967f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* mb/google/zork: Add EC device wakeup for morphiusJosie Nordrum2020-10-071-0/+3
| | | | | | | | | | | | | | | Add support for trackpoint wakeup from S3 by adding device events to mainboard and defining for morphius. BUG=b:160345665 BRANCH=zork TEST=tested trackpoint wake from S3 on morphius DVT Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I982f0f4b60fbaeb389774531e1dee83da77cb8a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google: Drop unneeded empty linesElyes HAOUAS2020-09-221-1/+0
| | | | | | | | Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/google/zork: Add helper function to read DB ID bits in FW_CONFIGBhanu Prakash Maiya2020-08-131-0/+2
| | | | | | | | | | | | | | | | Add helper function variant_get_daughterboard_id() to read daughterboard id bits (0-3) in firmware configuration table in CBI. BRANCH=none BUG=b:162344105,b:152817444 TEST=Check if daughterboard id bits (0-3) can be read from FW_CONFIG. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: Ia3c882439bfbe6da28be2df0ec0c976d5c142677 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44424 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Remove validity checks for FW_CONFIG in CBIBhanu Prakash Maiya2020-08-131-2/+0
| | | | | | | | | | | | | | | | | | | After confirming that all zork variants and phases have valid FW_CONFIG value in CBI, this patch is dropping FW_CONFIG validity checks like VARIANT_HAS_FW_CONFIG and VARIANT_BOARD_VER_FW_CONFIG_VALID in Kconfig and will also remove associated helper functions. BRANCH=none BUG=b:162344105,b:152817444 TEST=Check if FW_CONFIG bits can be read in coreboot and FW_CONIFG helper function do not return 0 if board has a valid FW_CONFIG in CBI. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: I633dc7c500ef8759f3fffb0db6b76d96257c3c9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/zork: Switch USI_RESET to active low polarity for v3.6+Furquan Shaikh2020-08-061-0/+2
| | | | | | | | | | | | | | | | | | v3.6 of reference schematics have switched the polarity of reset signal to touchscreen controller from active high to active low. This change updates the default configuration in baseboard gpio tables to set the reset GPIO to output low and override tables in variants to set the reset GPIO to output high. Additionally, devicetree by default exposes ACTIVE_LOW configuration for reset GPIO. In order to support pre-v3.6 boards, reset GPIO is updated to ACTIVE_HIGH based on board version. BUG=b:161937506 Change-Id: I092f274d8eb1920a1cd6d3eccbe8f26b0b28928a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/zork: Add kconfigs to check schematic version 3.6Josie Nordrum2020-08-061-0/+4
| | | | | | | | | | | | | | | | Added VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS and VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS. Added helper functions to check if variant uses v3.6 and if variant uses CODEC GPI. BUG=b:161938476 BRANCH=None TEST=None Change-Id: If86e1ea3c02db354c7b410f1bbc1daacb483cc51 Signed-off-by: Josie Nordrum <josienordrum@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44156 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: remove indirection for dxio lane configurationAaron Durbin2020-07-301-21/+0
| | | | | | | | | | | | | | | | | There was a mix of open coding DXIO logical lane numbers and clkreq pins. And there are separate macros depending on the baseboard as well as processor type. Remove the indirection and supply the values directly in the descriptors. BUG=b:162423378 Change-Id: I779cb0a514e3b668265e6039d6e7e7bd0f3d49ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/zork: Add Bluetooth reset gpios to devicetreeRob Barnes2020-07-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add bluetooth reset gpio 143 to dalboz baseboard devicetree Add bluetooth reset gpio 14 to trembyle baseboard devicetree Remove bluetooth reset_gpio when not supported on a specific board variant. BUG=b:157580724 TEST=Boot Ezkinil with Realtek 8822CE, observe log [ 12.240720] Bluetooth: af_bluetooth.c:bt_init() HCI device and connection manager initialized [ 12.249272] Bluetooth: hci_sock.c:hci_sock_init() HCI socket layer initialized [ 12.256520] Bluetooth: l2cap_sock.c:l2cap_init_sockets() L2CAP socket layer initialized [ 12.264575] Bluetooth: sco.c:sco_init() SCO socket layer initialized [ 12.273700] usb 3-2: GPIO lookup for consumer reset [ 12.273702] usb 3-2: using ACPI for GPIO lookup [ 12.273705] acpi device:18: GPIO: looking up reset-gpios [ 12.273707] acpi device:18: GPIO: looking up reset-gpio [ 12.273711] acpi device:18: GPIO: _DSD returned device:18 0 0 0 [ 12.273737] gpio gpiochip0: Persistence not supported for GPIO 14 [ 12.273960] usbcore: registered new interface driver btusb Change-Id: I14e3ef099d5b8f48c915b41284039b3508dec975 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* amd/picasso: rename PCIe descriptor to DXIO descriptorFelix Held2020-07-231-3/+3
| | | | | | | | | | | | Most of the DXIO descriptors are used to configure PCIe engines and lanes, but on Picasso system some of the DXIO lanes can also be configured as SATA or XGBE ports. Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Delete sleep.aslRaul E Rangel2020-07-201-48/+0
| | | | | | | | | | | | | | These methods are empty and the kernel treats these as optional. BUG=b:153001807, b:154756391 TEST=Suspend and resume trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5f2b375c1186951f95b7ac44dc7158a0299013a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43465 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Drop mainboard.aslFurquan Shaikh2020-07-171-14/+0
| | | | | | | | | | | | | | This change drops mainboard.asl from zork because none of the objects defined in it are used. BUG=b:153879530 Change-Id: If5440bcbce39b4461b44acaec69561663b1ea329 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43519 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Move PMOD global variable to globalnvs.aslFurquan Shaikh2020-07-171-1/+0
| | | | | | | | | | | | | | | | | | | Global variable `PMOD` that stores the interrupt mode used by OS is required by all mainboards. This change moves the variable definition to globalnvs.asl under picasso. Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC until _PIC() method is called by OS. Thus, this change also updates the default value of PMOD as 0 i.e. PIC mode. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I731c03d965882281a7a23f55894451210ba72274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatusRaul E Rangel2020-07-161-2/+0
| | | | | | | | | | | | | | | | The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390 No reason to have the firmware do it as well. BUG=b:153001807, b:154756391 TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variableRaul E Rangel2020-07-161-1/+0
| | | | | | | | | | | | | | PMx0EE is not defined in the Picasso PPR. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/zork: Drop variant_romstage_gpio_table()Furquan Shaikh2020-07-161-3/+2
| | | | | | | | | | | | | | | | gpio_set_stage_rom table is now configuring only PCIe related GPIOs in romstage. This change moves the configuration of PCIe related GPIOs to variant_pcie_gpio_configure() to keep all the configuration for WiFi and non-WiFi PCIe pads in one place. It also drops the function variant_romstage_gpio_table() as it is unused. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib1c41ba141dce6b52b6e0a250a3aa07c296068aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/43475 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork/.../sleep.asl: Remove unnecessary variableRaul E Rangel2020-07-151-7/+1
| | | | | | | | | | | | | | | | There is no reason to create a named variable. We can just return the package. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f8f0362adf5ea5f026d0ba5ac6ac917fa160142 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mainboard: Drop optional and empty ACPI \_BFS methodsAngel Pons2020-07-151-16/+0
| | | | | | | | | | | | | | | | The ACPI specification, version 2.0 says: _BFS is an optional control method. So, remove them. They have been copy-pasted around quite a bit, and do not do anything useful. Plus, it's deprecated in later ACPI versions. Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Rename get_gpe_table to variant_gpe_tableRaul E Rangel2020-07-101-1/+1
| | | | | | | | | | | | | This matches the other methods. BUG=b:154756391 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ba1fc5756c17da4dc1727425af17c4582c01a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/zork: Add helpers for v3 schematics and wifi power enableFurquan Shaikh2020-07-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | This change adds following two helper functions: 1. variant_uses_v3_schematics() - Check whether the variant is using v3 version of schematics. 2. variant_has_active_low_wifi_power() - Check whether the variant is using active low power enable for WiFi. In addition to this, Kconfig options are reorganized to add two new configs - VARIANT_SUPPORTS_PRE_V3_SCHEMATICS and VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. This allows the helper functions to return `true` early without checking for board version. Eventually, when a variant decides to drop support for pre-v3 schematics, it can be dropped from selecting VARIANT_SUPPORTS_PRE_V3_SCHEMATICS. Similarly, when the variant decides to drop support for active high power enable for WiFi, it can be dropped from selecting VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. Change-Id: I62851299e8dd7929a8e1e9a287389abd71c7706c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43224 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Drop unused function variant_romstage_entry()Furquan Shaikh2020-07-051-1/+0
| | | | | | | | | | | This change drops the function `variant_romstage_entry()` which is unused on zork. Change-Id: I140ab3e837971c4c7dbef5d27616043b5fc6c2c9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43116 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Use SSDT generator for Chrome EC audio codec deviceFurquan Shaikh2020-07-051-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change drops the inclusion of codec.asl in DSDT for `GOOG0013` device and instead uses the newly added Chrome EC audio codec driver for filling in the device node in SSDT. TEST=Verified that following node gets generated: Scope (\_SB.PCI0.LPCB.EC0.CREC) { Device (ECA0) { Name (_HID, "GOOG0013") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_DDN, "Cros EC audio codec") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Change-Id: I3e626ce01a3735ac2c966c0e95310be4c828b241 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43042 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: adjust eSPI virtual irq settingsAaron Durbin2020-07-031-2/+0
| | | | | | | | | | | | | | | | | The eSPI polarity macros were reversed. Those are fixed so adjust the corresponding values related to the correct expectations of the IRQ path: eSPI virtual wire IRQs are active level high. The EC sends active level high virtual wire IRQs. The default interrupt encodings in ACPI for P2/S devices are active edge high. Therefore, there is no need to override anything. BUG=b:157984427 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia28d82cd9e432df98839f68bac4eae4447455e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/zork: Generate I2SM ACPI device at runtimeFurquan Shaikh2020-07-022-40/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change moves the generation of I2SM ACPI device from static asl file to runtime generation by ACP device driver. dmic_select_gpio is set to match version 3+ of Trembyle and Dalboz schematics. In order to maintain backward compatibility, dmic_select_gpio is updated at runtime using variant_audio_update for board versions that are prior to version 3 of reference schematics. The only difference from static generation is that the device I2SM is added under ACPD (i.e. ACP device) instead of CREC (Chrome EC device). It does not make any functional difference from the kernel perspective. BUG=b:157603026 TEST=Verified that the following device gets generated in SSDT: Scope (\_SB.PCI0.PBRA.ACPD) { Device (I2SM) { Name (_HID, "AMDI5682") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_DDN, "I2S machine driver") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x000D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "dmic-gpios", Package (0x04) { \_SB.PCI0.PBRA.ACPD.I2SM, Zero, Zero, Zero } } } }) } } Verified audio via speakers and mic input. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I5d1602c7f719eef9487ddea68e429d27408f9a76 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2253638 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/zork: Drop unused/unnecessary GPIO macrosFurquan Shaikh2020-07-011-28/+1
| | | | | | | | | | | | | This change drops macros for GPIOs which are unused or don't really require extra indirection (same across all variants). BUG=b:159283649 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1a94327103a419f26b1d7feda4c995363ada7281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/zork: Add support for GPIO configuration on sleep pathFurquan Shaikh2020-07-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | This change adds support to configure GPIOs on the sleep path. This is required to turn off power to devices that do not act as wake sources and to assert reset to devices. Currently, variant_sleep_gpio_table() returns an empty table by default. In the following changes, entries will be added to gpio_sleep_table. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7286cbf165024bdd81f8748e525542dce8dd8702 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2253642 Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mb/google/zork: Add support for WiFi power sequencingFurquan Shaikh2020-06-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change replaces variant_wifi_romstage_gpio_table() with variant_pcie_power_reset_configure() to handle the reset and power sequencing for WiFi devices pre- and post- v3 version of schematics. These are the requirements that need to be satisfied: 1. As per PCI Express M.2 Specification Revision 3.0, Version 1.2, Section 3.1.4 "Power-up Timing", PERST# should stay disabled until `TPVPGL` time duration after device power has stabilized. Value of TPVPGL is implementation specific. 2. For Intel WiFi chip, it is known to get into a bad state if the above requirement is violated and hence requires a power cycle. 3. On pre-v3 schematics: - For both dalboz and trembyle references, GPIO42 drives WIFI_AUX_RESET_L which is pulled up to PP3300_WIFI. - For both dalboz and trembyle references, PP3300_WIFI is controlled using GPIO29. This pad gets pulled high by default on PWRGOOD because of internal pull-up. But, at RESET# it is known to have a glitch. When GPIO29 gets pulled high, it causes WIFI_AUX_RESET_L to be pulled high as well. This violates the PCIe power sequencing requirements. Hence, for pre-v3 schematics on both dalboz and trembyle, following sequence needs to be followed: a. Assert WIFI_AUX_RESET_L. b. Disable power to WiFi. c. Wait 10ms to allow WiFi power to go low. d. Enable power to WiFi. e. Wait 50ms as per PCIe specification. f. Deassert WIFI_AUX_RESET_L. 4. On v3 schematics: - For trembyle: WIFI_AUX_RESET_L is driven by GPIO86 which has an internal PU as well as an external PU to PP3300_WIFI. - For dalboz: WIFI_AUX_RESET is driven by GPIO29. This is active high and has an internal PU. It also has an external 1K PD to overcome internal PU. - For both dalboz and trembyle references, PP3300_WIFI is controlled by GPIO42 which has an internal PU and external PD. Trembyle schematics have a comment saying strong PD of 2.2K but the stuffed resistor is a weak one (499K). ON dalboz, it uses a weak PD (which doesn't look correct and instead should be a strong PD just like trembyle). Having a strong PD ensures that the WiFi power is kept disabled when coming out of G3 until coreboot configures GPIO42 as high. - Thus, for v3 schematics, following sequence needs to be followed: a. Assert WIFI_AUX_RESET{_L} signal. b. Enable power to WiFi. c. Wait 50ms as per PCIe specification. d. Deassert WIFI_AUX_RESET{_L} signal. BUG=b:157686402, b:158257076 TEST=Verified that QCA and AX200 cards both continue working. Tested QCA on Dalboz and Trembyle. Tested AX200 on morphius. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I532131ee911d5efb5130d8710f3e01578f6c9627 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42738 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/fsp/platform_descriptors: drop prefix from PCIe/DDI structsFelix Held2020-06-111-4/+4
| | | | | | | | | | | The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor structs isn't needed, since this code is picasso-specific, so drop it. Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork: Delete sb_fch.aslRaul E Rangel2020-06-031-246/+0
| | | | | | | | | | | | | | This file is not used. BUG=b:154756391 TEST=Build trembyle and check that peripherals still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I721e295546aa75c9745a4836425b6e3e0067afaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/41837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/zork: Add Picasso based Zork mainboard and variantsRaul E Rangel2020-05-279-0/+690
This is a copy of the mb/google/zork directory from the chromiumos coreboot-zork branch. This was from commit 29308ac8606. See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork Changes: * Minor changes to make the board build. * Add bootblock.c. * Modify romstage.c * Removed the FSP_X configs from zork/Kconfig since they should be set in picasso/Kconfig. picasso/Kconfig doesn't currently define the binaries since they haven't been published. To get a working build a custom config that sets FSP_X_FILE is required. BUG=b:157140753 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-27 02:04:13 +0000