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* soc/amd/common/block/apob/apob_cache.c: Add assert for APOB DRAM sizeFred Reitberger2022-08-011-0/+3
| | | | | | | | | | | | | | | | Add static check to ensure the reserved APOB DRAM space is the same size as the MRC_CACHE region specified in the fmap. Update sabrina APOB DRAM size to match the fmap. TEST: Timeless builds identical. Test build with a larger MRC_CACHE than APOB DRAM failed the assert as expected. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/spi/fch_spi_ctrl: Fix restricted command writeFred Reitberger2022-07-201-1/+1
| | | | | | | | | | | | | | | | The SPI_RESTRICTED_CMD register is not a PCI configuration register. It is memory mapped from the SPI bar. Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243 rev 1.50 TEST=Compile tested only Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63305 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/psp_verstage: Fix update_boot_regionKarthikeyan Ramasubramanian2022-07-202-6/+18
| | | | | | | | | | | | | | | | | | | | | | | On SoCs where PSP use A/B recovery layout, PSP expects PSP L2 directory address relative to the start of the SPI ROM. Unfortunately there is nothing in the EFS2 header to help identify such SoCs. Hence add a config item to statically identify such SoCs. Also when PSP uses A/B recovery layout, BIOS L2 directory is an entry in the PSP L2 directory. Hence the address of BIOS L2 directory is not part of EFS2 header. Thankfully PSP is able to identify the BIOS L2 directory itself and does not expect PSP verstage to pass the address. Modify PSP verstage to handle these updates. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that PSP verstage returned the PSP L2 directory as expected. Change-Id: I2f856a62055c80b8e2db91c983832611a5f0389c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* treewide: Remove unused <cpu/x86/msr.h>Elyes Haouas2022-07-201-1/+0
| | | | | | | | Change-Id: I187c2482dd82c6c6d1fe1cbda71710ae1a2f54ad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: Don't add bitsElyes Haouas2022-07-181-1/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id56310bd616cd19fee5dc934676006b2dc34b1ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/65929 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common: Fix some white spaces issuesElyes Haouas2022-07-179-16/+16
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I54438978db13ba00188e53239f7034d1b258e912 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/[cezanne,picasso,sabrina]/Kconfig: Add PSP_APOB_DRAM_SIZE config optionFred Reitberger2022-07-161-2/+2
| | | | | | | | | | | | | | | | | | | | The APOB in sabrina is larger than in cezanne/picasso and no longer fits in the previously allocated 64K space for it. Other symbols are placed immediately after the APOB region and end up corrupting the APOB data on sabrina. Add a Kconfig option to specify the APOB size in DRAM to reserve enough memory and increase the size for sabrina to 128K TEST=Timeless builds are identical for mandolin/majolica for PCO/CZN. Build chausie and verify symbols do not overlap _apob region BUG=b:224056176 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia5dbacae67ff02fc8a6ec84b9007110ca254daa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* commonlib: Substitude macro "__unused" in compiler.hBill XIE2022-07-142-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/amd/fsp: Cache smm_region() resultsArthur Heymans2022-07-141-5/+11
| | | | | | | | | | | This avoids searching the HOB output multiple times when calling smm_region(). Change-Id: Iad09c3aa3298745ba3ba7012e6bb8cfb8785d525 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cpu/amd: Add common helpers for TSEG and SMMArthur Heymans2022-07-133-17/+38
| | | | | | | | Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/block/lpc/lpc.c: Remove duplicated includeElyes Haouas2022-07-081-1/+0
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Idd214893f304ce767633ffbf905f47a5092c2ee4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/psp: Revert AMD_SOC_SEPARATE_EFS_SECTIONFred Reitberger2022-06-303-22/+0
| | | | | | | | | | | | | | | | Reverting commit 1e25fd426ad8 ("soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTION"). A better solution was used in commit c17330c1dddb ("mb/amd/chausie: Add EC blob into CBFS"), and this is no longer necessary. TEST: Boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I27a8622a1f0d871690b181a79adca225a20996ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc,sb/amd: Change SPI controller resourceKyösti Mälkki2022-06-281-2/+1
| | | | | | | | | | This replaces IORESOURCE_SUBTRACTIVE with IORESOURCE_RESERVE. Change-Id: Ib3d934ca704273daacbeb3c52412bf04e2be7217 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64695 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/noncar/cpu: Provide correct smbios processor familyFred Reitberger2022-06-241-0/+6
| | | | | | | | | | | | | | | | Return the correct processor family code for smbios per System Management BIOS (SMBIOS) Reference Specification DSP0134 revision 3.5.0. BUG=b:234409052 TEST=Boot chausie to chromeos and verify "dmidecode -t processor" outputs the correct processor family. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I617ce3e23f4b28a197034756d285339595d3b53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65364 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-222-2/+2
| | | | | | | | | | | | There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/*/Kconfig: drop unused SOC_AMD_COMMON_BLOCK_UCODE_SIZE optionFelix Held2022-06-211-6/+0
| | | | | | | | | | | | | | | | Commit 96f7b96866b0bce7a1323c4da478f838f884383f (soc/amd/common/block/ cpu/: Make ucode update more generic) removed the code that used the SOC_AMD_COMMON_BLOCK_UCODE_SIZE Kconfig value. Drop the now unused Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I079f229678452ff20d8bb282804cd2e49555a6fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65255 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/common/i2c: Add i2c bus ops handlerMatt DeVillier2022-06-211-0/+1
| | | | | | | | | | | | | | Without this, calls to i2c_link() and runtime i2c detection fails on AMD common platform boards. Test: Runtime i2c detection of correct touchpad model succeeds on google/zork. Change-Id: I238b680b2afb4b9d3e5ac75fe9e630b2adc74860 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/*: Move selection of DRIVERS_I2C_DESIGNWARE to common blockMatt DeVillier2022-06-211-0/+1
| | | | | | | | | | | | | | All AMD SoCs which select SOC_AMD_COMMON_BLOCK_I2C also select DRIVERS_I2C_DESIGNWARE, so make the pairing explicit by moving the selection into SOC_AMD_COMMON_BLOCK_I2C. This will facilitating adding the Designware I2C bus ops handler in a subsequent commit. Change-Id: Ice30c8806766deb9a6ba617c3e633ab069af3b46 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/smm_relocate.c: Improve TSEG programmingArthur Heymans2022-06-172-23/+26
| | | | | | | | | | | | | | TSEG does not need to be aligned to 128KiB but to its size, as the MSR works like an MTRR. 128KiB is a minimum TSEG size however. TESTED on google/vilboz. Change-Id: I30854111bb47f0cb14b07f71cedacd629432e0f4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64865 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* Replace some ENV_ROMSTAGE with ENV_RAMINITKyösti Mälkki2022-06-072-3/+3
| | | | | | | | | | | | | With a combined bootblock+romstage ENV_ROMSTAGE might no longer evaluate true. Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/cpu/: Make ucode update more genericFred Reitberger2022-06-073-43/+47
| | | | | | | | | | | | | | | | Use the equivalent cpuid in the microcode header to name the update file in cbfs. This allows the SOC to directly locate its microcode file when there are multiple processor revisions. TEST: Loaded a chausie with sabrina, cezanne, and picasso microcode files and booted. Verified that only the sabrina microcode file was successfully loaded Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* amdblocks/smm.h: Add header guardsArthur Heymans2022-06-031-0/+5
| | | | | | | | | | Change-Id: I5d01c36fa4695ee42d18701a90d1b96bceb5045f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* arch/x86/acpi_bert_storage.c: Use a common implementationArthur Heymans2022-05-251-8/+0
| | | | | | | | | | | | | | | | All targets now use cbmem for the BERT region, so the implementation can be common. This also drops the obsolete comment about the need to have bert in a reserved region (cbmem gets fixed to be in a reserved region). Change-Id: I6f33d9e05a02492a1c91fb7af94aadaa9acd2931 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* security/tpm/crtm: Add a function to measure the bootblock on SoC levelWerner Zeh2022-05-242-0/+9
| | | | | | | | | | | | | | | | | On platforms where the bootblock is not included in CBFS anymore (because it is part of another firmware section (IFWI or a different CBFS), the CRTM measurement fails. This patch adds a new function to provide a way at SoC level to measure the bootblock. Following patches will add functionality to retrieve the bootblock from the SoC related location and measure it from there. In this way the really executed code will be measured. Change-Id: I6d0da1e95a9588eb5228f63151bb04bfccfcf04b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* CBMEM: Change declarations for initialization hooksKyösti Mälkki2022-05-202-2/+2
| | | | | | | | | | | | | | | | | | There are efforts to have bootflows that do not follow a traditional bootblock-romstage-postcar-ramstage model. As part of that CBMEM initialisation hooks will need to move from romstage to bootblock. The interface towards platforms and drivers will change to use one of CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called in the first stage with CBMEM available. Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/block/psp/psp_gen2: move SPL fusing earlier to BS_PAYLOAD_LOADFelix Held2022-05-171-1/+1
| | | | | | | | | | | | | | | | | The psp_notify_boot_done call is done at the entry of BS_PAYLOAD_BOOT, so it's not guaranteed that the psp_set_spl_fuse call is done before the psp_notify_boot_done call. Moving the psp_set_spl_fuse call makes sure that it's done before the psp_notify_boot_done call. This also brings the psp_set_spl_fuse call in line with the enable_secure_boot call that sends the PSB fusing command to the PSP. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id76b462608c3d788cd90e73a64d18c8e8b89dbfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* acpi, arch/x86/smp/mpspec,soc/amd/common: Move MP_IRQ_ flags into acpi.hRaul E Rangel2022-05-161-1/+1
| | | | | | | | | | | | | | | The MP_IRQ flags can be used in the MP table and the ACPI MADT table. Move them into acpi.h to avoid pulling in the full mpspec.h which is only available on x86. BUG=b:218874489, b:160595155 TEST=Build Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f1091b7629a6446fa399720b0270556a926401a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63845 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/psp: Add platform secure boot supportRitul Guru2022-05-165-2/+176
| | | | | | | | | | | | | | Add Platform Secure Boot (PSB) enablement via the PSP if it is not already enabled. Upon receiving psb command, PSP will program PSB fuses as long as BIOS signing key token is valid. Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is only available with NDA customers. Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* arch/x86/postcar: Set up postcar MTRR in C codeArthur Heymans2022-05-161-6/+17
| | | | | | | | | | | | | | | | | Setting up postcar MTRRs is done when invd is already called so there is no reason to do this in assembly anymore. This also drops the custom code for Quark to set up MTRRs. TESTED on foxconn/g41m and hermes/prodrive that MTRR are properly set in postcar & ramstage. Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54299 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/non-car: Don't add bootblock cbfs fileArthur Heymans2022-05-121-0/+4
| | | | | | | | | | | | | The bootblock.elf file gets embedded in the BIOSPSP part and loaded by the PSP in dram. The top aligned bootblock in cbfs is unused. Tested on Cezanne/Guybrush. Change-Id: I72f0092e0e3628b388f6da6a417c2857a510b187 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/picasso: Use read*pArthur Heymans2022-05-062-8/+8
| | | | | | | | | | | This avoids compiler warnings on 64bit builds that complains about casting pointer to non matching integer size. Change-Id: I29fdb73ae1c0508796a21b650bf4fd1ac6688021 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/common/block/psp/psp_gen2: simplify soc_read_c2p38Felix Held2022-05-062-11/+4
| | | | | | | | | | | | | | | | Commit 198cc26e4951b3dbca588286706b7df562c45d42 (soc/amd/common/block/ psp/psp_gen2: use SMN access to PSP) changed how the PSP registers are accessed. Since the new method doesn't need to rely on a MMIO base address to be configured, the read will always be successful and so soc_read_c2p38 doesn't need to return an error status and can directly return the value instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1abace04668947ba3223a107461a27dddc0a9d83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/include/espi: reduce visibility of IO/MMIO decode definesFelix Held2022-05-062-65/+68
| | | | | | | | | | | | | | | | | The eSPI decode range defines aren't and shouldn't be used directly from outside of the common AMD eSPI code which provides functions to abstract the register access, so move the defines from amdblocks/espi.h to espi_def.h inside the common AMD LPC/eSPI support directory to limit the visibility. The special I/O range decode bits need to stay in amdblocks/espi.h since those are used in the devicetree. Also update the indentation in espi_def.h so that the defines line up properly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic4ea30a1a6f10e94d88bf3b29f86dee2da6b39b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64053 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/include/espi: generalize IO/MMIO decode range macrosFelix Held2022-05-062-8/+8
| | | | | | | | | | | | | | | | | | | Sabrina has more eSPI decode ranges than Picasso or Cezanne. Those registers are however not in one block where it's easy to calculate the addresses of a register from the index of the decode range. Within one group of decode range registers it's still easy to calculate the register address, so move the base address from within the macro to the instantiation of the macro as a preparation for adding the support for the additional ranges. TEST=Timeless build results in identical binary for Mandolin Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id309d955fa3558d660db37a2075240f938361e83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/common/block/psp/psp_gen2: use SMN access to PSPFelix Held2022-05-042-40/+26
| | | | | | | | | | | | | | | | | | Since we can't rely on the MMIO base address in the PSP_ADDR_MSR MSR to access the PSP mailbox registers, switch to using the SMN mapping of the PSP mailbox registers. The PSP SMN base address is taken from the amdgpu driver in the Linux kernel. BUG=b:229779018 TEST=Mandolin still boots successfully and there are no errors/warnings about possibly PSP-related things. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d17e523e9ae8d8e14ecedc37131a81f82351487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64034 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/psp/psp_gen2: move CORE_2_PSP_MSG_38 definesFelix Held2022-05-042-3/+3
| | | | | | | | | | | | | CORE_2_PSP_MSG_38_OFFSET and CORE_2_PSP_MSG_38_FUSE_SPL are only used in psp_gen2.c, so move them into this file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67cc2ff63d1c0322b514521975f3ce0f9b1cf5b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/common/block/spi: Pretty print SPI statusRaul E Rangel2022-05-021-2/+12
| | | | | | | | | | | | | | | | I find it difficult to constantly decode the registers when reading them. Let's print out something that's easier to parse. BUG=b:228289365 TEST=boot guybrush and see status codes printed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6c9d98cf43f340cf50e12c93b4c35187de9bb750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/block/spi: Print error when SPI bus can't be acquiredRaul E Rangel2022-05-021-1/+3
| | | | | | | | | | | | | | Silently failing makes it hard to debug when something goes wrong. BUG=b:228289365 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7423a7011e7656414155386c014a9a0f2fad4abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/block/psp/psp_gen2: drop unneeded variable initializationFelix Held2022-05-021-2/+2
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9a3ec9565e660d5fad61c7e73d56f2f821e152aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/63967 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/psp/psp_gen2: use offsets to access mailboxFelix Held2022-05-021-32/+20
| | | | | | | | | | | | Drop struct pspv2_mbox and access the PSP mailbox via their offsets into PSP MMIO region. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib665d7ae19deae07d6a69c11ba8cf44e45ea4e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63966 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/psp/psp_gen2: use read32p instead of typecastFelix Held2022-05-021-1/+1
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I50b8fc270669f079d4f2ec21aec40388afc1705f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63965 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/psp/psp_gen2: use union pspv2_mbox_commandFelix Held2022-05-021-12/+3
| | | | | | | | | | | | Don't use unnamed redefinitions of the pspv2_mbox_command union when the union definition can be used instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3757db45272f11bb47e5106ad9054c0a9ca0cd52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/common/block/psp/psp_gen2: factor out pspv2_mbox_command unionFelix Held2022-05-021-16/+18
| | | | | | | | | | | | | | | | | The pspv2_mbox struct contained an unnamed union that covered the 32 bits of the command register of the PSP v2 mailbox. Since the pspv2_mbox struct is mainly used for hardware register accesses and the union part is mostly used to access the different bits before/after writing/reading the command register, split this functionality. For the register access a command field is added to the pspv2_mbox struct instead of the unnamed union and for accessing the separate bits of the command register a new named union is added. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If3f00b6fd73c3f749154b77b940e6d5aa385ec49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/psp/psp_gen2: rename cmd_response to bufferFelix Held2022-05-021-4/+4
| | | | | | | | | | | | | | The cmd_response field in the pspv2_mbox struct is the buffer used to pass data to the PSP and back to the x86 side, so rename it to buffer. This also aligns the code a bit more with the reference code. Also rename the wr_mbox_cmd_resp function to wr_mbox_buffer_ptr. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22c8971b07b3dedcc2e6e50e93c98d69ec7379e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63962 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/psp/psp: remove unneeded line breakFelix Held2022-05-021-2/+1
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0f2fa245be6f7fabde53bfc45c1af73fa13fe862 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63961 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/psp: move mbox struct to generation-specific codeFelix Held2022-05-023-32/+33
| | | | | | | | | | | | | The pspv[1,2]_mbox struct is only used in psp_gen[1,2].c, so move those definitions from the common psp_def.h to the specific psp_gen[1,2].c files. Also fix the struct name in the comment about pspv1_mbox. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0c95e9a6e292b90e0d147c57f59828a9b41e4b82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63960 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/lpc/espi: Add support for ALERT_ENABLE bitRaul E Rangel2022-04-273-3/+15
| | | | | | | | | | | | | | | This bit is new on sabrina. We need to enable it after initialization has completed. BUG=b:227282870 TEST=Boot skyrim to OS and verify keyboard works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I795275993589e20c1d09674232ecff782c491335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* amdfwtool: Change the name of macros for 'BHD'Zheng Bao2022-04-252-4/+4
| | | | | | | | | | | | | Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/common/block/i2c/i23c_pad_ctrl: only configure mode and voltageFelix Held2022-04-011-7/+0
| | | | | | | | | | | | | | | | | | | The fch_i23c_pad_init implementation was written without looking at any reference code and turned out to not work properly on hardware. Before this function writes to the MISC_I23C_PAD_CTRL registers, the value read back is 0x3000003c which results in the I2C bus communication to work while the 0x300003fc the code writes to the register breaks the I2C communication. Removing the code that sets bits 6..9 fixes the I2C bus communication. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie6758b3d13c59b20ce810225fca8a365713b7a2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63234 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/i2c/i23c_pad_ctrl: invert and maskFelix Held2022-04-011-1/+1
| | | | | | | | | | | | When masking out bits with an and mask, the bit mask needs to be inverted. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9739d7150e230fbbe6523413de9c07d7340f3c61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63222 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-21 04:45:43 +0000