coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver	Raul E Rangel	2021-05-12	1	-191/+0
*	soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRT	Raul E Rangel	2021-05-09	1	-63/+1
*	soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data	Raul E Rangel	2021-05-09	1	-29/+0
*	soc/amd/picasso: Migrate to struct pci_routing_info	Raul E Rangel	2021-05-09	1	-46/+21
*	soc/amd/{picasso/common}: Move populate_pirq_data prototype to common	Raul E Rangel	2021-05-06	1	-1/+0
*	acpi/acpigen.h: Add more intuitive AML package closing functions	Jakub Czapiga	2021-03-22	1	-1/+0
*	acpi: Move PCI functions to separate file	Tim Wawrzynczak	2021-03-01	1	-0/+1
*	soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI code	Felix Held	2021-02-02	1	-3/+3
*	soc/amd/picasso/pcie_gpp: Remove duplication in pirq_data declaration	Raul E Rangel	2021-01-23	1	-17/+3
*	soc/amd/picasso/pci_gpp: Replace the swizzle string with a u8 array	Raul E Rangel	2021-01-23	1	-11/+11
*	soc/amd/picasso/pcie_gpp: Add clarifying comment	Raul E Rangel	2021-01-23	1	-0/+2
*	soc/amd/picasso: Generate GNB IO-APIC PCI routing table	Raul E Rangel	2021-01-08	1	-30/+100
*	soc/amd/picasso: Correctly populate the PCI interrupt line register	Raul E Rangel	2021-01-06	1	-0/+45
*	soc/amd/picasso: Fix ACPI PCI routing table	Raul E Rangel	2021-01-06	1	-2/+154
*	include/device/pci_ids: add model number to PCIe port and bus devices	Felix Held	2020-11-18	1	-3/+3
*	soc/amd/picasso: Split ops for internal and external PCIe GPP bridges	Furquan Shaikh	2020-07-30	1	-4/+20
*	soc/amd/picasso: Add driver for handling PCIE GPP bridges	Furquan Shaikh	2020-07-10	1	-0/+60