| Commit message (Collapse) | Author | Age | Files | Lines |
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'Mendocino' was an embargoed name and could previously not be used
in references to Skyrim. coreboot has references to sabrina both
in directory structure and in files. This will make life difficult
for people looking for Mendocino support in the long term. The code
name should be replaced with "mendocino".
BUG=b:239072117
TEST=Builds
Cq-Depend: chromium:3764023
Cq-Depend: chromium:3763392
Cq-Depend: chrome-internal:4876777
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Replace the Renoir/Cezanne PCI IDs with the Sabrina ones that were added
in commit 27b02c2eee68f4b6c8520c4737224aaaf81f137d (include/device/
pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoC).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I427df6f8e8c08fb47ae8513b6cf1085d4294e28f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The Cezanne SoC code was initially started as a copy of example/min86
which only provides enough code to make the SoC code build. Then the
different parts of the real SoC support was brought in patch by patch
which also helped cleaning up and untangling the code. Since the Cezanne
SoC code is now in a rather good shape and the Sabrina SoC is similar to
the Cezanne SoC from the coreboot side, the new SoC support is started
with a copy of the Cezanne code and all the needed changes will be
applied on top of that. In order for the build not to fail due to
duplicate files, this patch does not only copy the directory, but also
replaces most instances of the Cezanne name with Sabrina. Since the
needed blobs aren't available in the 3rdparty/amd_blobs repository yet,
the Cezanne blobs are used for now so that the build will succeed. As
soon as the proper blobs will be available in that repository, the code
will be switched over to use them.
As suggested by Nico, I added a "TODO: Check if this is still correct"
comment to the beginning of every copied file and all SOC_AMD_COMMON_*
Kconfig option selects which will be removed after re-verifying that
each file and each selected common code block is still correct for the
new SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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