coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/sifive/fu540: Add chip_operations stub	Kyösti Mälkki	2020-05-28	1	-0/+1
*	src: Remove leading blank lines from SPDX header	Elyes HAOUAS	2020-05-18	1	-2/+0
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi	2020-05-09	1	-8/+1
*	soc: Remove copyright notices	Patrick Georgi	2020-03-18	1	-1/+0
*	soc/sifive/fu540: add code for spi and map flash to memory spaces	Xiang Wang	2019-08-12	1	-3/+3
*	soc/sifive/fu540: Simplify UART refclk calculation	Jonathan Neuschäfer	2018-12-03	1	-0/+1
*	riscv: add support smp_pause / smp_resume	Xiang Wang	2018-11-05	1	-0/+1
*	sifive/hifive-unleashed: enable CBMEM support	Philipp Hug	2018-09-15	1	-0/+1
*	soc/sifive/fu540: Switch clock to 1GHz in romstage	Philipp Hug	2018-09-14	1	-0/+2
*	soc/sifive/fu540: Makefile: include mtime_init in ramstage	Philipp Hug	2018-09-10	1	-0/+1
*	soc/sifive/fu540: Add driver for OTP memory	Philipp Hug	2018-09-10	1	-0/+2
*	soc/sifive/fu540: add CLINT support	Xiang Wang	2018-09-10	1	-1/+1
*	riscv: update mtime initialization	Xiang Wang	2018-09-10	1	-0/+1
*	sifive/fu540: add empty sdram init and size functions	Philipp Hug	2018-07-18	1	-0/+2
*	src/sifive: Add the SiFive Freedom Unleashed 540 SoC	Jonathan Neuschäfer	2018-04-26	1	-0/+33