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* soc/amd/{common,cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZERaul E Rangel2022-01-235-5/+56
* soc/intel/alderlake: Implement get_soc_cpu_type helper functionSridhar Siricilla2022-01-221-0/+21
* soc/intel/common/cse: Add support to get CSME timestampsBora Guvendik2022-01-213-0/+170
* soc/intel/common/gpio: Add PCH `Pad Configuration Lock` optionsSubrata Banik2022-01-211-0/+15
* soc/intel/common/gpio: Use const variable to get gpio bitmaskSubrata Banik2022-01-211-1/+3
* soc/intel/alderlake: Add ADL-P 2+8+2 (28W) VR configCurtis Chen2022-01-213-3/+8
* soc/intel/ehl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-212-9/+1
* soc/intel/icl: Rework on HECI1 disable configsSubrata Banik2022-01-213-10/+5
* soc/amd/picasso/bootblock: drop unused includesFelix Held2022-01-201-4/+0
* soc/amd/cezanne,picasso: factor out common early non-car cache setupFelix Held2022-01-205-155/+85
* soc/amd/cezanne/include/espi.h: add missing include guardsFelix Held2022-01-201-0/+5
* soc/amd/common/vboot: Verify the size of the transfer bufferRaul E Rangel2022-01-201-1/+1
* soc/intel/alderlake: Add method to determine the cpu typeSridahr Siricilla2022-01-194-0/+82
* soc/intel/common/cpu: Use SoC overrides to get CPU privilege levelSubrata Banik2022-01-1920-4/+116
* soc/intel/alderlake: Rework the GPIO PAD Pin numbersSubrata Banik2022-01-191-420/+485
* soc/amd/{picasso,cezanne}: Enable CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTSRaul E Rangel2022-01-182-0/+2
* soc/intel/alderlake: Add eMMC device into chipset.cbKrishna Prasad Bhat2022-01-181-0/+2
* soc/intel/common: Add Alder Lake N eMMC device IDKrishna Prasad Bhat2022-01-181-0/+1
* soc/intel/{adl,common}: Support alderlake host device id 0x4619Kane Chen2022-01-183-0/+3
* pci_ids.h: Make Denverton IDs consistent with other Intel SoCsJeff Daly2022-01-179-12/+12
* soc/intel/cnl: Use Kconfig to disable HECI1Subrata Banik2022-01-173-5/+5
* src: Remove unused <cbfs.h>Elyes HAOUAS2022-01-171-1/+0
* soc/intel/common/cse: Add helper API for CSE SPI Protection ModeSubrata Banik2022-01-162-0/+22
* soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-163-13/+4
* soc/intel/common: Abstract the sideband accessJohn Zhao2022-01-164-6/+9
* soc/intel/denverton_ns: Add the Primary to Sideband Bridge definitionJohn Zhao2022-01-161-0/+1
* soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-142-9/+1
* soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-142-9/+1
* soc/amd/cezanne: factor out eSPI SPI2 pads configuration functionsFelix Held2022-01-143-0/+38
* soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner2022-01-142-0/+3
* soc/intel/tgl: deduplicate the PCIe root port mapMichael Niewöhner2022-01-141-17/+2
* soc/intel/tgl/pcie_rp: add TGL-H supportMichael Niewöhner2022-01-142-1/+21
* soc/amd/*/chip.h: add missing gpio.h includeFelix Held2022-01-133-0/+3
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04Nick Vaccaro2022-01-132-27/+27
* soc/mediatek: Fix include guard naming for emi.hYu-Ping Wu2022-01-131-3/+3
* soc/intel/common/gpio: Fix cosmetic issue with `gpio_lock_pads`Subrata Banik2022-01-121-3/+4
* sc7180: Update video mode active horizontal/vertical/total calculationsVinod Polimera2022-01-121-13/+6
* soc/intel/tigerlake: Implement function to map physical port to EC portjzhao802022-01-122-0/+33
* soc/intel/tgl/pcie_rp: correct root port mapMichael Niewöhner2022-01-121-2/+1
* soc/amd/common/block: add new PCI IDs to common codeFelix Held2022-01-123-0/+4
* soc/amd/cezanne/include/i2c: add missing types.h includeFelix Held2022-01-111-0/+1
* soc/amd/cezanne/include/i2c: move include inside header guardFelix Held2022-01-111-2/+2
* soc/intel/apl: Use Kconfig to disable HECI1Subrata Banik2022-01-112-1/+5
* soc/intel/alderlake: Factor out A0 stepping workaroundAngel Pons2022-01-115-0/+104
* soc/intel/apl: Rework on CPU privilege level implementationSubrata Banik2022-01-116-23/+16
* src/soc/qualcomm: Remove unused <delay.h>Elyes HAOUAS2022-01-105-5/+0
* src/soc: Remove unused <stdlib.h>Elyes HAOUAS2022-01-104-4/+0
* src/soc/qualcomm: Remove unused <console/console.h>Elyes HAOUAS2022-01-101-1/+0
* src/soc/intel: Remove unused <console/console.h>Elyes HAOUAS2022-01-106-6/+0
* src/soc/amd: Remove unused <console/console.h>Elyes HAOUAS2022-01-1010-10/+0
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