UefiCpuPkg: Apply uncrustify changes

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the UefiCpuPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

15 files changed, 182 insertions, 140 deletions

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
index 80a7df2957..beda97e238 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
@@ -23,7 +23,7 @@ AesniGetConfigData (
   IN UINTN  NumberOfProcessors

   )

 {

-  UINT64                            *ConfigData;

+  UINT64  *ConfigData;

 

   ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);

   ASSERT (ConfigData != NULL);

@@ -54,14 +54,15 @@ AesniSupport (
   IN VOID                              *ConfigData  OPTIONAL

   )

 {

-  MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER   *MsrFeatureConfig;

+  MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER  *MsrFeatureConfig;

 

   if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) {

-    MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;

+    MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;

     ASSERT (MsrFeatureConfig != NULL);

     MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);

     return TRUE;

   }

+

   return FALSE;

 }

 

@@ -91,7 +92,7 @@ AesniInitialize (
   IN BOOLEAN                           State

   )

 {

-  MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER   *MsrFeatureConfig;

+  MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER  *MsrFeatureConfig;

 

   //

   // SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index,

@@ -102,7 +103,7 @@ AesniInitialize (
   // programming it.

   //

   if (CpuInfo->ProcessorInfo.Location.Thread == 0) {

-    MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;

+    MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;

     ASSERT (MsrFeatureConfig != NULL);

     if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) {

       CPU_REGISTER_TABLE_WRITE_FIELD (

@@ -115,5 +116,6 @@ AesniInitialize (
         );

     }

   }

+

   return RETURN_SUCCESS;

 }

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
index 98a3408370..bc09f8bc62 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
@@ -66,7 +66,7 @@ C1eInitialize (
   // MSR_NEHALEM_POWER_CTL once for each package.

   //

   if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {

-  return RETURN_SUCCESS;

+    return RETURN_SUCCESS;

   }

 

   CPU_REGISTER_TABLE_WRITE_FIELD (

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
index 94d596605b..5874a99570 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
@@ -9,8 +9,8 @@
 #include "CpuCommonFeatures.h"

 

 typedef struct  {

-  CPUID_THERMAL_POWER_MANAGEMENT_EAX  ThermalPowerManagementEax;

-  MSR_IA32_CLOCK_MODULATION_REGISTER  ClockModulation;

+  CPUID_THERMAL_POWER_MANAGEMENT_EAX    ThermalPowerManagementEax;

+  MSR_IA32_CLOCK_MODULATION_REGISTER    ClockModulation;

 } CLOCK_MODULATION_CONFIG_DATA;

 

 /**

@@ -28,7 +28,7 @@ ClockModulationGetConfigData (
   IN UINTN  NumberOfProcessors

   )

 {

-  UINT32    *ConfigData;

+  UINT32  *ConfigData;

 

   ConfigData = AllocateZeroPool (sizeof (CLOCK_MODULATION_CONFIG_DATA) * NumberOfProcessors);

   ASSERT (ConfigData != NULL);

@@ -59,10 +59,10 @@ ClockModulationSupport (
   IN VOID                              *ConfigData  OPTIONAL

   )

 {

-  CLOCK_MODULATION_CONFIG_DATA         *CmConfigData;

+  CLOCK_MODULATION_CONFIG_DATA  *CmConfigData;

 

   if (CpuInfo->CpuIdVersionInfoEdx.Bits.ACPI == 1) {

-    CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData;

+    CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData;

     ASSERT (CmConfigData != NULL);

     AsmCpuid (

       CPUID_THERMAL_POWER_MANAGEMENT,

@@ -74,6 +74,7 @@ ClockModulationSupport (
     CmConfigData[ProcessorNumber].ClockModulation.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);

     return TRUE;

   }

+

   return FALSE;

 }

 

@@ -103,15 +104,15 @@ ClockModulationInitialize (
   IN BOOLEAN                           State

   )

 {

-  CLOCK_MODULATION_CONFIG_DATA         *CmConfigData;

-  MSR_IA32_CLOCK_MODULATION_REGISTER   *ClockModulation;

+  CLOCK_MODULATION_CONFIG_DATA        *CmConfigData;

+  MSR_IA32_CLOCK_MODULATION_REGISTER  *ClockModulation;

 

-  CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData;

+  CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData;

   ASSERT (CmConfigData != NULL);

   ClockModulation = &CmConfigData[ProcessorNumber].ClockModulation;

 

   if (State) {

-    ClockModulation->Bits.OnDemandClockModulationEnable = 1;

+    ClockModulation->Bits.OnDemandClockModulationEnable    = 1;

     ClockModulation->Bits.OnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1;

     if (CmConfigData[ProcessorNumber].ThermalPowerManagementEax.Bits.ECMD == 1) {

       ClockModulation->Bits.ExtendedOnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0;

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
index 74f27dcc44..5434a45f6a 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
@@ -860,7 +860,7 @@ X2ApicInitialize (
 VOID *

 EFIAPI

 PpinGetConfigData (

-  IN UINTN               NumberOfProcessors

+  IN UINTN  NumberOfProcessors

   );

 

 /**

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
index 725ef7bd43..7f0e1004b9 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
@@ -20,7 +20,7 @@ CpuCommonFeaturesLibConstructor (
   VOID

   )

 {

-  RETURN_STATUS         Status;

+  RETURN_STATUS  Status;

 

   if (IsCpuFeatureSupported (CPU_FEATURE_AESNI)) {

     Status = RegisterCpuFeature (

@@ -33,6 +33,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_MWAIT)) {

     Status = RegisterCpuFeature (

                "MWAIT",

@@ -44,6 +45,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_ACPI)) {

     Status = RegisterCpuFeature (

                "ACPI",

@@ -55,6 +57,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_EIST)) {

     Status = RegisterCpuFeature (

                "EIST",

@@ -66,6 +69,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_FASTSTRINGS)) {

     Status = RegisterCpuFeature (

                "FastStrings",

@@ -77,6 +81,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) {

     Status = RegisterCpuFeature (

                "Lock Feature Control Register",

@@ -88,6 +93,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) {

     Status = RegisterCpuFeature (

                "SMX",

@@ -100,6 +106,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) {

     Status = RegisterCpuFeature (

                "VMX",

@@ -112,6 +119,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_LIMIT_CPUID_MAX_VAL)) {

     Status = RegisterCpuFeature (

                "Limit CpuId Maximum Value",

@@ -123,6 +131,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_MCE)) {

     Status = RegisterCpuFeature (

                "Machine Check Enable",

@@ -134,6 +143,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_MCA)) {

     Status = RegisterCpuFeature (

                "Machine Check Architect",

@@ -145,6 +155,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_MCG_CTL)) {

     Status = RegisterCpuFeature (

                "MCG_CTL",

@@ -156,6 +167,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_PENDING_BREAK)) {

     Status = RegisterCpuFeature (

                "Pending Break",

@@ -167,6 +179,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_C1E)) {

     Status = RegisterCpuFeature (

                "C1E",

@@ -178,6 +191,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) {

     Status = RegisterCpuFeature (

                "X2Apic",

@@ -189,6 +203,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) {

     Status = RegisterCpuFeature (

                "PPIN",

@@ -200,6 +215,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) {

     Status = RegisterCpuFeature (

                "LMCE",

@@ -212,6 +228,7 @@ CpuCommonFeaturesLibConstructor (
                );

     ASSERT_EFI_ERROR (Status);

   }

+

   if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) {

     Status = RegisterCpuFeature (

                "Proc Trace",

@@ -226,6 +243,3 @@ CpuCommonFeaturesLibConstructor (
 

   return RETURN_SUCCESS;

 }

-

-

-

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
index ed42afe289..aedf3e6f2c 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
@@ -69,7 +69,8 @@ EistInitialize (
   //

   if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

-      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

+      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))

+  {

     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {

       return RETURN_SUCCESS;

     }

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
index 9ae5216555..63c3bf9d10 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
@@ -40,7 +40,8 @@ FastStringsInitialize (
   //

   if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

-      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

+      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))

+  {

     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {

       return RETURN_SUCCESS;

     }

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
index 8ad81a6e87..63ec27a1a6 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
@@ -68,7 +68,8 @@ VmxInitialize (
   //

   if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

-      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))

+  {

     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {

       return RETURN_SUCCESS;

     }

@@ -146,7 +147,8 @@ LockFeatureControlRegisterInitialize (
   //

   if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

-      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))

+  {

     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {

       return RETURN_SUCCESS;

     }

@@ -218,7 +220,7 @@ SmxInitialize (
   IN BOOLEAN                           State

   )

 {

-  RETURN_STATUS                        Status;

+  RETURN_STATUS  Status;

 

   //

   // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for

@@ -226,7 +228,8 @@ SmxInitialize (
   // core.

   //

   if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

-      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))

+  {

     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {

       return RETURN_SUCCESS;

     }

@@ -236,7 +239,7 @@ SmxInitialize (
 

   if (State && (!IsCpuFeatureInSetting (CPU_FEATURE_VMX))) {

     DEBUG ((DEBUG_WARN, "Warning :: Can't enable SMX feature when VMX feature not enabled, disable it.\n"));

-    State = FALSE;

+    State  = FALSE;

     Status = RETURN_UNSUPPORTED;

   }

 

@@ -247,7 +250,7 @@ SmxInitialize (
     IA32_CR4,

     Bits.SMXE,

     (State) ? 1 : 0

-  )

+    )

 

   CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (

     ProcessorNumber,

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
index 71d82eab8d..bf495f96bb 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
@@ -72,7 +72,8 @@ LimitCpuidMaxvalInitialize (
       IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

-      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

+      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))

+  {

     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {

       return RETURN_SUCCESS;

     }

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
index 0e78a0ce26..d8b070d9f1 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
@@ -102,6 +102,7 @@ McaSupport (
   if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) {

     return FALSE;

   }

+

   return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1);

 }

 

@@ -144,7 +145,8 @@ McaInitialize (
       IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

-      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

+      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))

+  {

     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {

       return RETURN_SUCCESS;

     }

@@ -162,7 +164,7 @@ McaInitialize (
 

   if (State) {

     McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);

-    for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {

+    for (BankIndex = 0; BankIndex < (UINT32)McgCap.Bits.Count; BankIndex++) {

       CPU_REGISTER_TABLE_WRITE64 (

         ProcessorNumber,

         Msr,

@@ -172,7 +174,7 @@ McaInitialize (
     }

 

     if (PcdGetBool (PcdIsPowerOnReset)) {

-      for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {

+      for (BankIndex = 0; BankIndex < (UINTN)McgCap.Bits.Count; BankIndex++) {

         CPU_REGISTER_TABLE_WRITE64 (

           ProcessorNumber,

           Msr,

@@ -215,6 +217,7 @@ McgCtlSupport (
   if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {

     return FALSE;

   }

+

   McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);

   return (McgCap.Bits.MCG_CTL_P == 1);

 }

@@ -249,7 +252,7 @@ McgCtlInitialize (
     ProcessorNumber,

     Msr,

     MSR_IA32_MCG_CTL,

-    (State)? MAX_UINT64 : 0

+    (State) ? MAX_UINT64 : 0

     );

   return RETURN_SUCCESS;

 }

@@ -279,7 +282,7 @@ LmceSupport (
   IN VOID                              *ConfigData  OPTIONAL

   )

 {

-  MSR_IA32_MCG_CAP_REGISTER    McgCap;

+  MSR_IA32_MCG_CAP_REGISTER  McgCap;

 

   if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {

     return FALSE;

@@ -287,9 +290,10 @@ LmceSupport (
 

   McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);

   if (ProcessorNumber == 0) {

-    DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0)));

+    DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0)));

   }

-  return (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0);

+

+  return (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0);

 }

 

 /**

@@ -325,7 +329,8 @@ LmceInitialize (
   //

   if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

-      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

+      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))

+  {

     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {

       return RETURN_SUCCESS;

     }

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
index 9fcbaf8d5d..d55cf6c6f2 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
@@ -70,7 +70,8 @@ MonitorMwaitInitialize (
       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

-      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

+      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))

+  {

     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {

       return RETURN_SUCCESS;

     }

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
index 3d7030d609..6095dbde05 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
@@ -36,9 +36,11 @@ PendingBreakSupport (
       IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

       IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

-      IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

+      IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))

+  {

     return (CpuInfo->CpuIdVersionInfoEdx.Bits.PBE == 1);

   }

+

   return FALSE;

 }

 

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
index 468e425a0b..a7c2c12a51 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
@@ -20,10 +20,10 @@
 VOID *

 EFIAPI

 PpinGetConfigData (

-  IN UINTN               NumberOfProcessors

+  IN UINTN  NumberOfProcessors

   )

 {

-  VOID          *ConfigData;

+  VOID  *ConfigData;

 

   ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);

   ASSERT (ConfigData != NULL);

@@ -55,8 +55,8 @@ PpinSupport (
   IN VOID                              *ConfigData  OPTIONAL

   )

 {

-  MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER    PlatformInfo;

-  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER           *MsrPpinCtrl;

+  MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  PlatformInfo;

+  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER         *MsrPpinCtrl;

 

   if ((CpuInfo->DisplayFamily == 0x06) &&

       ((CpuInfo->DisplayModel == 0x3E) ||      // Xeon E5 V2

@@ -65,13 +65,14 @@ PpinSupport (
        (CpuInfo->DisplayModel == 0x55) ||      // Xeon Processor Scalable

        (CpuInfo->DisplayModel == 0x57) ||      // Xeon Phi processor 3200, 5200, 7200 series.

        (CpuInfo->DisplayModel == 0x85)         // Future Xeon phi processor

-     )) {

+      ))

+  {

     //

     // Check whether platform support this feature.

     //

     PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);

     if (PlatformInfo.Bits.PPIN_CAP != 0) {

-      MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;

+      MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;

       ASSERT (MsrPpinCtrl != NULL);

       MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);

       return TRUE;

@@ -112,9 +113,9 @@ PpinInitialize (
   IN BOOLEAN                           State

   )

 {

-  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER     *MsrPpinCtrl;

+  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  *MsrPpinCtrl;

 

-  MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;

+  MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;

   ASSERT (MsrPpinCtrl != NULL);

 

   //

@@ -143,14 +144,14 @@ PpinInitialize (
     // According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.

     //

     MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;

-    MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;

+    MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 0;

   } else {

     //

     // Disable and Lock.

     // According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.

     //

     MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;

-    MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;

+    MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 1;

   }

 

   CPU_REGISTER_TABLE_WRITE64 (

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
index e567ed54e7..04e6a60728 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
@@ -17,8 +17,7 @@
 /// be terminated by an entry with the END bit set to 1, so 2

 /// entries are required to use a single valid entry.

 ///

-#define MAX_TOPA_ENTRY_COUNT         2

-

+#define MAX_TOPA_ENTRY_COUNT  2

 

 ///

 /// Processor trace output scheme selection.

@@ -29,25 +28,25 @@ typedef enum {
 } RTIT_OUTPUT_SCHEME;

 

 typedef struct  {

-  BOOLEAN                                   TopaSupported;

-  BOOLEAN                                   SingleRangeSupported;

-  MSR_IA32_RTIT_CTL_REGISTER                RtitCtrl;

-  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER        RtitOutputBase;

-  MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER   RtitOutputMaskPtrs;

+  BOOLEAN                                    TopaSupported;

+  BOOLEAN                                    SingleRangeSupported;

+  MSR_IA32_RTIT_CTL_REGISTER                 RtitCtrl;

+  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER         RtitOutputBase;

+  MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER    RtitOutputMaskPtrs;

 } PROC_TRACE_PROCESSOR_DATA;

 

 typedef struct  {

-  UINT32                      NumberOfProcessors;

+  UINT32                       NumberOfProcessors;

 

-  UINT8                       ProcTraceOutputScheme;

-  UINT32                      ProcTraceMemSize;

+  UINT8                        ProcTraceOutputScheme;

+  UINT32                       ProcTraceMemSize;

 

-  UINTN                       *ThreadMemRegionTable;

-  UINTN                       AllocatedThreads;

+  UINTN                        *ThreadMemRegionTable;

+  UINTN                        AllocatedThreads;

 

-  UINTN                       *TopaMemArray;

+  UINTN                        *TopaMemArray;

 

-  PROC_TRACE_PROCESSOR_DATA   *ProcessorData;

+  PROC_TRACE_PROCESSOR_DATA    *ProcessorData;

 } PROC_TRACE_DATA;

 

 typedef struct {

@@ -73,10 +72,10 @@ ProcTraceGetConfigData (
 

   ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors);

   ASSERT (ConfigData != NULL);

-  ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *) ((UINT8*) ConfigData + sizeof (PROC_TRACE_DATA));

+  ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *)((UINT8 *)ConfigData + sizeof (PROC_TRACE_DATA));

 

-  ConfigData->NumberOfProcessors = (UINT32) NumberOfProcessors;

-  ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);

+  ConfigData->NumberOfProcessors    = (UINT32)NumberOfProcessors;

+  ConfigData->ProcTraceMemSize      = PcdGet32 (PcdCpuProcTraceMemSize);

   ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme);

 

   return ConfigData;

@@ -107,17 +106,18 @@ ProcTraceSupport (
   IN VOID                              *ConfigData  OPTIONAL

   )

 {

-  PROC_TRACE_DATA                             *ProcTraceData;

-  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;

-  CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX   Ecx;

+  PROC_TRACE_DATA                              *ProcTraceData;

+  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX  Ebx;

+  CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX    Ecx;

 

   //

   // Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)

   //

-  ProcTraceData = (PROC_TRACE_DATA *) ConfigData;

+  ProcTraceData = (PROC_TRACE_DATA *)ConfigData;

   ASSERT (ProcTraceData != NULL);

   if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||

-      (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) {

+      (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA))

+  {

     return FALSE;

   }

 

@@ -130,12 +130,13 @@ ProcTraceSupport (
   }

 

   AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);

-  ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1);

-  ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1);

+  ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported        = (BOOLEAN)(Ecx.Bits.RTIT == 1);

+  ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN)(Ecx.Bits.SingleRangeOutput == 1);

   if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||

-      (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) {

-    ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);

-    ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);

+      (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)))

+  {

+    ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64           = AsmReadMsr64 (MSR_IA32_RTIT_CTL);

+    ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64     = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);

     ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);

     return TRUE;

   }

@@ -170,36 +171,37 @@ ProcTraceInitialize (
   IN BOOLEAN                           State

   )

 {

-  UINT32                               MemRegionSize;

-  UINTN                                Pages;

-  UINTN                                Alignment;

-  UINTN                                MemRegionBaseAddr;

-  UINTN                                *ThreadMemRegionTable;

-  UINTN                                Index;

-  UINTN                                TopaTableBaseAddr;

-  UINTN                                AlignedAddress;

-  UINTN                                *TopaMemArray;

-  PROC_TRACE_TOPA_TABLE                *TopaTable;

-  PROC_TRACE_DATA                      *ProcTraceData;

-  BOOLEAN                              FirstIn;

-  MSR_IA32_RTIT_CTL_REGISTER           CtrlReg;

-  MSR_IA32_RTIT_STATUS_REGISTER        StatusReg;

-  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER   OutputBaseReg;

+  UINT32                                   MemRegionSize;

+  UINTN                                    Pages;

+  UINTN                                    Alignment;

+  UINTN                                    MemRegionBaseAddr;

+  UINTN                                    *ThreadMemRegionTable;

+  UINTN                                    Index;

+  UINTN                                    TopaTableBaseAddr;

+  UINTN                                    AlignedAddress;

+  UINTN                                    *TopaMemArray;

+  PROC_TRACE_TOPA_TABLE                    *TopaTable;

+  PROC_TRACE_DATA                          *ProcTraceData;

+  BOOLEAN                                  FirstIn;

+  MSR_IA32_RTIT_CTL_REGISTER               CtrlReg;

+  MSR_IA32_RTIT_STATUS_REGISTER            StatusReg;

+  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER       OutputBaseReg;

   MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER  OutputMaskPtrsReg;

-  RTIT_TOPA_TABLE_ENTRY                *TopaEntryPtr;

+  RTIT_TOPA_TABLE_ENTRY                    *TopaEntryPtr;

 

   //

   // The scope of the MSR_IA32_RTIT_* is core for below processor type, only program

   // MSR_IA32_RTIT_* for thread 0 in each core.

   //

   if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||

-      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))

+  {

     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {

       return RETURN_SUCCESS;

     }

   }

 

-  ProcTraceData = (PROC_TRACE_DATA *) ConfigData;

+  ProcTraceData = (PROC_TRACE_DATA *)ConfigData;

   ASSERT (ProcTraceData != NULL);

 

   //

@@ -235,7 +237,7 @@ ProcTraceInitialize (
   }

 

   MemRegionBaseAddr = 0;

-  FirstIn = FALSE;

+  FirstIn           = FALSE;

 

   if (ProcTraceData->ThreadMemRegionTable == NULL) {

     FirstIn = TRUE;

@@ -245,7 +247,7 @@ ProcTraceInitialize (
   ///

   /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding

   ///

-  MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));

+  MemRegionSize = (UINT32)(1 << (ProcTraceData->ProcTraceMemSize + 12));

   if (FirstIn) {

     DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));

   }

@@ -258,32 +260,34 @@ ProcTraceInitialize (
     //   address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be

     //   aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 cleared.

     //

-    ThreadMemRegionTable = (UINTN *) AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));

+    ThreadMemRegionTable = (UINTN *)AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));

     if (ThreadMemRegionTable == NULL) {

       DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));

       return RETURN_OUT_OF_RESOURCES;

     }

+

     ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;

 

     for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {

-      Pages = EFI_SIZE_TO_PAGES (MemRegionSize);

-      Alignment = MemRegionSize;

-      AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);

+      Pages          = EFI_SIZE_TO_PAGES (MemRegionSize);

+      Alignment      = MemRegionSize;

+      AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);

       if (AlignedAddress == 0) {

         DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads));

         if (Index == 0) {

           //

           // Could not allocate for BSP even

           //

-          FreePool ((VOID *) ThreadMemRegionTable);

+          FreePool ((VOID *)ThreadMemRegionTable);

           ThreadMemRegionTable = NULL;

           return RETURN_OUT_OF_RESOURCES;

         }

+

         break;

       }

 

       ThreadMemRegionTable[Index] = AlignedAddress;

-      DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index]));

+      DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64)ThreadMemRegionTable[Index]));

     }

 

     DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads));

@@ -303,7 +307,8 @@ ProcTraceInitialize (
   //  Single Range output scheme

   //

   if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&

-      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {

+      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))

+  {

     if (FirstIn) {

       DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));

     }

@@ -322,9 +327,9 @@ ProcTraceInitialize (
     //

     // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region

     //

-    OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;

-    OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;

-    OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;

+    OutputBaseReg.Uint64      = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;

+    OutputBaseReg.Bits.Base   = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;

+    OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;

     CPU_REGISTER_TABLE_WRITE64 (

       ProcessorNumber,

       Msr,

@@ -335,9 +340,9 @@ ProcTraceInitialize (
     //

     // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)

     //

-    OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;

+    OutputMaskPtrsReg.Uint64                 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;

     OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;

-    OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;

+    OutputMaskPtrsReg.Bits.OutputOffset      = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;

     CPU_REGISTER_TABLE_WRITE64 (

       ProcessorNumber,

       Msr,

@@ -350,7 +355,8 @@ ProcTraceInitialize (
   //  ToPA(Table of physical address) scheme

   //

   if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&

-      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {

+      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA))

+  {

     //

     //  Create ToPA structure aligned at 4KB for each logical thread

     //  with at least 2 entries by 8 bytes size each. The first entry

@@ -364,35 +370,38 @@ ProcTraceInitialize (
       //

       // Let BSP allocate ToPA table mem for all threads

       //

-      TopaMemArray = (UINTN *) AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));

+      TopaMemArray = (UINTN *)AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));

       if (TopaMemArray == NULL) {

         DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));

         return RETURN_OUT_OF_RESOURCES;

       }

+

       ProcTraceData->TopaMemArray = TopaMemArray;

 

       for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {

-        Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));

-        Alignment = 0x1000;

-        AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);

+        Pages          = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));

+        Alignment      = 0x1000;

+        AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);

         if (AlignedAddress == 0) {

           if (Index < ProcTraceData->AllocatedThreads) {

             ProcTraceData->AllocatedThreads = Index;

           }

+

           DEBUG ((DEBUG_ERROR, "ProcTrace:  Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));

           if (Index == 0) {

             //

             // Could not allocate for BSP even

             //

-            FreePool ((VOID *) TopaMemArray);

+            FreePool ((VOID *)TopaMemArray);

             TopaMemArray = NULL;

             return RETURN_OUT_OF_RESOURCES;

           }

+

           break;

         }

 

         TopaMemArray[Index] = AlignedAddress;

-        DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index,  (UINT64) TopaMemArray[Index]));

+        DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64)TopaMemArray[Index]));

       }

 

       DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads));

@@ -404,26 +413,26 @@ ProcTraceInitialize (
       return RETURN_SUCCESS;

     }

 

-    TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr;

-    TopaEntryPtr = &TopaTable->TopaEntry[0];

-    TopaEntryPtr->Uint64 = 0;

-    TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;

-    TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;

-    TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;

-    TopaEntryPtr->Bits.END = 0;

+    TopaTable                 = (PROC_TRACE_TOPA_TABLE *)TopaTableBaseAddr;

+    TopaEntryPtr              = &TopaTable->TopaEntry[0];

+    TopaEntryPtr->Uint64      = 0;

+    TopaEntryPtr->Bits.Base   = (MemRegionBaseAddr >> 12) & 0x000FFFFF;

+    TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;

+    TopaEntryPtr->Bits.Size   = ProcTraceData->ProcTraceMemSize;

+    TopaEntryPtr->Bits.END    = 0;

 

-    TopaEntryPtr = &TopaTable->TopaEntry[1];

-    TopaEntryPtr->Uint64 = 0;

-    TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;

-    TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;

-    TopaEntryPtr->Bits.END = 1;

+    TopaEntryPtr              = &TopaTable->TopaEntry[1];

+    TopaEntryPtr->Uint64      = 0;

+    TopaEntryPtr->Bits.Base   = (TopaTableBaseAddr >> 12) & 0x000FFFFF;

+    TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;

+    TopaEntryPtr->Bits.END    = 1;

 

     //

     // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base

     //

-    OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;

-    OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;

-    OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;

+    OutputBaseReg.Uint64      = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;

+    OutputBaseReg.Bits.Base   = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;

+    OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;

     CPU_REGISTER_TABLE_WRITE64 (

       ProcessorNumber,

       Msr,

@@ -434,9 +443,9 @@ ProcTraceInitialize (
     //

     // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0

     //

-    OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;

+    OutputMaskPtrsReg.Uint64                 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;

     OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0;

-    OutputMaskPtrsReg.Bits.OutputOffset = 0;

+    OutputMaskPtrsReg.Bits.OutputOffset      = 0;

     CPU_REGISTER_TABLE_WRITE64 (

       ProcessorNumber,

       Msr,

@@ -458,10 +467,10 @@ ProcTraceInitialize (
   ///

   /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)

   ///

-  CtrlReg.Bits.OS = 1;

-  CtrlReg.Bits.User = 1;

+  CtrlReg.Bits.OS       = 1;

+  CtrlReg.Bits.User     = 1;

   CtrlReg.Bits.BranchEn = 1;

-  CtrlReg.Bits.TraceEn = 1;

+  CtrlReg.Bits.TraceEn  = 1;

   CPU_REGISTER_TABLE_WRITE64 (

     ProcessorNumber,

     Msr,

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
index 181dcae21c..220f307e5a 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
@@ -23,7 +23,7 @@ X2ApicGetConfigData (
   IN UINTN  NumberOfProcessors

   )

 {

-  BOOLEAN                            *ConfigData;

+  BOOLEAN  *ConfigData;

 

   ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors);

   ASSERT (ConfigData != NULL);

@@ -56,10 +56,10 @@ X2ApicSupport (
   IN VOID                              *ConfigData  OPTIONAL

   )

 {

-  BOOLEAN                            *X2ApicEnabled;

+  BOOLEAN  *X2ApicEnabled;

 

   ASSERT (ConfigData != NULL);

-  X2ApicEnabled = (BOOLEAN *) ConfigData;

+  X2ApicEnabled = (BOOLEAN *)ConfigData;

   //

   // *ConfigData indicates if X2APIC enabled on current processor

   //

@@ -94,7 +94,7 @@ X2ApicInitialize (
   IN BOOLEAN                           State

   )

 {

-  BOOLEAN                            *X2ApicEnabled;

+  BOOLEAN  *X2ApicEnabled;

 

   //

   // The scope of the MSR_IA32_APIC_BASE is core for below processor type, only program

@@ -107,7 +107,7 @@ X2ApicInitialize (
   }

 

   ASSERT (ConfigData != NULL);

-  X2ApicEnabled = (BOOLEAN *) ConfigData;

+  X2ApicEnabled = (BOOLEAN *)ConfigData;

   if (X2ApicEnabled[ProcessorNumber]) {

     PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (

       ProcessorNumber,

@@ -133,5 +133,6 @@ X2ApicInitialize (
         );

     }

   }

+

   return RETURN_SUCCESS;

 }