diff options
Diffstat (limited to 'UefiCpuPkg/Library')
61 files changed, 9312 insertions, 8715 deletions
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c index 50891618c4..5d925bc273 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c @@ -77,5 +77,5 @@ GetCpuSteppingId ( AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);
- return (UINT8) Eax.Bits.SteppingId;
+ return (UINT8)Eax.Bits.SteppingId;
}
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c index 7b4e730f98..f9e06b2fca 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -44,13 +44,14 @@ LocalApicBaseAddressMsrSupported ( AsmCpuid (1, &RegEax, NULL, NULL, NULL);
FamilyId = BitFieldRead32 (RegEax, 8, 11);
- if (FamilyId == 0x04 || FamilyId == 0x05) {
+ if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
//
// CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR
//
return FALSE;
}
+
return TRUE;
}
@@ -78,8 +79,8 @@ GetLocalApicBaseAddress ( ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
- return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
- (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
+ return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
+ (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
}
/**
@@ -93,7 +94,7 @@ GetLocalApicBaseAddress ( VOID
EFIAPI
SetLocalApicBaseAddress (
- IN UINTN BaseAddress
+ IN UINTN BaseAddress
)
{
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
@@ -109,8 +110,8 @@ SetLocalApicBaseAddress ( ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
- ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
- ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
+ ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);
+ ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
}
@@ -137,7 +138,7 @@ ReadLocalApicReg ( ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
- return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
+ return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);
}
/**
@@ -157,14 +158,14 @@ ReadLocalApicReg ( VOID
EFIAPI
WriteLocalApicReg (
- IN UINTN MmioOffset,
- IN UINT32 Value
+ IN UINTN MmioOffset,
+ IN UINT32 Value
)
{
ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
- MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
+ MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);
}
/**
@@ -177,13 +178,13 @@ WriteLocalApicReg ( **/
VOID
SendIpi (
- IN UINT32 IcrLow,
- IN UINT32 ApicId
+ IN UINT32 IcrLow,
+ IN UINT32 ApicId
)
{
- LOCAL_APIC_ICR_LOW IcrLowReg;
- UINT32 IcrHigh;
- BOOLEAN InterruptState;
+ LOCAL_APIC_ICR_LOW IcrLowReg;
+ UINT32 IcrHigh;
+ BOOLEAN InterruptState;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
ASSERT (ApicId <= 0xff);
@@ -222,7 +223,6 @@ SendIpi ( WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);
SetInterruptState (InterruptState);
-
}
//
@@ -244,21 +244,21 @@ GetApicMode ( )
{
DEBUG_CODE_BEGIN ();
- {
- MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
+ {
+ MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
+ //
+ // Check to see if the CPU supports the APIC Base Address MSR
+ //
+ if (LocalApicBaseAddressMsrSupported ()) {
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
//
- // Check to see if the CPU supports the APIC Base Address MSR
+ // Local APIC should have been enabled
//
- if (LocalApicBaseAddressMsrSupported ()) {
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
- //
- // Local APIC should have been enabled
- //
- ASSERT (ApicBaseMsr.Bits.EN != 0);
- ASSERT (ApicBaseMsr.Bits.EXTD == 0);
- }
+ ASSERT (ApicBaseMsr.Bits.EN != 0);
+ ASSERT (ApicBaseMsr.Bits.EXTD == 0);
}
+ }
DEBUG_CODE_END ();
return LOCAL_APIC_MODE_XAPIC;
}
@@ -299,9 +299,9 @@ GetInitialApicId ( VOID
)
{
- UINT32 ApicId;
- UINT32 MaxCpuIdIndex;
- UINT32 RegEbx;
+ UINT32 ApicId;
+ UINT32 MaxCpuIdIndex;
+ UINT32 RegEbx;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
@@ -338,7 +338,7 @@ GetApicId ( VOID
)
{
- UINT32 ApicId;
+ UINT32 ApicId;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
@@ -347,9 +347,10 @@ GetApicId ( // If the initial local APIC ID is less 0x100, read APIC ID from
// XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
//
- ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
+ ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
ApicId >>= 24;
}
+
return ApicId;
}
@@ -378,16 +379,16 @@ GetApicVersion ( VOID
EFIAPI
SendFixedIpi (
- IN UINT32 ApicId,
- IN UINT8 Vector
+ IN UINT32 ApicId,
+ IN UINT8 Vector
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
+ IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
- IcrLow.Bits.Level = 1;
- IcrLow.Bits.Vector = Vector;
+ IcrLow.Bits.Level = 1;
+ IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, ApicId);
}
@@ -401,16 +402,16 @@ SendFixedIpi ( VOID
EFIAPI
SendFixedIpiAllExcludingSelf (
- IN UINT8 Vector
+ IN UINT8 Vector
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
- IcrLow.Bits.Level = 1;
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
+ IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
- IcrLow.Bits.Vector = Vector;
+ IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, 0);
}
@@ -424,14 +425,14 @@ SendFixedIpiAllExcludingSelf ( VOID
EFIAPI
SendSmiIpi (
- IN UINT32 ApicId
+ IN UINT32 ApicId
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
+ IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
- IcrLow.Bits.Level = 1;
+ IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
}
@@ -446,11 +447,11 @@ SendSmiIpiAllExcludingSelf ( VOID
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
- IcrLow.Bits.Level = 1;
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
+ IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
}
@@ -465,14 +466,14 @@ SendSmiIpiAllExcludingSelf ( VOID
EFIAPI
SendInitIpi (
- IN UINT32 ApicId
+ IN UINT32 ApicId
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
+ IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
- IcrLow.Bits.Level = 1;
+ IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
}
@@ -487,11 +488,11 @@ SendInitIpiAllExcludingSelf ( VOID
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
- IcrLow.Bits.Level = 1;
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
+ IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
}
@@ -511,21 +512,21 @@ SendInitIpiAllExcludingSelf ( VOID
EFIAPI
SendInitSipiSipi (
- IN UINT32 ApicId,
- IN UINT32 StartupRoutine
+ IN UINT32 ApicId,
+ IN UINT32 StartupRoutine
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpi (ApicId);
- MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
- IcrLow.Uint32 = 0;
- IcrLow.Bits.Vector = (StartupRoutine >> 12);
+ MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
- IcrLow.Bits.Level = 1;
+ IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
if (!StandardSignatureIsAuthenticAMD ()) {
MicroSecondDelay (200);
@@ -547,20 +548,20 @@ SendInitSipiSipi ( VOID
EFIAPI
SendInitSipiSipiAllExcludingSelf (
- IN UINT32 StartupRoutine
+ IN UINT32 StartupRoutine
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpiAllExcludingSelf ();
- MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
- IcrLow.Uint32 = 0;
- IcrLow.Bits.Vector = (StartupRoutine >> 12);
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
- IcrLow.Bits.Level = 1;
+ MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.Vector = (StartupRoutine >> 12);
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
+ IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
if (!StandardSignatureIsAuthenticAMD ()) {
@@ -616,13 +617,13 @@ ProgramVirtualWireMode ( VOID
)
{
- LOCAL_APIC_SVR Svr;
- LOCAL_APIC_LVT_LINT Lint;
+ LOCAL_APIC_SVR Svr;
+ LOCAL_APIC_LVT_LINT Lint;
//
// Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
//
- Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
+ Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
Svr.Bits.SpuriousVector = 0xf;
Svr.Bits.SoftwareEnable = 1;
WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
@@ -630,21 +631,21 @@ ProgramVirtualWireMode ( //
// Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
//
- Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
- Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
+ Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
+ Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
Lint.Bits.InputPinPolarity = 0;
- Lint.Bits.TriggerMode = 0;
- Lint.Bits.Mask = 0;
+ Lint.Bits.TriggerMode = 0;
+ Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
//
// Program the LINT0 vector entry as NMI. Not masked, edge, active high.
//
- Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
- Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
+ Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
+ Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
Lint.Bits.InputPinPolarity = 0;
- Lint.Bits.TriggerMode = 0;
- Lint.Bits.Mask = 0;
+ Lint.Bits.TriggerMode = 0;
+ Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
}
@@ -659,13 +660,13 @@ DisableLvtInterrupts ( VOID
)
{
- LOCAL_APIC_LVT_LINT LvtLint;
+ LOCAL_APIC_LVT_LINT LvtLint;
- LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
+ LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
- LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
+ LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
}
@@ -712,15 +713,15 @@ GetApicTimerCurrentCount ( VOID
EFIAPI
InitializeApicTimer (
- IN UINTN DivideValue,
- IN UINT32 InitCount,
- IN BOOLEAN PeriodicMode,
- IN UINT8 Vector
+ IN UINTN DivideValue,
+ IN UINT32 InitCount,
+ IN BOOLEAN PeriodicMode,
+ IN UINT8 Vector
)
{
- LOCAL_APIC_DCR Dcr;
- LOCAL_APIC_LVT_TIMER LvtTimer;
- UINT32 Divisor;
+ LOCAL_APIC_DCR Dcr;
+ LOCAL_APIC_LVT_TIMER LvtTimer;
+ UINT32 Divisor;
//
// Ensure local APIC is in software-enabled state.
@@ -734,10 +735,10 @@ InitializeApicTimer ( if (DivideValue != 0) {
ASSERT (DivideValue <= 128);
- ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
+ ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));
Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
- Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
+ Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Dcr.Bits.DivideValue1 = (Divisor & 0x3);
Dcr.Bits.DivideValue2 = (Divisor >> 2);
WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
@@ -752,7 +753,8 @@ InitializeApicTimer ( } else {
LvtTimer.Bits.TimerMode = 0;
}
- LvtTimer.Bits.Mask = 0;
+
+ LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Vector = Vector;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
@@ -774,25 +776,25 @@ GetApicTimerState ( OUT UINT8 *Vector OPTIONAL
)
{
- UINT32 Divisor;
- LOCAL_APIC_DCR Dcr;
- LOCAL_APIC_LVT_TIMER LvtTimer;
+ UINT32 Divisor;
+ LOCAL_APIC_DCR Dcr;
+ LOCAL_APIC_LVT_TIMER LvtTimer;
//
// Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
// Vector Register.
// This bit will be 1, if local APIC is software enabled.
//
- ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
+ ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
if (DivideValue != NULL) {
- Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
- Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
- Divisor = (Divisor + 1) & 0x7;
+ Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
+ Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
+ Divisor = (Divisor + 1) & 0x7;
*DivideValue = ((UINTN)1) << Divisor;
}
- if (PeriodicMode != NULL || Vector != NULL) {
+ if ((PeriodicMode != NULL) || (Vector != NULL)) {
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
if (PeriodicMode != NULL) {
if (LvtTimer.Bits.TimerMode == 1) {
@@ -801,8 +803,9 @@ GetApicTimerState ( *PeriodicMode = FALSE;
}
}
+
if (Vector != NULL) {
- *Vector = (UINT8) LvtTimer.Bits.Vector;
+ *Vector = (UINT8)LvtTimer.Bits.Vector;
}
}
}
@@ -816,9 +819,9 @@ EnableApicTimerInterrupt ( VOID
)
{
- LOCAL_APIC_LVT_TIMER LvtTimer;
+ LOCAL_APIC_LVT_TIMER LvtTimer;
- LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
+ LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
@@ -832,9 +835,9 @@ DisableApicTimerInterrupt ( VOID
)
{
- LOCAL_APIC_LVT_TIMER LvtTimer;
+ LOCAL_APIC_LVT_TIMER LvtTimer;
- LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
+ LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
@@ -851,7 +854,7 @@ GetApicTimerInterruptState ( VOID
)
{
- LOCAL_APIC_LVT_TIMER LvtTimer;
+ LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
@@ -944,6 +947,7 @@ GetApicMsiValue ( MsiData.Bits.Level = 1;
}
}
+
return MsiData.Uint64;
}
@@ -995,12 +999,15 @@ GetProcessorLocationByApicId ( if (Thread != NULL) {
*Thread = 0;
}
+
if (Core != NULL) {
*Core = 0;
}
+
if (Package != NULL) {
*Package = 0;
}
+
return;
}
@@ -1008,7 +1015,7 @@ GetProcessorLocationByApicId ( // Assume three-level mapping of APIC ID: Package|Core|Thread.
//
ThreadBits = 0;
- CoreBits = 0;
+ CoreBits = 0;
//
// Get max index of CPUID
@@ -1022,7 +1029,7 @@ GetProcessorLocationByApicId ( //
TopologyLeafSupported = FALSE;
if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
- AsmCpuidEx(
+ AsmCpuidEx (
CPUID_EXTENDED_TOPOLOGY,
0,
&ExtendedTopologyEax.Uint32,
@@ -1065,6 +1072,7 @@ GetProcessorLocationByApicId ( CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
break;
}
+
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
}
@@ -1085,7 +1093,7 @@ GetProcessorLocationByApicId ( //
// Check for topology extensions on AMD processor
//
- if (StandardSignatureIsAuthenticAMD()) {
+ if (StandardSignatureIsAuthenticAMD ()) {
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
@@ -1102,8 +1110,7 @@ GetProcessorLocationByApicId ( MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
}
}
- }
- else {
+ } else {
//
// Extract core count based on CACHE information
//
@@ -1115,16 +1122,18 @@ GetProcessorLocationByApicId ( }
}
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+ ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);
}
if (Thread != NULL) {
*Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
+
if (Core != NULL) {
*Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
+
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
}
@@ -1158,13 +1167,13 @@ GetProcessorLocation2ByApicId ( OUT UINT32 *Thread OPTIONAL
)
{
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxStandardCpuIdIndex;
- UINT32 Index;
- UINTN LevelType;
- UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
- UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 Index;
+ UINTN LevelType;
+ UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
+ UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {
Bits[LevelType] = 0;
@@ -1178,12 +1187,15 @@ GetProcessorLocation2ByApicId ( if (Die != NULL) {
*Die = 0;
}
+
if (Tile != NULL) {
*Tile = 0;
}
+
if (Module != NULL) {
*Module = 0;
}
+
GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
return;
}
@@ -1193,7 +1205,7 @@ GetProcessorLocation2ByApicId ( // is the preferred mechanism for enumerating topology.
//
for (Index = 0; ; Index++) {
- AsmCpuidEx(
+ AsmCpuidEx (
CPUID_V2_EXTENDED_TOPOLOGY,
Index,
&ExtendedTopologyEax.Uint32,
@@ -1211,6 +1223,7 @@ GetProcessorLocation2ByApicId ( if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break;
}
+
ASSERT (LevelType < ARRAY_SIZE (Bits));
Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
}
@@ -1226,18 +1239,19 @@ GetProcessorLocation2ByApicId ( }
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;
- Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die;
- Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile;
- Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module;
- Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core;
- Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread;
+ Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;
+ Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;
+ Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;
+ Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;
+ Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;
Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;
for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
- ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
- ; LevelType ++
- ) {
+ ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
+ ; LevelType++
+ )
+ {
if (Location[LevelType] != NULL) {
//
// Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index cdcbca0461..aaa42ff845 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -45,13 +45,14 @@ LocalApicBaseAddressMsrSupported ( AsmCpuid (1, &RegEax, NULL, NULL, NULL);
FamilyId = BitFieldRead32 (RegEax, 8, 11);
- if (FamilyId == 0x04 || FamilyId == 0x05) {
+ if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
//
// CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR
//
return FALSE;
}
+
return TRUE;
}
@@ -79,8 +80,8 @@ GetLocalApicBaseAddress ( ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
- return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
- (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
+ return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
+ (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
}
/**
@@ -94,7 +95,7 @@ GetLocalApicBaseAddress ( VOID
EFIAPI
SetLocalApicBaseAddress (
- IN UINTN BaseAddress
+ IN UINTN BaseAddress
)
{
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
@@ -110,8 +111,8 @@ SetLocalApicBaseAddress ( ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
- ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
- ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
+ ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);
+ ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
}
@@ -135,12 +136,12 @@ ReadLocalApicReg ( IN UINTN MmioOffset
)
{
- UINT32 MsrIndex;
+ UINT32 MsrIndex;
ASSERT ((MmioOffset & 0xf) == 0);
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
- return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
+ return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);
} else {
//
// DFR is not supported in x2APIC mode.
@@ -174,16 +175,16 @@ ReadLocalApicReg ( VOID
EFIAPI
WriteLocalApicReg (
- IN UINTN MmioOffset,
- IN UINT32 Value
+ IN UINTN MmioOffset,
+ IN UINT32 Value
)
{
- UINT32 MsrIndex;
+ UINT32 MsrIndex;
ASSERT ((MmioOffset & 0xf) == 0);
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
- MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
+ MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);
} else {
//
// DFR is not supported in x2APIC mode.
@@ -216,15 +217,15 @@ WriteLocalApicReg ( **/
VOID
SendIpi (
- IN UINT32 IcrLow,
- IN UINT32 ApicId
+ IN UINT32 IcrLow,
+ IN UINT32 ApicId
)
{
- UINT64 MsrValue;
- LOCAL_APIC_ICR_LOW IcrLowReg;
- UINTN LocalApciBaseAddress;
- UINT32 IcrHigh;
- BOOLEAN InterruptState;
+ UINT64 MsrValue;
+ LOCAL_APIC_ICR_LOW IcrLowReg;
+ UINTN LocalApciBaseAddress;
+ UINT32 IcrHigh;
+ BOOLEAN InterruptState;
//
// Legacy APIC or X2APIC?
@@ -237,7 +238,7 @@ SendIpi ( //
// Get base address of this LAPIC
//
- LocalApciBaseAddress = GetLocalApicBaseAddress();
+ LocalApciBaseAddress = GetLocalApicBaseAddress ();
//
// Save existing contents of ICR high 32 bits
@@ -271,13 +272,12 @@ SendIpi ( MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);
SetInterruptState (InterruptState);
-
} else {
//
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
// interrupt in x2APIC mode.
//
- MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;
+ MsrValue = LShiftU64 ((UINT64)ApicId, 32) | IcrLow;
AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
}
}
@@ -354,7 +354,7 @@ SetApicMode ( case LOCAL_APIC_MODE_XAPIC:
break;
case LOCAL_APIC_MODE_X2APIC:
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.EXTD = 1;
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
break;
@@ -368,9 +368,9 @@ SetApicMode ( // Transition from x2APIC mode to xAPIC mode is a two-step process:
// x2APIC -> Local APIC disabled -> xAPIC
//
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.EXTD = 0;
- ApicBaseMsr.Bits.EN = 0;
+ ApicBaseMsr.Bits.EN = 0;
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
ApicBaseMsr.Bits.EN = 1;
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
@@ -398,9 +398,9 @@ GetInitialApicId ( VOID
)
{
- UINT32 ApicId;
- UINT32 MaxCpuIdIndex;
- UINT32 RegEbx;
+ UINT32 ApicId;
+ UINT32 MaxCpuIdIndex;
+ UINT32 RegEbx;
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
//
@@ -419,6 +419,7 @@ GetInitialApicId ( return ApicId;
}
}
+
AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
return RegEbx >> 24;
} else {
@@ -437,8 +438,8 @@ GetApicId ( VOID
)
{
- UINT32 ApicId;
- UINT32 InitApicId;
+ UINT32 ApicId;
+ UINT32 InitApicId;
ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
@@ -473,16 +474,16 @@ GetApicVersion ( VOID
EFIAPI
SendFixedIpi (
- IN UINT32 ApicId,
- IN UINT8 Vector
+ IN UINT32 ApicId,
+ IN UINT8 Vector
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
+ IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
- IcrLow.Bits.Level = 1;
- IcrLow.Bits.Vector = Vector;
+ IcrLow.Bits.Level = 1;
+ IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, ApicId);
}
@@ -496,16 +497,16 @@ SendFixedIpi ( VOID
EFIAPI
SendFixedIpiAllExcludingSelf (
- IN UINT8 Vector
+ IN UINT8 Vector
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
- IcrLow.Bits.Level = 1;
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
+ IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
- IcrLow.Bits.Vector = Vector;
+ IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, 0);
}
@@ -519,14 +520,14 @@ SendFixedIpiAllExcludingSelf ( VOID
EFIAPI
SendSmiIpi (
- IN UINT32 ApicId
+ IN UINT32 ApicId
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
+ IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
- IcrLow.Bits.Level = 1;
+ IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
}
@@ -541,11 +542,11 @@ SendSmiIpiAllExcludingSelf ( VOID
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
- IcrLow.Bits.Level = 1;
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
+ IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
}
@@ -560,14 +561,14 @@ SendSmiIpiAllExcludingSelf ( VOID
EFIAPI
SendInitIpi (
- IN UINT32 ApicId
+ IN UINT32 ApicId
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
+ IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
- IcrLow.Bits.Level = 1;
+ IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
}
@@ -582,11 +583,11 @@ SendInitIpiAllExcludingSelf ( VOID
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
- IcrLow.Uint32 = 0;
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
- IcrLow.Bits.Level = 1;
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
+ IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
}
@@ -606,21 +607,21 @@ SendInitIpiAllExcludingSelf ( VOID
EFIAPI
SendInitSipiSipi (
- IN UINT32 ApicId,
- IN UINT32 StartupRoutine
+ IN UINT32 ApicId,
+ IN UINT32 StartupRoutine
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpi (ApicId);
- MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
- IcrLow.Uint32 = 0;
- IcrLow.Bits.Vector = (StartupRoutine >> 12);
+ MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
- IcrLow.Bits.Level = 1;
+ IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
if (!StandardSignatureIsAuthenticAMD ()) {
MicroSecondDelay (200);
@@ -642,20 +643,20 @@ SendInitSipiSipi ( VOID
EFIAPI
SendInitSipiSipiAllExcludingSelf (
- IN UINT32 StartupRoutine
+ IN UINT32 StartupRoutine
)
{
- LOCAL_APIC_ICR_LOW IcrLow;
+ LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpiAllExcludingSelf ();
- MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
- IcrLow.Uint32 = 0;
- IcrLow.Bits.Vector = (StartupRoutine >> 12);
- IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
- IcrLow.Bits.Level = 1;
+ MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
+ IcrLow.Uint32 = 0;
+ IcrLow.Bits.Vector = (StartupRoutine >> 12);
+ IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
+ IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
if (!StandardSignatureIsAuthenticAMD ()) {
@@ -711,13 +712,13 @@ ProgramVirtualWireMode ( VOID
)
{
- LOCAL_APIC_SVR Svr;
- LOCAL_APIC_LVT_LINT Lint;
+ LOCAL_APIC_SVR Svr;
+ LOCAL_APIC_LVT_LINT Lint;
//
// Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
//
- Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
+ Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
Svr.Bits.SpuriousVector = 0xf;
Svr.Bits.SoftwareEnable = 1;
WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
@@ -725,21 +726,21 @@ ProgramVirtualWireMode ( //
// Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
//
- Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
- Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
+ Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
+ Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
Lint.Bits.InputPinPolarity = 0;
- Lint.Bits.TriggerMode = 0;
- Lint.Bits.Mask = 0;
+ Lint.Bits.TriggerMode = 0;
+ Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
//
// Program the LINT0 vector entry as NMI. Not masked, edge, active high.
//
- Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
- Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
+ Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
+ Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
Lint.Bits.InputPinPolarity = 0;
- Lint.Bits.TriggerMode = 0;
- Lint.Bits.Mask = 0;
+ Lint.Bits.TriggerMode = 0;
+ Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
}
@@ -754,13 +755,13 @@ DisableLvtInterrupts ( VOID
)
{
- LOCAL_APIC_LVT_LINT LvtLint;
+ LOCAL_APIC_LVT_LINT LvtLint;
- LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
+ LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
- LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
+ LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
}
@@ -807,15 +808,15 @@ GetApicTimerCurrentCount ( VOID
EFIAPI
InitializeApicTimer (
- IN UINTN DivideValue,
- IN UINT32 InitCount,
- IN BOOLEAN PeriodicMode,
- IN UINT8 Vector
+ IN UINTN DivideValue,
+ IN UINT32 InitCount,
+ IN BOOLEAN PeriodicMode,
+ IN UINT8 Vector
)
{
- LOCAL_APIC_DCR Dcr;
- LOCAL_APIC_LVT_TIMER LvtTimer;
- UINT32 Divisor;
+ LOCAL_APIC_DCR Dcr;
+ LOCAL_APIC_LVT_TIMER LvtTimer;
+ UINT32 Divisor;
//
// Ensure local APIC is in software-enabled state.
@@ -829,10 +830,10 @@ InitializeApicTimer ( if (DivideValue != 0) {
ASSERT (DivideValue <= 128);
- ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
+ ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));
Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
- Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
+ Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Dcr.Bits.DivideValue1 = (Divisor & 0x3);
Dcr.Bits.DivideValue2 = (Divisor >> 2);
WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
@@ -847,7 +848,8 @@ InitializeApicTimer ( } else {
LvtTimer.Bits.TimerMode = 0;
}
- LvtTimer.Bits.Mask = 0;
+
+ LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Vector = Vector;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
@@ -869,25 +871,25 @@ GetApicTimerState ( OUT UINT8 *Vector OPTIONAL
)
{
- UINT32 Divisor;
- LOCAL_APIC_DCR Dcr;
- LOCAL_APIC_LVT_TIMER LvtTimer;
+ UINT32 Divisor;
+ LOCAL_APIC_DCR Dcr;
+ LOCAL_APIC_LVT_TIMER LvtTimer;
//
// Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
// Vector Register.
// This bit will be 1, if local APIC is software enabled.
//
- ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
+ ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
if (DivideValue != NULL) {
- Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
- Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
- Divisor = (Divisor + 1) & 0x7;
+ Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
+ Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
+ Divisor = (Divisor + 1) & 0x7;
*DivideValue = ((UINTN)1) << Divisor;
}
- if (PeriodicMode != NULL || Vector != NULL) {
+ if ((PeriodicMode != NULL) || (Vector != NULL)) {
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
if (PeriodicMode != NULL) {
if (LvtTimer.Bits.TimerMode == 1) {
@@ -896,8 +898,9 @@ GetApicTimerState ( *PeriodicMode = FALSE;
}
}
+
if (Vector != NULL) {
- *Vector = (UINT8) LvtTimer.Bits.Vector;
+ *Vector = (UINT8)LvtTimer.Bits.Vector;
}
}
}
@@ -911,9 +914,9 @@ EnableApicTimerInterrupt ( VOID
)
{
- LOCAL_APIC_LVT_TIMER LvtTimer;
+ LOCAL_APIC_LVT_TIMER LvtTimer;
- LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
+ LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
@@ -927,9 +930,9 @@ DisableApicTimerInterrupt ( VOID
)
{
- LOCAL_APIC_LVT_TIMER LvtTimer;
+ LOCAL_APIC_LVT_TIMER LvtTimer;
- LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
+ LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
@@ -946,7 +949,7 @@ GetApicTimerInterruptState ( VOID
)
{
- LOCAL_APIC_LVT_TIMER LvtTimer;
+ LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
@@ -1039,6 +1042,7 @@ GetApicMsiValue ( MsiData.Bits.Level = 1;
}
}
+
return MsiData.Uint64;
}
@@ -1090,12 +1094,15 @@ GetProcessorLocationByApicId ( if (Thread != NULL) {
*Thread = 0;
}
+
if (Core != NULL) {
*Core = 0;
}
+
if (Package != NULL) {
*Package = 0;
}
+
return;
}
@@ -1103,7 +1110,7 @@ GetProcessorLocationByApicId ( // Assume three-level mapping of APIC ID: Package|Core|Thread.
//
ThreadBits = 0;
- CoreBits = 0;
+ CoreBits = 0;
//
// Get max index of CPUID
@@ -1117,7 +1124,7 @@ GetProcessorLocationByApicId ( //
TopologyLeafSupported = FALSE;
if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
- AsmCpuidEx(
+ AsmCpuidEx (
CPUID_EXTENDED_TOPOLOGY,
0,
&ExtendedTopologyEax.Uint32,
@@ -1160,6 +1167,7 @@ GetProcessorLocationByApicId ( CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
break;
}
+
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
}
@@ -1180,7 +1188,7 @@ GetProcessorLocationByApicId ( //
// Check for topology extensions on AMD processor
//
- if (StandardSignatureIsAuthenticAMD()) {
+ if (StandardSignatureIsAuthenticAMD ()) {
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
@@ -1197,8 +1205,7 @@ GetProcessorLocationByApicId ( MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
}
}
- }
- else {
+ } else {
//
// Extract core count based on CACHE information
//
@@ -1210,16 +1217,18 @@ GetProcessorLocationByApicId ( }
}
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+ ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);
}
if (Thread != NULL) {
*Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
+
if (Core != NULL) {
*Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
+
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
}
@@ -1253,13 +1262,13 @@ GetProcessorLocation2ByApicId ( OUT UINT32 *Thread OPTIONAL
)
{
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxStandardCpuIdIndex;
- UINT32 Index;
- UINTN LevelType;
- UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
- UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 Index;
+ UINTN LevelType;
+ UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
+ UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {
Bits[LevelType] = 0;
@@ -1273,12 +1282,15 @@ GetProcessorLocation2ByApicId ( if (Die != NULL) {
*Die = 0;
}
+
if (Tile != NULL) {
*Tile = 0;
}
+
if (Module != NULL) {
*Module = 0;
}
+
GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
return;
}
@@ -1288,7 +1300,7 @@ GetProcessorLocation2ByApicId ( // is the preferred mechanism for enumerating topology.
//
for (Index = 0; ; Index++) {
- AsmCpuidEx(
+ AsmCpuidEx (
CPUID_V2_EXTENDED_TOPOLOGY,
Index,
&ExtendedTopologyEax.Uint32,
@@ -1306,6 +1318,7 @@ GetProcessorLocation2ByApicId ( if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break;
}
+
ASSERT (LevelType < ARRAY_SIZE (Bits));
Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
}
@@ -1321,18 +1334,19 @@ GetProcessorLocation2ByApicId ( }
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;
- Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die;
- Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile;
- Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module;
- Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core;
- Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread;
+ Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;
+ Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;
+ Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;
+ Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;
+ Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;
Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;
for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
- ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
- ; LevelType ++
- ) {
+ ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
+ ; LevelType++
+ )
+ {
if (Location[LevelType] != NULL) {
//
// Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c index f4fcee39e9..c7973735e1 100644 --- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c @@ -17,21 +17,31 @@ **/
VOID
CpuCacheInfoPrintCpuCacheInfoTable (
- IN CPU_CACHE_INFO *CpuCacheInfo,
- IN UINTN CpuCacheInfoCount
+ IN CPU_CACHE_INFO *CpuCacheInfo,
+ IN UINTN CpuCacheInfoCount
)
{
- UINTN Index;
+ UINTN Index;
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType CacheWays (FA|DM) CacheSizeinKB CacheCount |\n"));
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
for (Index = 0; Index < CpuCacheInfoCount; Index++) {
- DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n",
- Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel,
- CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].FullyAssociativeCache,
- CpuCacheInfo[Index].DirectMappedCache, CpuCacheInfo[Index].CacheSizeinKB, CpuCacheInfo[Index].CacheCount));
+ DEBUG ((
+ DEBUG_INFO,
+ "| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n",
+ Index,
+ CpuCacheInfo[Index].Package,
+ CpuCacheInfo[Index].CoreType,
+ CpuCacheInfo[Index].CacheLevel,
+ CpuCacheInfo[Index].CacheType,
+ CpuCacheInfo[Index].CacheWays,
+ CpuCacheInfo[Index].FullyAssociativeCache,
+ CpuCacheInfo[Index].DirectMappedCache,
+ CpuCacheInfo[Index].CacheSizeinKB,
+ CpuCacheInfo[Index].CacheCount
+ ));
}
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
@@ -50,24 +60,24 @@ CpuCacheInfoPrintCpuCacheInfoTable ( INTN
EFIAPI
CpuCacheInfoCompare (
- IN CONST VOID *Buffer1,
- IN CONST VOID *Buffer2
+ IN CONST VOID *Buffer1,
+ IN CONST VOID *Buffer2
)
{
- CPU_CACHE_INFO_COMPARATOR Comparator1, Comparator2;
+ CPU_CACHE_INFO_COMPARATOR Comparator1, Comparator2;
ZeroMem (&Comparator1, sizeof (Comparator1));
ZeroMem (&Comparator2, sizeof (Comparator2));
- Comparator1.Bits.Package = ((CPU_CACHE_INFO*)Buffer1)->Package;
- Comparator1.Bits.CoreType = ((CPU_CACHE_INFO*)Buffer1)->CoreType;
- Comparator1.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer1)->CacheLevel;
- Comparator1.Bits.CacheType = ((CPU_CACHE_INFO*)Buffer1)->CacheType;
+ Comparator1.Bits.Package = ((CPU_CACHE_INFO *)Buffer1)->Package;
+ Comparator1.Bits.CoreType = ((CPU_CACHE_INFO *)Buffer1)->CoreType;
+ Comparator1.Bits.CacheLevel = ((CPU_CACHE_INFO *)Buffer1)->CacheLevel;
+ Comparator1.Bits.CacheType = ((CPU_CACHE_INFO *)Buffer1)->CacheType;
- Comparator2.Bits.Package = ((CPU_CACHE_INFO*)Buffer2)->Package;
- Comparator2.Bits.CoreType = ((CPU_CACHE_INFO*)Buffer2)->CoreType;
- Comparator2.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer2)->CacheLevel;
- Comparator2.Bits.CacheType = ((CPU_CACHE_INFO*)Buffer2)->CacheType;
+ Comparator2.Bits.Package = ((CPU_CACHE_INFO *)Buffer2)->Package;
+ Comparator2.Bits.CoreType = ((CPU_CACHE_INFO *)Buffer2)->CoreType;
+ Comparator2.Bits.CacheLevel = ((CPU_CACHE_INFO *)Buffer2)->CacheLevel;
+ Comparator2.Bits.CacheType = ((CPU_CACHE_INFO *)Buffer2)->CacheType;
if (Comparator1.Uint64 == Comparator2.Uint64) {
return 0;
@@ -89,15 +99,15 @@ CpuCacheInfoCompare ( **/
UINT32
CpuCacheInfoGetNumberOfPackages (
- IN CPUID_PROCESSOR_INFO *ProcessorInfo,
- IN UINTN NumberOfProcessors,
- IN OUT UINT32 *Package
+ IN CPUID_PROCESSOR_INFO *ProcessorInfo,
+ IN UINTN NumberOfProcessors,
+ IN OUT UINT32 *Package
)
{
- UINTN ProcessorIndex;
- UINT32 PackageIndex;
- UINT32 PackageCount;
- UINT32 CurrentPackage;
+ UINTN ProcessorIndex;
+ UINT32 PackageIndex;
+ UINT32 PackageCount;
+ UINT32 CurrentPackage;
PackageCount = 0;
@@ -135,21 +145,21 @@ CpuCacheInfoGetNumberOfPackages ( @retval Return the number of CoreType of requested package.
**/
UINTN
-CpuCacheInfoGetNumberOfCoreTypePerPackage(
- IN CPUID_PROCESSOR_INFO *ProcessorInfo,
- IN UINTN NumberOfProcessors,
- IN UINTN Package
+CpuCacheInfoGetNumberOfCoreTypePerPackage (
+ IN CPUID_PROCESSOR_INFO *ProcessorInfo,
+ IN UINTN NumberOfProcessors,
+ IN UINTN Package
)
{
- UINTN ProcessorIndex;
+ UINTN ProcessorIndex;
//
// Core Type value comes from CPUID.1Ah.EAX[31:24].
// So max number of core types should be MAX_UINT8.
//
- UINT8 CoreType[MAX_UINT8];
- UINTN CoreTypeIndex;
- UINTN CoreTypeCount;
- UINT8 CurrentCoreType;
+ UINT8 CoreType[MAX_UINT8];
+ UINTN CoreTypeIndex;
+ UINTN CoreTypeCount;
+ UINT8 CurrentCoreType;
//
// CoreType array is empty.
@@ -192,23 +202,23 @@ CpuCacheInfoGetNumberOfCoreTypePerPackage( VOID
EFIAPI
CpuCacheInfoCollectCoreAndCacheData (
- IN OUT VOID *Buffer
+ IN OUT VOID *Buffer
)
{
- UINTN ProcessorIndex;
- UINT32 CpuidMaxInput;
- UINT8 CacheParamLeafIndex;
- CPUID_CACHE_PARAMS_EAX CacheParamEax;
- CPUID_CACHE_PARAMS_EBX CacheParamEbx;
- UINT32 CacheParamEcx;
- CPUID_CACHE_PARAMS_EDX CacheParamEdx;
- CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX NativeModelIdAndCoreTypeEax;
- COLLECT_CPUID_CACHE_DATA_CONTEXT *Context;
- CPUID_CACHE_DATA *CacheData;
-
- Context = (COLLECT_CPUID_CACHE_DATA_CONTEXT *)Buffer;
+ UINTN ProcessorIndex;
+ UINT32 CpuidMaxInput;
+ UINT8 CacheParamLeafIndex;
+ CPUID_CACHE_PARAMS_EAX CacheParamEax;
+ CPUID_CACHE_PARAMS_EBX CacheParamEbx;
+ UINT32 CacheParamEcx;
+ CPUID_CACHE_PARAMS_EDX CacheParamEdx;
+ CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX NativeModelIdAndCoreTypeEax;
+ COLLECT_CPUID_CACHE_DATA_CONTEXT *Context;
+ CPUID_CACHE_DATA *CacheData;
+
+ Context = (COLLECT_CPUID_CACHE_DATA_CONTEXT *)Buffer;
ProcessorIndex = CpuCacheInfoWhoAmI (Context->MpServices);
- CacheData = &Context->CacheData[MAX_NUM_OF_CACHE_PARAMS_LEAF * ProcessorIndex];
+ CacheData = &Context->CacheData[MAX_NUM_OF_CACHE_PARAMS_LEAF * ProcessorIndex];
AsmCpuid (CPUID_SIGNATURE, &CpuidMaxInput, NULL, NULL, NULL);
@@ -218,7 +228,7 @@ CpuCacheInfoCollectCoreAndCacheData ( Context->ProcessorInfo[ProcessorIndex].CoreType = 0;
if (CpuidMaxInput >= CPUID_HYBRID_INFORMATION) {
AsmCpuidEx (CPUID_HYBRID_INFORMATION, CPUID_HYBRID_INFORMATION_MAIN_LEAF, &NativeModelIdAndCoreTypeEax.Uint32, NULL, NULL, NULL);
- Context->ProcessorInfo[ProcessorIndex].CoreType = (UINT8) NativeModelIdAndCoreTypeEax.Bits.CoreType;
+ Context->ProcessorInfo[ProcessorIndex].CoreType = (UINT8)NativeModelIdAndCoreTypeEax.Bits.CoreType;
}
//
@@ -240,7 +250,7 @@ CpuCacheInfoCollectCoreAndCacheData ( CacheData[CacheParamLeafIndex].DirectMappedCache = (UINT8)(CacheParamEdx.Bits.ComplexCacheIndexing == 0);
CacheData[CacheParamLeafIndex].CacheShareBits = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;
CacheData[CacheParamLeafIndex].CacheSizeinKB = (CacheParamEbx.Bits.Ways + 1) *
- (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB;
+ (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB;
CacheParamLeafIndex++;
}
@@ -264,25 +274,25 @@ CpuCacheInfoCollectCoreAndCacheData ( **/
EFI_STATUS
CpuCacheInfoCollectCpuCacheInfoData (
- IN CPUID_CACHE_DATA *CacheData,
- IN CPUID_PROCESSOR_INFO *ProcessorInfo,
- IN UINTN NumberOfProcessors,
- IN OUT CPU_CACHE_INFO *CacheInfo,
- IN OUT UINTN *CacheInfoCount
+ IN CPUID_CACHE_DATA *CacheData,
+ IN CPUID_PROCESSOR_INFO *ProcessorInfo,
+ IN UINTN NumberOfProcessors,
+ IN OUT CPU_CACHE_INFO *CacheInfo,
+ IN OUT UINTN *CacheInfoCount
)
{
- EFI_STATUS Status;
- UINT32 NumberOfPackage;
- UINT32 Package[MAX_NUM_OF_PACKAGE];
- UINTN PackageIndex;
- UINTN TotalNumberOfCoreType;
- UINTN MaxCacheInfoCount;
- CPU_CACHE_INFO *LocalCacheInfo;
- UINTN CacheInfoIndex;
- UINTN LocalCacheInfoCount;
- UINTN Index;
- UINTN NextIndex;
- CPU_CACHE_INFO SortBuffer;
+ EFI_STATUS Status;
+ UINT32 NumberOfPackage;
+ UINT32 Package[MAX_NUM_OF_PACKAGE];
+ UINTN PackageIndex;
+ UINTN TotalNumberOfCoreType;
+ UINTN MaxCacheInfoCount;
+ CPU_CACHE_INFO *LocalCacheInfo;
+ UINTN CacheInfoIndex;
+ UINTN LocalCacheInfoCount;
+ UINTN Index;
+ UINTN NextIndex;
+ CPU_CACHE_INFO SortBuffer;
//
// Get number of Packages and Package ID.
@@ -299,7 +309,7 @@ CpuCacheInfoCollectCpuCacheInfoData ( }
MaxCacheInfoCount = TotalNumberOfCoreType * MAX_NUM_OF_CACHE_PARAMS_LEAF;
- LocalCacheInfo = AllocatePages (EFI_SIZE_TO_PAGES (MaxCacheInfoCount * sizeof (*LocalCacheInfo)));
+ LocalCacheInfo = AllocatePages (EFI_SIZE_TO_PAGES (MaxCacheInfoCount * sizeof (*LocalCacheInfo)));
ASSERT (LocalCacheInfo != NULL);
if (LocalCacheInfo == NULL) {
return EFI_OUT_OF_RESOURCES;
@@ -320,12 +330,13 @@ CpuCacheInfoCollectCpuCacheInfoData ( continue;
}
- if (CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel &&
- CacheData[Index].CacheType == CacheData[NextIndex].CacheType &&
- ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package &&
- ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType &&
- (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) ==
- (ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits)) {
+ if ((CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel) &&
+ (CacheData[Index].CacheType == CacheData[NextIndex].CacheType) &&
+ (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) &&
+ (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) &&
+ ((ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) ==
+ (ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits)))
+ {
CacheData[NextIndex].CacheSizeinKB = 0; // uses the sharing cache
}
}
@@ -334,10 +345,11 @@ CpuCacheInfoCollectCpuCacheInfoData ( // For the cache that already exists in LocalCacheInfo, increase its CacheCount.
//
for (CacheInfoIndex = 0; CacheInfoIndex < LocalCacheInfoCount; CacheInfoIndex++) {
- if (LocalCacheInfo[CacheInfoIndex].Package == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package &&
- LocalCacheInfo[CacheInfoIndex].CoreType == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType &&
- LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel &&
- LocalCacheInfo[CacheInfoIndex].CacheType == CacheData[Index].CacheType) {
+ if ((LocalCacheInfo[CacheInfoIndex].Package == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) &&
+ (LocalCacheInfo[CacheInfoIndex].CoreType == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) &&
+ (LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel) &&
+ (LocalCacheInfo[CacheInfoIndex].CacheType == CacheData[Index].CacheType))
+ {
LocalCacheInfo[CacheInfoIndex].CacheCount++;
break;
}
@@ -370,11 +382,11 @@ CpuCacheInfoCollectCpuCacheInfoData ( //
// Sort LocalCacheInfo array by CPU package ID, core type, cache level and cache type.
//
- QuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalCacheInfo), CpuCacheInfoCompare, (VOID*) &SortBuffer);
+ QuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalCacheInfo), CpuCacheInfoCompare, (VOID *)&SortBuffer);
CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * LocalCacheInfoCount);
DEBUG_CODE (
CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount);
- );
+ );
Status = EFI_SUCCESS;
}
@@ -405,23 +417,23 @@ CpuCacheInfoCollectCpuCacheInfoData ( EFI_STATUS
EFIAPI
GetCpuCacheInfo (
- IN OUT CPU_CACHE_INFO *CpuCacheInfo,
- IN OUT UINTN *CpuCacheInfoCount
+ IN OUT CPU_CACHE_INFO *CpuCacheInfo,
+ IN OUT UINTN *CpuCacheInfoCount
)
{
- EFI_STATUS Status;
- UINT32 CpuidMaxInput;
- UINT32 NumberOfProcessors;
- UINTN CacheDataCount;
- UINTN ProcessorIndex;
- EFI_PROCESSOR_INFORMATION ProcessorInfo;
+ EFI_STATUS Status;
+ UINT32 CpuidMaxInput;
+ UINT32 NumberOfProcessors;
+ UINTN CacheDataCount;
+ UINTN ProcessorIndex;
+ EFI_PROCESSOR_INFORMATION ProcessorInfo;
COLLECT_CPUID_CACHE_DATA_CONTEXT Context;
if (CpuCacheInfoCount == NULL) {
return EFI_INVALID_PARAMETER;
}
- if (*CpuCacheInfoCount != 0 && CpuCacheInfo == NULL) {
+ if ((*CpuCacheInfoCount != 0) && (CpuCacheInfo == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -445,13 +457,14 @@ GetCpuCacheInfo ( if (Context.ProcessorInfo == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
//
// Initialize COLLECT_CPUID_CACHE_DATA_CONTEXT.CacheData.
// CacheData array consists of CPUID_CACHE_DATA data structure for each Cpuid Cache Parameter Leaf
// per logical processor. The array begin with data of each Cache Parameter Leaf of processor 0, followed
// by data of each Cache Parameter Leaf of processor 1 ...
//
- CacheDataCount = NumberOfProcessors * MAX_NUM_OF_CACHE_PARAMS_LEAF;
+ CacheDataCount = NumberOfProcessors * MAX_NUM_OF_CACHE_PARAMS_LEAF;
Context.CacheData = AllocatePages (EFI_SIZE_TO_PAGES (CacheDataCount * sizeof (*Context.CacheData)));
ASSERT (Context.CacheData != NULL);
if (Context.CacheData == NULL) {
@@ -467,7 +480,7 @@ GetCpuCacheInfo ( for (ProcessorIndex = 0; ProcessorIndex < NumberOfProcessors; ProcessorIndex++) {
CpuCacheInfoGetProcessorInfo (Context.MpServices, ProcessorIndex, &ProcessorInfo);
Context.ProcessorInfo[ProcessorIndex].Package = ProcessorInfo.Location.Package;
- Context.ProcessorInfo[ProcessorIndex].ApicId = (UINT32) ProcessorInfo.ProcessorId;
+ Context.ProcessorInfo[ProcessorIndex].ApicId = (UINT32)ProcessorInfo.ProcessorId;
}
//
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c index d810294e21..ebf2db86ba 100644 --- a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c @@ -23,10 +23,10 @@ **/
EFI_STATUS
CpuCacheInfoGetMpServices (
- OUT MP_SERVICES *MpServices
+ OUT MP_SERVICES *MpServices
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices->Protocol);
ASSERT_EFI_ERROR (Status);
@@ -43,12 +43,12 @@ CpuCacheInfoGetMpServices ( **/
VOID
CpuCacheInfoStartupAllCPUs (
- IN MP_SERVICES MpServices,
- IN EFI_AP_PROCEDURE Procedure,
- IN VOID *ProcedureArgument
+ IN MP_SERVICES MpServices,
+ IN EFI_AP_PROCEDURE Procedure,
+ IN VOID *ProcedureArgument
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = MpServices.Protocol->StartupAllAPs (MpServices.Protocol, Procedure, FALSE, NULL, 0, ProcedureArgument, NULL);
if (Status == EFI_NOT_STARTED) {
@@ -58,6 +58,7 @@ CpuCacheInfoStartupAllCPUs ( //
Status = EFI_SUCCESS;
}
+
ASSERT_EFI_ERROR (Status);
Procedure (ProcedureArgument);
@@ -72,12 +73,12 @@ CpuCacheInfoStartupAllCPUs ( **/
VOID
CpuCacheInfoGetProcessorInfo (
- IN MP_SERVICES MpServices,
- IN UINTN ProcessorNum,
- OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo
+ IN MP_SERVICES MpServices,
+ IN UINTN ProcessorNum,
+ OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = MpServices.Protocol->GetProcessorInfo (MpServices.Protocol, ProcessorNum, ProcessorInfo);
ASSERT_EFI_ERROR (Status);
@@ -92,11 +93,11 @@ CpuCacheInfoGetProcessorInfo ( **/
UINT32
CpuCacheInfoWhoAmI (
- IN MP_SERVICES MpServices
+ IN MP_SERVICES MpServices
)
{
- EFI_STATUS Status;
- UINTN ProcessorNum;
+ EFI_STATUS Status;
+ UINTN ProcessorNum;
Status = MpServices.Protocol->WhoAmI (MpServices.Protocol, &ProcessorNum);
ASSERT_EFI_ERROR (Status);
@@ -113,12 +114,12 @@ CpuCacheInfoWhoAmI ( **/
UINT32
CpuCacheInfoGetNumberOfProcessors (
- IN MP_SERVICES MpServices
+ IN MP_SERVICES MpServices
)
{
- EFI_STATUS Status;
- UINTN NumberOfProcessor;
- UINTN NumberOfEnabledProcessor;
+ EFI_STATUS Status;
+ UINTN NumberOfProcessor;
+ UINTN NumberOfEnabledProcessor;
Status = MpServices.Protocol->GetNumberOfProcessors (MpServices.Protocol, &NumberOfProcessor, &NumberOfEnabledProcessor);
ASSERT_EFI_ERROR (Status);
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h index 829a9f43ce..953b3d66b1 100644 --- a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h @@ -25,24 +25,24 @@ typedef union { // Type of the cache that this package's this type of logical processor corresponds to.
// Value = CPUID.04h:EAX[04:00]
//
- UINT32 CacheType : 5;
+ UINT32 CacheType : 5;
//
// Level of the cache that this package's this type of logical processor corresponds to.
// Value = CPUID.04h:EAX[07:05]
//
- UINT32 CacheLevel : 3;
+ UINT32 CacheLevel : 3;
//
// Core type of logical processor.
// Value = CPUID.1Ah:EAX[31:24]
//
- UINT32 CoreType : 8;
- UINT32 Reserved : 16;
+ UINT32 CoreType : 8;
+ UINT32 Reserved : 16;
//
// Package number.
//
- UINT32 Package;
+ UINT32 Package;
} Bits;
- UINT64 Uint64;
+ UINT64 Uint64;
} CPU_CACHE_INFO_COMPARATOR;
typedef struct {
@@ -50,17 +50,17 @@ typedef struct { // Package ID, the information comes from
// EFI_CPU_PHYSICAL_LOCATION.Package
//
- UINT32 Package;
+ UINT32 Package;
//
// APIC ID, the information comes from
// EFI_PROCESSOR_INFORMATION.ProcessorId
//
- UINT32 ApicId;
+ UINT32 ApicId;
//
// Core type of logical processor.
// Value = CPUID.1Ah:EAX[31:24]
//
- UINT8 CoreType;
+ UINT8 CoreType;
} CPUID_PROCESSOR_INFO;
typedef struct {
@@ -68,39 +68,39 @@ typedef struct { // Level of the cache.
// Value = CPUID.04h:EAX[07:05]
//
- UINT8 CacheLevel : 3;
+ UINT8 CacheLevel : 3;
//
// Type of the cache.
// Value = CPUID.04h:EAX[04:00]
//
- UINT8 CacheType : 5;
+ UINT8 CacheType : 5;
//
// Ways of associativity.
// Value = CPUID.04h:EBX[31:22]
//
- UINT16 CacheWays : 10;
+ UINT16 CacheWays : 10;
//
// Fully associative cache.
// Value = CPUID.04h:EAX[09]
//
- UINT16 FullyAssociativeCache : 1;
+ UINT16 FullyAssociativeCache : 1;
//
// Direct mapped cache.
// Value = CPUID.04h:EDX[02]
//
- UINT16 DirectMappedCache : 1;
- UINT16 Reserved : 4;
+ UINT16 DirectMappedCache : 1;
+ UINT16 Reserved : 4;
//
// Cache share bits.
// Value = CPUID.04h:EAX[25:14]
//
- UINT16 CacheShareBits;
+ UINT16 CacheShareBits;
//
// Size of single cache.
// Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) *
// (CPUID.04h:EBX[11:00] + 1) * (CPUID.04h:ECX[31:00] + 1)
//
- UINT32 CacheSizeinKB;
+ UINT32 CacheSizeinKB;
} CPUID_CACHE_DATA;
typedef union {
@@ -109,24 +109,23 @@ typedef union { } MP_SERVICES;
typedef struct {
- MP_SERVICES MpServices;
- CPUID_PROCESSOR_INFO *ProcessorInfo;
- CPUID_CACHE_DATA *CacheData;
+ MP_SERVICES MpServices;
+ CPUID_PROCESSOR_INFO *ProcessorInfo;
+ CPUID_CACHE_DATA *CacheData;
} COLLECT_CPUID_CACHE_DATA_CONTEXT;
-
/*
Defines the maximum count of Deterministic Cache Parameters Leaf of all APs and BSP.
To save boot time, skip starting up all APs to calculate each AP's count of Deterministic
Cache Parameters Leaf, so use a definition instead.
Anyway, definition value will be checked in CpuCacheInfoCollectCoreAndCacheData function.
*/
-#define MAX_NUM_OF_CACHE_PARAMS_LEAF 6
+#define MAX_NUM_OF_CACHE_PARAMS_LEAF 6
/*
Defines the maximum count of packages.
*/
-#define MAX_NUM_OF_PACKAGE 100
+#define MAX_NUM_OF_PACKAGE 100
/**
Get EDKII_PEI_MP_SERVICES2_PPI or EFI_MP_SERVICES_PROTOCOL pointer.
@@ -139,7 +138,7 @@ typedef struct { **/
EFI_STATUS
CpuCacheInfoGetMpServices (
- OUT MP_SERVICES *MpServices
+ OUT MP_SERVICES *MpServices
);
/**
@@ -151,9 +150,9 @@ CpuCacheInfoGetMpServices ( **/
VOID
CpuCacheInfoStartupAllCPUs (
- IN MP_SERVICES MpServices,
- IN EFI_AP_PROCEDURE Procedure,
- IN VOID *ProcedureArgument
+ IN MP_SERVICES MpServices,
+ IN EFI_AP_PROCEDURE Procedure,
+ IN VOID *ProcedureArgument
);
/**
@@ -165,9 +164,9 @@ CpuCacheInfoStartupAllCPUs ( **/
VOID
CpuCacheInfoGetProcessorInfo (
- IN MP_SERVICES MpServices,
- IN UINTN ProcessorNum,
- OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo
+ IN MP_SERVICES MpServices,
+ IN UINTN ProcessorNum,
+ OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo
);
/**
@@ -179,7 +178,7 @@ CpuCacheInfoGetProcessorInfo ( **/
UINT32
CpuCacheInfoWhoAmI (
- IN MP_SERVICES MpServices
+ IN MP_SERVICES MpServices
);
/**
@@ -191,6 +190,7 @@ CpuCacheInfoWhoAmI ( **/
UINT32
CpuCacheInfoGetNumberOfProcessors (
- IN MP_SERVICES MpServices
+ IN MP_SERVICES MpServices
);
+
#endif
diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c index 06c160421b..ea262d8f02 100644 --- a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c @@ -24,10 +24,10 @@ **/
EFI_STATUS
CpuCacheInfoGetMpServices (
- OUT MP_SERVICES *MpServices
+ OUT MP_SERVICES *MpServices
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = PeiServicesLocatePpi (&gEdkiiPeiMpServices2PpiGuid, 0, NULL, (VOID **)&MpServices->Ppi);
ASSERT_EFI_ERROR (Status);
@@ -44,12 +44,12 @@ CpuCacheInfoGetMpServices ( **/
VOID
CpuCacheInfoStartupAllCPUs (
- IN MP_SERVICES MpServices,
- IN EFI_AP_PROCEDURE Procedure,
- IN VOID *ProcedureArgument
+ IN MP_SERVICES MpServices,
+ IN EFI_AP_PROCEDURE Procedure,
+ IN VOID *ProcedureArgument
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = MpServices.Ppi->StartupAllCPUs (MpServices.Ppi, Procedure, 0, ProcedureArgument);
ASSERT_EFI_ERROR (Status);
@@ -64,12 +64,12 @@ CpuCacheInfoStartupAllCPUs ( **/
VOID
CpuCacheInfoGetProcessorInfo (
- IN MP_SERVICES MpServices,
- IN UINTN ProcessorNum,
- OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo
+ IN MP_SERVICES MpServices,
+ IN UINTN ProcessorNum,
+ OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = MpServices.Ppi->GetProcessorInfo (MpServices.Ppi, ProcessorNum, ProcessorInfo);
ASSERT_EFI_ERROR (Status);
@@ -84,11 +84,11 @@ CpuCacheInfoGetProcessorInfo ( **/
UINT32
CpuCacheInfoWhoAmI (
- IN MP_SERVICES MpServices
+ IN MP_SERVICES MpServices
)
{
- EFI_STATUS Status;
- UINTN ProcessorNum;
+ EFI_STATUS Status;
+ UINTN ProcessorNum;
Status = MpServices.Ppi->WhoAmI (MpServices.Ppi, &ProcessorNum);
ASSERT_EFI_ERROR (Status);
@@ -105,12 +105,12 @@ CpuCacheInfoWhoAmI ( **/
UINT32
CpuCacheInfoGetNumberOfProcessors (
- IN MP_SERVICES MpServices
+ IN MP_SERVICES MpServices
)
{
- EFI_STATUS Status;
- UINTN NumberOfProcessor;
- UINTN NumberOfEnabledProcessor;
+ EFI_STATUS Status;
+ UINTN NumberOfProcessor;
+ UINTN NumberOfEnabledProcessor;
Status = MpServices.Ppi->GetNumberOfProcessors (MpServices.Ppi, &NumberOfProcessor, &NumberOfEnabledProcessor);
ASSERT_EFI_ERROR (Status);
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c index 80a7df2957..beda97e238 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c @@ -23,7 +23,7 @@ AesniGetConfigData ( IN UINTN NumberOfProcessors
)
{
- UINT64 *ConfigData;
+ UINT64 *ConfigData;
ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);
ASSERT (ConfigData != NULL);
@@ -54,14 +54,15 @@ AesniSupport ( IN VOID *ConfigData OPTIONAL
)
{
- MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
+ MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) {
- MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;
+ MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;
ASSERT (MsrFeatureConfig != NULL);
MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
return TRUE;
}
+
return FALSE;
}
@@ -91,7 +92,7 @@ AesniInitialize ( IN BOOLEAN State
)
{
- MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
+ MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
//
// SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index,
@@ -102,7 +103,7 @@ AesniInitialize ( // programming it.
//
if (CpuInfo->ProcessorInfo.Location.Thread == 0) {
- MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;
+ MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;
ASSERT (MsrFeatureConfig != NULL);
if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) {
CPU_REGISTER_TABLE_WRITE_FIELD (
@@ -115,5 +116,6 @@ AesniInitialize ( );
}
}
+
return RETURN_SUCCESS;
}
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c index 98a3408370..bc09f8bc62 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c @@ -66,7 +66,7 @@ C1eInitialize ( // MSR_NEHALEM_POWER_CTL once for each package.
//
if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {
- return RETURN_SUCCESS;
+ return RETURN_SUCCESS;
}
CPU_REGISTER_TABLE_WRITE_FIELD (
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c index 94d596605b..5874a99570 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c @@ -9,8 +9,8 @@ #include "CpuCommonFeatures.h"
typedef struct {
- CPUID_THERMAL_POWER_MANAGEMENT_EAX ThermalPowerManagementEax;
- MSR_IA32_CLOCK_MODULATION_REGISTER ClockModulation;
+ CPUID_THERMAL_POWER_MANAGEMENT_EAX ThermalPowerManagementEax;
+ MSR_IA32_CLOCK_MODULATION_REGISTER ClockModulation;
} CLOCK_MODULATION_CONFIG_DATA;
/**
@@ -28,7 +28,7 @@ ClockModulationGetConfigData ( IN UINTN NumberOfProcessors
)
{
- UINT32 *ConfigData;
+ UINT32 *ConfigData;
ConfigData = AllocateZeroPool (sizeof (CLOCK_MODULATION_CONFIG_DATA) * NumberOfProcessors);
ASSERT (ConfigData != NULL);
@@ -59,10 +59,10 @@ ClockModulationSupport ( IN VOID *ConfigData OPTIONAL
)
{
- CLOCK_MODULATION_CONFIG_DATA *CmConfigData;
+ CLOCK_MODULATION_CONFIG_DATA *CmConfigData;
if (CpuInfo->CpuIdVersionInfoEdx.Bits.ACPI == 1) {
- CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData;
+ CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData;
ASSERT (CmConfigData != NULL);
AsmCpuid (
CPUID_THERMAL_POWER_MANAGEMENT,
@@ -74,6 +74,7 @@ ClockModulationSupport ( CmConfigData[ProcessorNumber].ClockModulation.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
return TRUE;
}
+
return FALSE;
}
@@ -103,15 +104,15 @@ ClockModulationInitialize ( IN BOOLEAN State
)
{
- CLOCK_MODULATION_CONFIG_DATA *CmConfigData;
- MSR_IA32_CLOCK_MODULATION_REGISTER *ClockModulation;
+ CLOCK_MODULATION_CONFIG_DATA *CmConfigData;
+ MSR_IA32_CLOCK_MODULATION_REGISTER *ClockModulation;
- CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData;
+ CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData;
ASSERT (CmConfigData != NULL);
ClockModulation = &CmConfigData[ProcessorNumber].ClockModulation;
if (State) {
- ClockModulation->Bits.OnDemandClockModulationEnable = 1;
+ ClockModulation->Bits.OnDemandClockModulationEnable = 1;
ClockModulation->Bits.OnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1;
if (CmConfigData[ProcessorNumber].ThermalPowerManagementEax.Bits.ECMD == 1) {
ClockModulation->Bits.ExtendedOnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0;
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index 74f27dcc44..5434a45f6a 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -860,7 +860,7 @@ X2ApicInitialize ( VOID *
EFIAPI
PpinGetConfigData (
- IN UINTN NumberOfProcessors
+ IN UINTN NumberOfProcessors
);
/**
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index 725ef7bd43..7f0e1004b9 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -20,7 +20,7 @@ CpuCommonFeaturesLibConstructor ( VOID
)
{
- RETURN_STATUS Status;
+ RETURN_STATUS Status;
if (IsCpuFeatureSupported (CPU_FEATURE_AESNI)) {
Status = RegisterCpuFeature (
@@ -33,6 +33,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_MWAIT)) {
Status = RegisterCpuFeature (
"MWAIT",
@@ -44,6 +45,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_ACPI)) {
Status = RegisterCpuFeature (
"ACPI",
@@ -55,6 +57,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_EIST)) {
Status = RegisterCpuFeature (
"EIST",
@@ -66,6 +69,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_FASTSTRINGS)) {
Status = RegisterCpuFeature (
"FastStrings",
@@ -77,6 +81,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) {
Status = RegisterCpuFeature (
"Lock Feature Control Register",
@@ -88,6 +93,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) {
Status = RegisterCpuFeature (
"SMX",
@@ -100,6 +106,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) {
Status = RegisterCpuFeature (
"VMX",
@@ -112,6 +119,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_LIMIT_CPUID_MAX_VAL)) {
Status = RegisterCpuFeature (
"Limit CpuId Maximum Value",
@@ -123,6 +131,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_MCE)) {
Status = RegisterCpuFeature (
"Machine Check Enable",
@@ -134,6 +143,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_MCA)) {
Status = RegisterCpuFeature (
"Machine Check Architect",
@@ -145,6 +155,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_MCG_CTL)) {
Status = RegisterCpuFeature (
"MCG_CTL",
@@ -156,6 +167,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_PENDING_BREAK)) {
Status = RegisterCpuFeature (
"Pending Break",
@@ -167,6 +179,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_C1E)) {
Status = RegisterCpuFeature (
"C1E",
@@ -178,6 +191,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) {
Status = RegisterCpuFeature (
"X2Apic",
@@ -189,6 +203,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) {
Status = RegisterCpuFeature (
"PPIN",
@@ -200,6 +215,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) {
Status = RegisterCpuFeature (
"LMCE",
@@ -212,6 +228,7 @@ CpuCommonFeaturesLibConstructor ( );
ASSERT_EFI_ERROR (Status);
}
+
if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) {
Status = RegisterCpuFeature (
"Proc Trace",
@@ -226,6 +243,3 @@ CpuCommonFeaturesLibConstructor ( return RETURN_SUCCESS;
}
-
-
-
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c index ed42afe289..aedf3e6f2c 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c @@ -69,7 +69,8 @@ EistInitialize ( //
if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
- IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
+ {
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c index 9ae5216555..63c3bf9d10 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c @@ -40,7 +40,8 @@ FastStringsInitialize ( //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
- IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
+ {
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c index 8ad81a6e87..63ec27a1a6 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c @@ -68,7 +68,8 @@ VmxInitialize ( //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
- IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
+ {
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
@@ -146,7 +147,8 @@ LockFeatureControlRegisterInitialize ( //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
- IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
+ {
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
@@ -218,7 +220,7 @@ SmxInitialize ( IN BOOLEAN State
)
{
- RETURN_STATUS Status;
+ RETURN_STATUS Status;
//
// The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for
@@ -226,7 +228,8 @@ SmxInitialize ( // core.
//
if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
- IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
+ {
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
@@ -236,7 +239,7 @@ SmxInitialize ( if (State && (!IsCpuFeatureInSetting (CPU_FEATURE_VMX))) {
DEBUG ((DEBUG_WARN, "Warning :: Can't enable SMX feature when VMX feature not enabled, disable it.\n"));
- State = FALSE;
+ State = FALSE;
Status = RETURN_UNSUPPORTED;
}
@@ -247,7 +250,7 @@ SmxInitialize ( IA32_CR4,
Bits.SMXE,
(State) ? 1 : 0
- )
+ )
CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
ProcessorNumber,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c index 71d82eab8d..bf495f96bb 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c @@ -72,7 +72,8 @@ LimitCpuidMaxvalInitialize ( IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
- IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
+ {
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index 0e78a0ce26..d8b070d9f1 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -102,6 +102,7 @@ McaSupport ( if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) {
return FALSE;
}
+
return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1);
}
@@ -144,7 +145,8 @@ McaInitialize ( IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
- IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
+ {
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
@@ -162,7 +164,7 @@ McaInitialize ( if (State) {
McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
- for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {
+ for (BankIndex = 0; BankIndex < (UINT32)McgCap.Bits.Count; BankIndex++) {
CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber,
Msr,
@@ -172,7 +174,7 @@ McaInitialize ( }
if (PcdGetBool (PcdIsPowerOnReset)) {
- for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {
+ for (BankIndex = 0; BankIndex < (UINTN)McgCap.Bits.Count; BankIndex++) {
CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber,
Msr,
@@ -215,6 +217,7 @@ McgCtlSupport ( if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {
return FALSE;
}
+
McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
return (McgCap.Bits.MCG_CTL_P == 1);
}
@@ -249,7 +252,7 @@ McgCtlInitialize ( ProcessorNumber,
Msr,
MSR_IA32_MCG_CTL,
- (State)? MAX_UINT64 : 0
+ (State) ? MAX_UINT64 : 0
);
return RETURN_SUCCESS;
}
@@ -279,7 +282,7 @@ LmceSupport ( IN VOID *ConfigData OPTIONAL
)
{
- MSR_IA32_MCG_CAP_REGISTER McgCap;
+ MSR_IA32_MCG_CAP_REGISTER McgCap;
if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {
return FALSE;
@@ -287,9 +290,10 @@ LmceSupport ( McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
if (ProcessorNumber == 0) {
- DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0)));
+ DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0)));
}
- return (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0);
+
+ return (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0);
}
/**
@@ -325,7 +329,8 @@ LmceInitialize ( //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
- IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
+ {
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c index 9fcbaf8d5d..d55cf6c6f2 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c @@ -70,7 +70,8 @@ MonitorMwaitInitialize ( IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
- IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
+ {
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c index 3d7030d609..6095dbde05 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c @@ -36,9 +36,11 @@ PendingBreakSupport ( IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
- IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
+ {
return (CpuInfo->CpuIdVersionInfoEdx.Bits.PBE == 1);
}
+
return FALSE;
}
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c index 468e425a0b..a7c2c12a51 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c @@ -20,10 +20,10 @@ VOID *
EFIAPI
PpinGetConfigData (
- IN UINTN NumberOfProcessors
+ IN UINTN NumberOfProcessors
)
{
- VOID *ConfigData;
+ VOID *ConfigData;
ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);
ASSERT (ConfigData != NULL);
@@ -55,8 +55,8 @@ PpinSupport ( IN VOID *ConfigData OPTIONAL
)
{
- MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
- MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
+ MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
+ MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
if ((CpuInfo->DisplayFamily == 0x06) &&
((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2
@@ -65,13 +65,14 @@ PpinSupport ( (CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable
(CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.
(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
- )) {
+ ))
+ {
//
// Check whether platform support this feature.
//
PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
if (PlatformInfo.Bits.PPIN_CAP != 0) {
- MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;
+ MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
ASSERT (MsrPpinCtrl != NULL);
MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
return TRUE;
@@ -112,9 +113,9 @@ PpinInitialize ( IN BOOLEAN State
)
{
- MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
+ MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
- MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;
+ MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
ASSERT (MsrPpinCtrl != NULL);
//
@@ -143,14 +144,14 @@ PpinInitialize ( // According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.
//
MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;
- MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;
+ MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;
} else {
//
// Disable and Lock.
// According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.
//
MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;
- MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;
+ MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;
}
CPU_REGISTER_TABLE_WRITE64 (
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c index e567ed54e7..04e6a60728 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c @@ -17,8 +17,7 @@ /// be terminated by an entry with the END bit set to 1, so 2
/// entries are required to use a single valid entry.
///
-#define MAX_TOPA_ENTRY_COUNT 2
-
+#define MAX_TOPA_ENTRY_COUNT 2
///
/// Processor trace output scheme selection.
@@ -29,25 +28,25 @@ typedef enum { } RTIT_OUTPUT_SCHEME;
typedef struct {
- BOOLEAN TopaSupported;
- BOOLEAN SingleRangeSupported;
- MSR_IA32_RTIT_CTL_REGISTER RtitCtrl;
- MSR_IA32_RTIT_OUTPUT_BASE_REGISTER RtitOutputBase;
- MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER RtitOutputMaskPtrs;
+ BOOLEAN TopaSupported;
+ BOOLEAN SingleRangeSupported;
+ MSR_IA32_RTIT_CTL_REGISTER RtitCtrl;
+ MSR_IA32_RTIT_OUTPUT_BASE_REGISTER RtitOutputBase;
+ MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER RtitOutputMaskPtrs;
} PROC_TRACE_PROCESSOR_DATA;
typedef struct {
- UINT32 NumberOfProcessors;
+ UINT32 NumberOfProcessors;
- UINT8 ProcTraceOutputScheme;
- UINT32 ProcTraceMemSize;
+ UINT8 ProcTraceOutputScheme;
+ UINT32 ProcTraceMemSize;
- UINTN *ThreadMemRegionTable;
- UINTN AllocatedThreads;
+ UINTN *ThreadMemRegionTable;
+ UINTN AllocatedThreads;
- UINTN *TopaMemArray;
+ UINTN *TopaMemArray;
- PROC_TRACE_PROCESSOR_DATA *ProcessorData;
+ PROC_TRACE_PROCESSOR_DATA *ProcessorData;
} PROC_TRACE_DATA;
typedef struct {
@@ -73,10 +72,10 @@ ProcTraceGetConfigData ( ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors);
ASSERT (ConfigData != NULL);
- ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *) ((UINT8*) ConfigData + sizeof (PROC_TRACE_DATA));
+ ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *)((UINT8 *)ConfigData + sizeof (PROC_TRACE_DATA));
- ConfigData->NumberOfProcessors = (UINT32) NumberOfProcessors;
- ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);
+ ConfigData->NumberOfProcessors = (UINT32)NumberOfProcessors;
+ ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);
ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme);
return ConfigData;
@@ -107,17 +106,18 @@ ProcTraceSupport ( IN VOID *ConfigData OPTIONAL
)
{
- PROC_TRACE_DATA *ProcTraceData;
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
- CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
+ PROC_TRACE_DATA *ProcTraceData;
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
+ CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
//
// Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)
//
- ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
+ ProcTraceData = (PROC_TRACE_DATA *)ConfigData;
ASSERT (ProcTraceData != NULL);
if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||
- (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) {
+ (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA))
+ {
return FALSE;
}
@@ -130,12 +130,13 @@ ProcTraceSupport ( }
AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);
- ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1);
- ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1);
+ ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN)(Ecx.Bits.RTIT == 1);
+ ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN)(Ecx.Bits.SingleRangeOutput == 1);
if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||
- (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) {
- ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
- ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
+ (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)))
+ {
+ ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
+ ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
return TRUE;
}
@@ -170,36 +171,37 @@ ProcTraceInitialize ( IN BOOLEAN State
)
{
- UINT32 MemRegionSize;
- UINTN Pages;
- UINTN Alignment;
- UINTN MemRegionBaseAddr;
- UINTN *ThreadMemRegionTable;
- UINTN Index;
- UINTN TopaTableBaseAddr;
- UINTN AlignedAddress;
- UINTN *TopaMemArray;
- PROC_TRACE_TOPA_TABLE *TopaTable;
- PROC_TRACE_DATA *ProcTraceData;
- BOOLEAN FirstIn;
- MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
- MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
- MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
+ UINT32 MemRegionSize;
+ UINTN Pages;
+ UINTN Alignment;
+ UINTN MemRegionBaseAddr;
+ UINTN *ThreadMemRegionTable;
+ UINTN Index;
+ UINTN TopaTableBaseAddr;
+ UINTN AlignedAddress;
+ UINTN *TopaMemArray;
+ PROC_TRACE_TOPA_TABLE *TopaTable;
+ PROC_TRACE_DATA *ProcTraceData;
+ BOOLEAN FirstIn;
+ MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
+ MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
+ MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;
- RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
+ RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
//
// The scope of the MSR_IA32_RTIT_* is core for below processor type, only program
// MSR_IA32_RTIT_* for thread 0 in each core.
//
if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
- IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
+ IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
+ {
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
}
- ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
+ ProcTraceData = (PROC_TRACE_DATA *)ConfigData;
ASSERT (ProcTraceData != NULL);
//
@@ -235,7 +237,7 @@ ProcTraceInitialize ( }
MemRegionBaseAddr = 0;
- FirstIn = FALSE;
+ FirstIn = FALSE;
if (ProcTraceData->ThreadMemRegionTable == NULL) {
FirstIn = TRUE;
@@ -245,7 +247,7 @@ ProcTraceInitialize ( ///
/// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding
///
- MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));
+ MemRegionSize = (UINT32)(1 << (ProcTraceData->ProcTraceMemSize + 12));
if (FirstIn) {
DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));
}
@@ -258,32 +260,34 @@ ProcTraceInitialize ( // address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be
// aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 cleared.
//
- ThreadMemRegionTable = (UINTN *) AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));
+ ThreadMemRegionTable = (UINTN *)AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));
if (ThreadMemRegionTable == NULL) {
DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));
return RETURN_OUT_OF_RESOURCES;
}
+
ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;
for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {
- Pages = EFI_SIZE_TO_PAGES (MemRegionSize);
- Alignment = MemRegionSize;
- AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
+ Pages = EFI_SIZE_TO_PAGES (MemRegionSize);
+ Alignment = MemRegionSize;
+ AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);
if (AlignedAddress == 0) {
DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads));
if (Index == 0) {
//
// Could not allocate for BSP even
//
- FreePool ((VOID *) ThreadMemRegionTable);
+ FreePool ((VOID *)ThreadMemRegionTable);
ThreadMemRegionTable = NULL;
return RETURN_OUT_OF_RESOURCES;
}
+
break;
}
ThreadMemRegionTable[Index] = AlignedAddress;
- DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index]));
+ DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64)ThreadMemRegionTable[Index]));
}
DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads));
@@ -303,7 +307,8 @@ ProcTraceInitialize ( // Single Range output scheme
//
if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
- (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {
+ (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))
+ {
if (FirstIn) {
DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
}
@@ -322,9 +327,9 @@ ProcTraceInitialize ( //
// Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region
//
- OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
- OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;
- OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;
+ OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
+ OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;
+ OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;
CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber,
Msr,
@@ -335,9 +340,9 @@ ProcTraceInitialize ( //
// Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)
//
- OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
+ OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;
- OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;
+ OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;
CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber,
Msr,
@@ -350,7 +355,8 @@ ProcTraceInitialize ( // ToPA(Table of physical address) scheme
//
if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
- (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {
+ (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA))
+ {
//
// Create ToPA structure aligned at 4KB for each logical thread
// with at least 2 entries by 8 bytes size each. The first entry
@@ -364,35 +370,38 @@ ProcTraceInitialize ( //
// Let BSP allocate ToPA table mem for all threads
//
- TopaMemArray = (UINTN *) AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));
+ TopaMemArray = (UINTN *)AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));
if (TopaMemArray == NULL) {
DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));
return RETURN_OUT_OF_RESOURCES;
}
+
ProcTraceData->TopaMemArray = TopaMemArray;
for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {
- Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));
- Alignment = 0x1000;
- AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
+ Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));
+ Alignment = 0x1000;
+ AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);
if (AlignedAddress == 0) {
if (Index < ProcTraceData->AllocatedThreads) {
ProcTraceData->AllocatedThreads = Index;
}
+
DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));
if (Index == 0) {
//
// Could not allocate for BSP even
//
- FreePool ((VOID *) TopaMemArray);
+ FreePool ((VOID *)TopaMemArray);
TopaMemArray = NULL;
return RETURN_OUT_OF_RESOURCES;
}
+
break;
}
TopaMemArray[Index] = AlignedAddress;
- DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64) TopaMemArray[Index]));
+ DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64)TopaMemArray[Index]));
}
DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads));
@@ -404,26 +413,26 @@ ProcTraceInitialize ( return RETURN_SUCCESS;
}
- TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr;
- TopaEntryPtr = &TopaTable->TopaEntry[0];
- TopaEntryPtr->Uint64 = 0;
- TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;
- TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;
- TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;
- TopaEntryPtr->Bits.END = 0;
+ TopaTable = (PROC_TRACE_TOPA_TABLE *)TopaTableBaseAddr;
+ TopaEntryPtr = &TopaTable->TopaEntry[0];
+ TopaEntryPtr->Uint64 = 0;
+ TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;
+ TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;
+ TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;
+ TopaEntryPtr->Bits.END = 0;
- TopaEntryPtr = &TopaTable->TopaEntry[1];
- TopaEntryPtr->Uint64 = 0;
- TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;
- TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;
- TopaEntryPtr->Bits.END = 1;
+ TopaEntryPtr = &TopaTable->TopaEntry[1];
+ TopaEntryPtr->Uint64 = 0;
+ TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;
+ TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;
+ TopaEntryPtr->Bits.END = 1;
//
// Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base
//
- OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
- OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;
- OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;
+ OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
+ OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;
+ OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;
CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber,
Msr,
@@ -434,9 +443,9 @@ ProcTraceInitialize ( //
// Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0
//
- OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
+ OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0;
- OutputMaskPtrsReg.Bits.OutputOffset = 0;
+ OutputMaskPtrsReg.Bits.OutputOffset = 0;
CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber,
Msr,
@@ -458,10 +467,10 @@ ProcTraceInitialize ( ///
/// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)
///
- CtrlReg.Bits.OS = 1;
- CtrlReg.Bits.User = 1;
+ CtrlReg.Bits.OS = 1;
+ CtrlReg.Bits.User = 1;
CtrlReg.Bits.BranchEn = 1;
- CtrlReg.Bits.TraceEn = 1;
+ CtrlReg.Bits.TraceEn = 1;
CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber,
Msr,
diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c index 181dcae21c..220f307e5a 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c @@ -23,7 +23,7 @@ X2ApicGetConfigData ( IN UINTN NumberOfProcessors
)
{
- BOOLEAN *ConfigData;
+ BOOLEAN *ConfigData;
ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors);
ASSERT (ConfigData != NULL);
@@ -56,10 +56,10 @@ X2ApicSupport ( IN VOID *ConfigData OPTIONAL
)
{
- BOOLEAN *X2ApicEnabled;
+ BOOLEAN *X2ApicEnabled;
ASSERT (ConfigData != NULL);
- X2ApicEnabled = (BOOLEAN *) ConfigData;
+ X2ApicEnabled = (BOOLEAN *)ConfigData;
//
// *ConfigData indicates if X2APIC enabled on current processor
//
@@ -94,7 +94,7 @@ X2ApicInitialize ( IN BOOLEAN State
)
{
- BOOLEAN *X2ApicEnabled;
+ BOOLEAN *X2ApicEnabled;
//
// The scope of the MSR_IA32_APIC_BASE is core for below processor type, only program
@@ -107,7 +107,7 @@ X2ApicInitialize ( }
ASSERT (ConfigData != NULL);
- X2ApicEnabled = (BOOLEAN *) ConfigData;
+ X2ApicEnabled = (BOOLEAN *)ConfigData;
if (X2ApicEnabled[ProcessorNumber]) {
PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
@@ -133,5 +133,6 @@ X2ApicInitialize ( );
}
}
+
return RETURN_SUCCESS;
}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c index 49d0041e2f..903fac927e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c @@ -14,15 +14,15 @@ //
// 1 means an error code will be pushed, otherwise 0
//
-CONST UINT32 mErrorCodeFlag = 0x20227d00;
+CONST UINT32 mErrorCodeFlag = 0x20227d00;
//
// Define the maximum message length
//
#define MAX_DEBUG_MESSAGE_LENGTH 0x100
-CONST CHAR8 mExceptionReservedStr[] = "Reserved";
-CONST CHAR8 *mExceptionNameStr[] = {
+CONST CHAR8 mExceptionReservedStr[] = "Reserved";
+CONST CHAR8 *mExceptionNameStr[] = {
"#DE - Divide Error",
"#DB - Debug",
"NMI Interrupt",
@@ -66,10 +66,10 @@ CONST CHAR8 *mExceptionNameStr[] = { **/
CONST CHAR8 *
GetExceptionNameStr (
- IN EFI_EXCEPTION_TYPE ExceptionType
+ IN EFI_EXCEPTION_TYPE ExceptionType
)
{
- if ((UINTN) ExceptionType < EXCEPTION_KNOWN_NAME_NUM) {
+ if ((UINTN)ExceptionType < EXCEPTION_KNOWN_NAME_NUM) {
return mExceptionNameStr[ExceptionType];
} else {
return mExceptionReservedStr;
@@ -115,13 +115,13 @@ InternalPrintMessage ( **/
VOID
DumpModuleImageInfo (
- IN UINTN CurrentEip
+ IN UINTN CurrentEip
)
{
- EFI_STATUS Status;
- UINTN Pe32Data;
- VOID *PdbPointer;
- VOID *EntryPoint;
+ EFI_STATUS Status;
+ UINTN Pe32Data;
+ VOID *PdbPointer;
+ VOID *EntryPoint;
Pe32Data = PeCoffSearchImageBase (CurrentEip);
if (Pe32Data == 0) {
@@ -130,20 +130,22 @@ DumpModuleImageInfo ( //
// Find Image Base entry point
//
- Status = PeCoffLoaderGetEntryPoint ((VOID *) Pe32Data, &EntryPoint);
+ Status = PeCoffLoaderGetEntryPoint ((VOID *)Pe32Data, &EntryPoint);
if (EFI_ERROR (Status)) {
EntryPoint = NULL;
}
+
InternalPrintMessage ("!!!! Find image based on IP(0x%x) ", CurrentEip);
- PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
+ PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data);
if (PdbPointer != NULL) {
InternalPrintMessage ("%a", PdbPointer);
} else {
- InternalPrintMessage ("(No PDB) " );
+ InternalPrintMessage ("(No PDB) ");
}
+
InternalPrintMessage (
" (ImageBase=%016lp, EntryPoint=%016p) !!!!\n",
- (VOID *) Pe32Data,
+ (VOID *)Pe32Data,
EntryPoint
);
}
@@ -162,9 +164,9 @@ DumpModuleImageInfo ( **/
EFI_STATUS
ReadAndVerifyVectorInfo (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo,
- OUT RESERVED_VECTORS_DATA *ReservedVector,
- IN UINTN VectorCount
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo,
+ OUT RESERVED_VECTORS_DATA *ReservedVector,
+ IN UINTN VectorCount
)
{
while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {
@@ -174,10 +176,13 @@ ReadAndVerifyVectorInfo ( //
return EFI_INVALID_PARAMETER;
}
+
if (VectorInfo->VectorNumber < VectorCount) {
ReservedVector[VectorInfo->VectorNumber].Attribute = VectorInfo->Attribute;
}
- VectorInfo ++;
+
+ VectorInfo++;
}
+
return EFI_SUCCESS;
}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index 0544d6dba6..0f012bccde 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -20,21 +20,21 @@ #include <Library/SynchronizationLib.h>
#include <Library/CpuExceptionHandlerLib.h>
-#define CPU_EXCEPTION_NUM 32
-#define CPU_INTERRUPT_NUM 256
-#define HOOKAFTER_STUB_SIZE 16
+#define CPU_EXCEPTION_NUM 32
+#define CPU_INTERRUPT_NUM 256
+#define HOOKAFTER_STUB_SIZE 16
//
// Exception Error Code of Page-Fault Exception
//
-#define IA32_PF_EC_P BIT0
-#define IA32_PF_EC_WR BIT1
-#define IA32_PF_EC_US BIT2
-#define IA32_PF_EC_RSVD BIT3
-#define IA32_PF_EC_ID BIT4
-#define IA32_PF_EC_PK BIT5
-#define IA32_PF_EC_SS BIT6
-#define IA32_PF_EC_SGX BIT15
+#define IA32_PF_EC_P BIT0
+#define IA32_PF_EC_WR BIT1
+#define IA32_PF_EC_US BIT2
+#define IA32_PF_EC_RSVD BIT3
+#define IA32_PF_EC_ID BIT4
+#define IA32_PF_EC_PK BIT5
+#define IA32_PF_EC_SS BIT6
+#define IA32_PF_EC_SGX BIT15
#include "ArchInterruptDefs.h"
@@ -47,26 +47,26 @@ #define CPU_KNOWN_GOOD_STACK_SIZE \
FixedPcdGet32 (PcdCpuKnownGoodStackSize)
-#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)
+#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)
//
// Record exception handler information
//
typedef struct {
- UINTN ExceptionStart;
- UINTN ExceptionStubHeaderSize;
- UINTN HookAfterStubHeaderStart;
+ UINTN ExceptionStart;
+ UINTN ExceptionStubHeaderSize;
+ UINTN HookAfterStubHeaderStart;
} EXCEPTION_HANDLER_TEMPLATE_MAP;
typedef struct {
- UINTN IdtEntryCount;
- SPIN_LOCK DisplayMessageSpinLock;
- RESERVED_VECTORS_DATA *ReservedVectors;
- EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
+ UINTN IdtEntryCount;
+ SPIN_LOCK DisplayMessageSpinLock;
+ RESERVED_VECTORS_DATA *ReservedVectors;
+ EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
} EXCEPTION_HANDLER_DATA;
-extern CONST UINT32 mErrorCodeFlag;
-extern CONST UINTN mDoFarReturnFlag;
+extern CONST UINT32 mErrorCodeFlag;
+extern CONST UINTN mDoFarReturnFlag;
/**
Return address map of exception handler template so that C code can generate
@@ -77,7 +77,7 @@ extern CONST UINTN mDoFarReturnFlag; VOID
EFIAPI
AsmGetTemplateAddressMap (
- OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
+ OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
);
/**
@@ -90,8 +90,8 @@ AsmGetTemplateAddressMap ( **/
VOID
ArchUpdateIdtEntry (
- OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
- IN UINTN InterruptHandler
+ OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
+ IN UINTN InterruptHandler
);
/**
@@ -102,7 +102,7 @@ ArchUpdateIdtEntry ( **/
UINTN
ArchGetIdtHandler (
- IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
+ IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
);
/**
@@ -128,7 +128,7 @@ InternalPrintMessage ( **/
VOID
DumpModuleImageInfo (
- IN UINTN CurrentEip
+ IN UINTN CurrentEip
);
/**
@@ -139,8 +139,8 @@ DumpModuleImageInfo ( **/
VOID
DumpImageAndCpuContent (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
);
/**
@@ -157,8 +157,8 @@ DumpImageAndCpuContent ( **/
EFI_STATUS
InitializeCpuExceptionHandlersWorker (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
- IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData
);
/**
@@ -180,9 +180,9 @@ InitializeCpuExceptionHandlersWorker ( **/
EFI_STATUS
RegisterCpuInterruptHandlerWorker (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
- IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
+ IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
);
/**
@@ -210,9 +210,9 @@ UpdateIdtTable ( **/
VOID
ArchSaveExceptionContext (
- IN UINTN ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext,
- IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN UINTN ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext,
+ IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
);
/**
@@ -224,9 +224,9 @@ ArchSaveExceptionContext ( **/
VOID
ArchRestoreExceptionContext (
- IN UINTN ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext,
- IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN UINTN ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext,
+ IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
);
/**
@@ -240,9 +240,9 @@ ArchRestoreExceptionContext ( VOID
EFIAPI
AsmVectorNumFixup (
- IN VOID *NewVectorAddr,
- IN UINT8 VectorNum,
- IN VOID *OldVectorAddr
+ IN VOID *NewVectorAddr,
+ IN UINT8 VectorNum,
+ IN VOID *OldVectorAddr
);
/**
@@ -258,9 +258,9 @@ AsmVectorNumFixup ( **/
EFI_STATUS
ReadAndVerifyVectorInfo (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo,
- OUT RESERVED_VECTORS_DATA *ReservedVector,
- IN UINTN VectorCount
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo,
+ OUT RESERVED_VECTORS_DATA *ReservedVector,
+ IN UINTN VectorCount
);
/**
@@ -272,7 +272,7 @@ ReadAndVerifyVectorInfo ( **/
CONST CHAR8 *
GetExceptionNameStr (
- IN EFI_EXCEPTION_TYPE ExceptionType
+ IN EFI_EXCEPTION_TYPE ExceptionType
);
/**
@@ -284,9 +284,9 @@ GetExceptionNameStr ( **/
VOID
CommonExceptionHandlerWorker (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext,
- IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext,
+ IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
);
/**
@@ -301,7 +301,7 @@ CommonExceptionHandlerWorker ( **/
EFI_STATUS
ArchSetupExceptionStack (
- IN CPU_EXCEPTION_INIT_DATA *StackSwitchData
+ IN CPU_EXCEPTION_INIT_DATA *StackSwitchData
);
/**
@@ -318,4 +318,3 @@ AsmGetTssTemplateMap ( );
#endif
-
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c index fd59f09ecd..61f11e98f8 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c @@ -12,17 +12,17 @@ #include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
-CONST UINTN mDoFarReturnFlag = 0;
+CONST UINTN mDoFarReturnFlag = 0;
-RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM];
-EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];
-UINTN mEnabledInterruptNum = 0;
+RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM];
+EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];
+UINTN mEnabledInterruptNum = 0;
-EXCEPTION_HANDLER_DATA mExceptionHandlerData;
+EXCEPTION_HANDLER_DATA mExceptionHandlerData;
-UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
- CPU_KNOWN_GOOD_STACK_SIZE];
-UINT8 mNewGdt[CPU_TSS_GDT_SIZE];
+UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
+ CPU_KNOWN_GOOD_STACK_SIZE];
+UINT8 mNewGdt[CPU_TSS_GDT_SIZE];
/**
Common exception handler.
@@ -33,8 +33,8 @@ UINT8 mNewGdt[CPU_TSS_GDT_SIZE]; VOID
EFIAPI
CommonExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
CommonExceptionHandlerWorker (ExceptionType, SystemContext, &mExceptionHandlerData);
@@ -59,7 +59,7 @@ CommonExceptionHandler ( EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlers (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
mExceptionHandlerData.ReservedVectors = mReservedVectorsData;
@@ -87,19 +87,19 @@ InitializeCpuExceptionHandlers ( EFI_STATUS
EFIAPI
InitializeCpuInterruptHandlers (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
- EFI_STATUS Status;
- IA32_IDT_GATE_DESCRIPTOR *IdtTable;
- IA32_DESCRIPTOR IdtDescriptor;
- UINTN IdtEntryCount;
- EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
- UINTN Index;
- UINTN InterruptEntry;
- UINT8 *InterruptEntryCode;
- RESERVED_VECTORS_DATA *ReservedVectors;
- EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
+ EFI_STATUS Status;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ IA32_DESCRIPTOR IdtDescriptor;
+ UINTN IdtEntryCount;
+ EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
+ UINTN Index;
+ UINTN InterruptEntry;
+ UINT8 *InterruptEntryCode;
+ RESERVED_VECTORS_DATA *ReservedVectors;
+ EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
Status = gBS->AllocatePool (
EfiBootServicesCode,
@@ -107,7 +107,7 @@ InitializeCpuInterruptHandlers ( (VOID **)&ReservedVectors
);
ASSERT (!EFI_ERROR (Status) && ReservedVectors != NULL);
- SetMem ((VOID *) ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff);
+ SetMem ((VOID *)ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff);
if (VectorInfo != NULL) {
Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_INTERRUPT_NUM);
if (EFI_ERROR (Status)) {
@@ -127,6 +127,7 @@ InitializeCpuInterruptHandlers ( if (IdtEntryCount > CPU_INTERRUPT_NUM) {
IdtEntryCount = CPU_INTERRUPT_NUM;
}
+
//
// Create Interrupt Descriptor Table and Copy the old IDT table in
//
@@ -144,18 +145,18 @@ InitializeCpuInterruptHandlers ( );
ASSERT (!EFI_ERROR (Status) && InterruptEntryCode != NULL);
- InterruptEntry = (UINTN) InterruptEntryCode;
- for (Index = 0; Index < CPU_INTERRUPT_NUM; Index ++) {
+ InterruptEntry = (UINTN)InterruptEntryCode;
+ for (Index = 0; Index < CPU_INTERRUPT_NUM; Index++) {
CopyMem (
- (VOID *) InterruptEntry,
- (VOID *) TemplateMap.ExceptionStart,
+ (VOID *)InterruptEntry,
+ (VOID *)TemplateMap.ExceptionStart,
TemplateMap.ExceptionStubHeaderSize
);
- AsmVectorNumFixup ((VOID *) InterruptEntry, (UINT8) Index, (VOID *) TemplateMap.ExceptionStart);
+ AsmVectorNumFixup ((VOID *)InterruptEntry, (UINT8)Index, (VOID *)TemplateMap.ExceptionStart);
InterruptEntry += TemplateMap.ExceptionStubHeaderSize;
}
- TemplateMap.ExceptionStart = (UINTN) InterruptEntryCode;
+ TemplateMap.ExceptionStart = (UINTN)InterruptEntryCode;
mExceptionHandlerData.IdtEntryCount = CPU_INTERRUPT_NUM;
mExceptionHandlerData.ReservedVectors = ReservedVectors;
mExceptionHandlerData.ExternalInterruptHandler = ExternalInterruptHandler;
@@ -166,9 +167,9 @@ InitializeCpuInterruptHandlers ( //
// Load Interrupt Descriptor Table
//
- IdtDescriptor.Base = (UINTN) IdtTable;
- IdtDescriptor.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1);
- AsmWriteIdtr ((IA32_DESCRIPTOR *) &IdtDescriptor);
+ IdtDescriptor.Base = (UINTN)IdtTable;
+ IdtDescriptor.Limit = (UINT16)(sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1);
+ AsmWriteIdtr ((IA32_DESCRIPTOR *)&IdtDescriptor);
return EFI_SUCCESS;
}
@@ -199,8 +200,8 @@ InitializeCpuInterruptHandlers ( EFI_STATUS
EFIAPI
RegisterCpuInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData);
@@ -230,14 +231,14 @@ RegisterCpuInterruptHandler ( EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlersEx (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
- IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
)
{
- EFI_STATUS Status;
- CPU_EXCEPTION_INIT_DATA EssData;
- IA32_DESCRIPTOR Idtr;
- IA32_DESCRIPTOR Gdtr;
+ EFI_STATUS Status;
+ CPU_EXCEPTION_INIT_DATA EssData;
+ IA32_DESCRIPTOR Idtr;
+ IA32_DESCRIPTOR Gdtr;
//
// To avoid repeat initialization of default handlers, the caller should pass
@@ -246,7 +247,7 @@ InitializeCpuExceptionHandlersEx ( // version instead; or this method must be implemented as a simple wrapper of
// non-ex version of it, if this version has to be called.
//
- if (InitData == NULL || InitData->X64.InitDefaultHandlers) {
+ if ((InitData == NULL) || InitData->X64.InitDefaultHandlers) {
Status = InitializeCpuExceptionHandlers (VectorInfo);
} else {
Status = EFI_SUCCESS;
@@ -263,25 +264,26 @@ InitializeCpuExceptionHandlersEx ( AsmReadIdtr (&Idtr);
AsmReadGdtr (&Gdtr);
- EssData.X64.Revision = CPU_EXCEPTION_INIT_DATA_REV;
- EssData.X64.KnownGoodStackTop = (UINTN)mNewStack + sizeof (mNewStack);
- EssData.X64.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE;
- EssData.X64.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
+ EssData.X64.Revision = CPU_EXCEPTION_INIT_DATA_REV;
+ EssData.X64.KnownGoodStackTop = (UINTN)mNewStack + sizeof (mNewStack);
+ EssData.X64.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE;
+ EssData.X64.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;
- EssData.X64.IdtTable = (VOID *)Idtr.Base;
- EssData.X64.IdtTableSize = Idtr.Limit + 1;
- EssData.X64.GdtTable = mNewGdt;
- EssData.X64.GdtTableSize = sizeof (mNewGdt);
- EssData.X64.ExceptionTssDesc = mNewGdt + Gdtr.Limit + 1;
- EssData.X64.ExceptionTssDescSize = CPU_TSS_DESC_SIZE;
- EssData.X64.ExceptionTss = mNewGdt + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;
- EssData.X64.ExceptionTssSize = CPU_TSS_SIZE;
+ EssData.X64.IdtTable = (VOID *)Idtr.Base;
+ EssData.X64.IdtTableSize = Idtr.Limit + 1;
+ EssData.X64.GdtTable = mNewGdt;
+ EssData.X64.GdtTableSize = sizeof (mNewGdt);
+ EssData.X64.ExceptionTssDesc = mNewGdt + Gdtr.Limit + 1;
+ EssData.X64.ExceptionTssDescSize = CPU_TSS_DESC_SIZE;
+ EssData.X64.ExceptionTss = mNewGdt + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;
+ EssData.X64.ExceptionTssSize = CPU_TSS_SIZE;
InitData = &EssData;
}
+
Status = ArchSetupExceptionStack (InitData);
}
}
- return Status;
+ return Status;
}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c index 903449e0da..f13e8e7020 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -18,13 +18,13 @@ **/
VOID
ArchUpdateIdtEntry (
- OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
- IN UINTN InterruptHandler
+ OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
+ IN UINTN InterruptHandler
)
{
- IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
- IdtEntry->Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
- IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
+ IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
+ IdtEntry->Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
+ IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
}
/**
@@ -35,7 +35,7 @@ ArchUpdateIdtEntry ( **/
UINTN
ArchGetIdtHandler (
- IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
+ IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
)
{
return (UINTN)IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh) << 16);
@@ -50,13 +50,13 @@ ArchGetIdtHandler ( **/
VOID
ArchSaveExceptionContext (
- IN UINTN ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext,
- IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN UINTN ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext,
+ IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
)
{
- IA32_EFLAGS32 Eflags;
- RESERVED_VECTORS_DATA *ReservedVectors;
+ IA32_EFLAGS32 Eflags;
+ RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = ExceptionHandlerData->ReservedVectors;
//
@@ -71,13 +71,13 @@ ArchSaveExceptionContext ( //
// Clear IF flag to avoid old IDT handler enable interrupt by IRET
//
- Eflags.UintN = SystemContext.SystemContextIa32->Eflags;
- Eflags.Bits.IF = 0;
+ Eflags.UintN = SystemContext.SystemContextIa32->Eflags;
+ Eflags.Bits.IF = 0;
SystemContext.SystemContextIa32->Eflags = Eflags.UintN;
//
// Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin.
//
- SystemContext.SystemContextIa32->Eip = (UINTN) ReservedVectors[ExceptionType].HookAfterStubHeaderCode;
+ SystemContext.SystemContextIa32->Eip = (UINTN)ReservedVectors[ExceptionType].HookAfterStubHeaderCode;
}
/**
@@ -89,14 +89,14 @@ ArchSaveExceptionContext ( **/
VOID
ArchRestoreExceptionContext (
- IN UINTN ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext,
- IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN UINTN ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext,
+ IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
)
{
- RESERVED_VECTORS_DATA *ReservedVectors;
+ RESERVED_VECTORS_DATA *ReservedVectors;
- ReservedVectors = ExceptionHandlerData->ReservedVectors;
+ ReservedVectors = ExceptionHandlerData->ReservedVectors;
SystemContext.SystemContextIa32->Eflags = ReservedVectors[ExceptionType].OldFlags;
SystemContext.SystemContextIa32->Cs = ReservedVectors[ExceptionType].OldCs;
SystemContext.SystemContextIa32->Eip = ReservedVectors[ExceptionType].OldIp;
@@ -116,32 +116,33 @@ ArchRestoreExceptionContext ( **/
EFI_STATUS
ArchSetupExceptionStack (
- IN CPU_EXCEPTION_INIT_DATA *StackSwitchData
+ IN CPU_EXCEPTION_INIT_DATA *StackSwitchData
)
{
- IA32_DESCRIPTOR Gdtr;
- IA32_DESCRIPTOR Idtr;
- IA32_IDT_GATE_DESCRIPTOR *IdtTable;
- IA32_TSS_DESCRIPTOR *TssDesc;
- IA32_TASK_STATE_SEGMENT *Tss;
- UINTN StackTop;
- UINTN Index;
- UINTN Vector;
- UINTN TssBase;
- UINTN GdtSize;
- EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
-
- if (StackSwitchData == NULL ||
- StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV ||
- StackSwitchData->Ia32.KnownGoodStackTop == 0 ||
- StackSwitchData->Ia32.KnownGoodStackSize == 0 ||
- StackSwitchData->Ia32.StackSwitchExceptions == NULL ||
- StackSwitchData->Ia32.StackSwitchExceptionNumber == 0 ||
- StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM ||
- StackSwitchData->Ia32.GdtTable == NULL ||
- StackSwitchData->Ia32.IdtTable == NULL ||
- StackSwitchData->Ia32.ExceptionTssDesc == NULL ||
- StackSwitchData->Ia32.ExceptionTss == NULL) {
+ IA32_DESCRIPTOR Gdtr;
+ IA32_DESCRIPTOR Idtr;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ IA32_TSS_DESCRIPTOR *TssDesc;
+ IA32_TASK_STATE_SEGMENT *Tss;
+ UINTN StackTop;
+ UINTN Index;
+ UINTN Vector;
+ UINTN TssBase;
+ UINTN GdtSize;
+ EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
+
+ if ((StackSwitchData == NULL) ||
+ (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||
+ (StackSwitchData->Ia32.KnownGoodStackTop == 0) ||
+ (StackSwitchData->Ia32.KnownGoodStackSize == 0) ||
+ (StackSwitchData->Ia32.StackSwitchExceptions == NULL) ||
+ (StackSwitchData->Ia32.StackSwitchExceptionNumber == 0) ||
+ (StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||
+ (StackSwitchData->Ia32.GdtTable == NULL) ||
+ (StackSwitchData->Ia32.IdtTable == NULL) ||
+ (StackSwitchData->Ia32.ExceptionTssDesc == NULL) ||
+ (StackSwitchData->Ia32.ExceptionTss == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -159,7 +160,8 @@ ArchSetupExceptionStack ( }
if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize >
- ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize)) {
+ ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -168,11 +170,14 @@ ArchSetupExceptionStack ( // specified.
//
if (StackSwitchData->Ia32.ExceptionTssDescSize <
- sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) {
+ sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))
+ {
return EFI_INVALID_PARAMETER;
}
+
if (StackSwitchData->Ia32.ExceptionTssSize <
- sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) {
+ sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -191,13 +196,14 @@ ArchSetupExceptionStack ( (UINTN)(StackSwitchData->Ia32.GdtTable);
if ((UINTN)StackSwitchData->Ia32.GdtTable != Gdtr.Base) {
CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
- Gdtr.Base = (UINTN)StackSwitchData->Ia32.GdtTable;
+ Gdtr.Base = (UINTN)StackSwitchData->Ia32.GdtTable;
Gdtr.Limit = (UINT16)GdtSize - 1;
}
if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) {
Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable;
}
+
if (StackSwitchData->Ia32.IdtTableSize > 0) {
Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1);
}
@@ -208,14 +214,14 @@ ArchSetupExceptionStack ( //
TssBase = (UINTN)Tss;
- TssDesc->Uint64 = 0;
- TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
- TssDesc->Bits.BaseLow = (UINT16)TssBase;
- TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
- TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
- TssDesc->Bits.P = 1;
- TssDesc->Bits.LimitHigh = 0;
- TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
+ TssDesc->Uint64 = 0;
+ TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1;
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;
+ TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
+ TssDesc->Bits.P = 1;
+ TssDesc->Bits.LimitHigh = 0;
+ TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
//
// Fixup exception task descriptor and task-state segment
@@ -234,7 +240,7 @@ ArchSetupExceptionStack ( TssBase = (UINTN)Tss;
TssDesc->Uint64 = 0;
- TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
+ TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1;
TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
@@ -246,14 +252,15 @@ ArchSetupExceptionStack ( // Fixup TSS
//
Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index];
- if (Vector >= CPU_EXCEPTION_NUM ||
- Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) {
+ if ((Vector >= CPU_EXCEPTION_NUM) ||
+ (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))
+ {
continue;
}
ZeroMem (Tss, sizeof (*Tss));
- Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
- + Vector * TemplateMap.ExceptionStubHeaderSize);
+ Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
+ + Vector * TemplateMap.ExceptionStubHeaderSize);
Tss->EFLAGS = 0x2;
Tss->ESP = StackTop;
Tss->CR3 = AsmReadCr3 ();
@@ -264,7 +271,7 @@ ArchSetupExceptionStack ( Tss->FS = AsmReadFs ();
Tss->GS = AsmReadGs ();
- StackTop -= StackSwitchData->Ia32.KnownGoodStackSize;
+ StackTop -= StackSwitchData->Ia32.KnownGoodStackSize;
//
// Update IDT to use Task Gate for given exception
@@ -303,8 +310,8 @@ ArchSetupExceptionStack ( VOID
EFIAPI
DumpCpuContext (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
InternalPrintMessage (
@@ -331,8 +338,10 @@ DumpCpuContext ( (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX) != 0
);
}
+
InternalPrintMessage ("\n");
}
+
InternalPrintMessage (
"EIP - %08x, CS - %08x, EFLAGS - %08x\n",
SystemContext.SystemContextIa32->Eip,
@@ -406,8 +415,8 @@ DumpCpuContext ( **/
VOID
DumpImageAndCpuContent (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
DumpCpuContext (ExceptionType, SystemContext);
@@ -415,7 +424,8 @@ DumpImageAndCpuContent ( // Dump module image base and module entry point by EIP
//
if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) &&
- ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0)) {
+ ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0))
+ {
//
// The EIP in SystemContext could not be used
// if it is page fault with I/D set.
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h index fc37fbe582..211d2abe48 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h @@ -10,29 +10,29 @@ #define _ARCH_CPU_INTERRUPT_DEFS_H_
typedef struct {
- EFI_SYSTEM_CONTEXT_IA32 SystemContext;
- BOOLEAN ExceptionDataFlag;
- UINTN OldIdtHandler;
+ EFI_SYSTEM_CONTEXT_IA32 SystemContext;
+ BOOLEAN ExceptionDataFlag;
+ UINTN OldIdtHandler;
} EXCEPTION_HANDLER_CONTEXT;
//
// Register Structure Definitions
//
typedef struct {
- EFI_STATUS_CODE_DATA Header;
- EFI_SYSTEM_CONTEXT_IA32 SystemContext;
+ EFI_STATUS_CODE_DATA Header;
+ EFI_SYSTEM_CONTEXT_IA32 SystemContext;
} CPU_STATUS_CODE_TEMPLATE;
typedef struct {
- SPIN_LOCK SpinLock;
- UINT32 ApicId;
- UINT32 Attribute;
- UINTN ExceptonHandler;
- UINTN OldFlags;
- UINTN OldCs;
- UINTN OldIp;
- UINTN ExceptionData;
- UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
+ SPIN_LOCK SpinLock;
+ UINT32 ApicId;
+ UINT32 Attribute;
+ UINTN ExceptonHandler;
+ UINTN OldFlags;
+ UINTN OldCs;
+ UINTN OldIp;
+ UINTN ExceptionData;
+ UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
} RESERVED_VECTORS_DATA;
#define CPU_TSS_DESC_SIZE \
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c index d256643435..687fc4177f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c @@ -13,11 +13,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
-CONST UINTN mDoFarReturnFlag = 0;
+CONST UINTN mDoFarReturnFlag = 0;
typedef struct {
- UINT8 ExceptionStubHeader[HOOKAFTER_STUB_SIZE];
- EXCEPTION_HANDLER_DATA *ExceptionHandlerData;
+ UINT8 ExceptionStubHeader[HOOKAFTER_STUB_SIZE];
+ EXCEPTION_HANDLER_DATA *ExceptionHandlerData;
} EXCEPTION0_STUB_HEADER;
/**
@@ -34,9 +34,9 @@ GetExceptionHandlerData ( VOID
)
{
- IA32_DESCRIPTOR IdtDescriptor;
- IA32_IDT_GATE_DESCRIPTOR *IdtTable;
- EXCEPTION0_STUB_HEADER *Exception0StubHeader;
+ IA32_DESCRIPTOR IdtDescriptor;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ EXCEPTION0_STUB_HEADER *Exception0StubHeader;
AsmReadIdtr (&IdtDescriptor);
IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;
@@ -56,12 +56,13 @@ GetExceptionHandlerData ( **/
VOID
SetExceptionHandlerData (
- IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
)
{
- EXCEPTION0_STUB_HEADER *Exception0StubHeader;
- IA32_DESCRIPTOR IdtDescriptor;
- IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ EXCEPTION0_STUB_HEADER *Exception0StubHeader;
+ IA32_DESCRIPTOR IdtDescriptor;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+
//
// Duplicate the exception #0 stub header in pool and cache the ExceptionHandlerData just after the stub header.
// So AP can get the ExceptionHandlerData by reading the IDT[0].
@@ -89,8 +90,8 @@ SetExceptionHandlerData ( VOID
EFIAPI
CommonExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
EXCEPTION_HANDLER_DATA *ExceptionHandlerData;
@@ -120,12 +121,12 @@ CommonExceptionHandler ( EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlers (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
- EFI_STATUS Status;
- EXCEPTION_HANDLER_DATA *ExceptionHandlerData;
- RESERVED_VECTORS_DATA *ReservedVectors;
+ EFI_STATUS Status;
+ EXCEPTION_HANDLER_DATA *ExceptionHandlerData;
+ RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = AllocatePool (sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM);
ASSERT (ReservedVectors != NULL);
@@ -166,7 +167,7 @@ InitializeCpuExceptionHandlers ( EFI_STATUS
EFIAPI
InitializeCpuInterruptHandlers (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
return EFI_UNSUPPORTED;
@@ -198,8 +199,8 @@ InitializeCpuInterruptHandlers ( EFI_STATUS
EFIAPI
RegisterCpuInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
return EFI_UNSUPPORTED;
@@ -230,11 +231,11 @@ RegisterCpuInterruptHandler ( EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlersEx (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
- IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// To avoid repeat initialization of default handlers, the caller should pass
@@ -243,7 +244,7 @@ InitializeCpuExceptionHandlersEx ( // version instead; or this method must be implemented as a simple wrapper of
// non-ex version of it, if this version has to be called.
//
- if (InitData == NULL || InitData->Ia32.InitDefaultHandlers) {
+ if ((InitData == NULL) || InitData->Ia32.InitDefaultHandlers) {
Status = InitializeCpuExceptionHandlers (VectorInfo);
} else {
Status = EFI_SUCCESS;
@@ -253,10 +254,10 @@ InitializeCpuExceptionHandlersEx ( //
// Initializing stack switch is only necessary for Stack Guard functionality.
//
- if (PcdGetBool (PcdCpuStackGuard) && InitData != NULL) {
+ if (PcdGetBool (PcdCpuStackGuard) && (InitData != NULL)) {
Status = ArchSetupExceptionStack (InitData);
}
}
- return Status;
+ return Status;
}
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c index 892d349d4b..762ea2460f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c @@ -19,14 +19,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
VOID
CommonExceptionHandlerWorker (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext,
- IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext,
+ IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
)
{
- EXCEPTION_HANDLER_CONTEXT *ExceptionHandlerContext;
- RESERVED_VECTORS_DATA *ReservedVectors;
- EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
+ EXCEPTION_HANDLER_CONTEXT *ExceptionHandlerContext;
+ RESERVED_VECTORS_DATA *ReservedVectors;
+ EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
if (ExceptionType == VC_EXCEPTION) {
EFI_STATUS Status;
@@ -45,68 +45,72 @@ CommonExceptionHandlerWorker ( }
}
- ExceptionHandlerContext = (EXCEPTION_HANDLER_CONTEXT *) (UINTN) (SystemContext.SystemContextIa32);
+ ExceptionHandlerContext = (EXCEPTION_HANDLER_CONTEXT *)(UINTN)(SystemContext.SystemContextIa32);
ReservedVectors = ExceptionHandlerData->ReservedVectors;
ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler;
switch (ReservedVectors[ExceptionType].Attribute) {
- case EFI_VECTOR_HANDOFF_HOOK_BEFORE:
- //
- // The new exception handler registered by RegisterCpuInterruptHandler() is executed BEFORE original handler.
- // Save the original handler to stack so the assembly code can jump to it instead of returning from handler.
- //
- ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;
- ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler;
- break;
- case EFI_VECTOR_HANDOFF_HOOK_AFTER:
- while (TRUE) {
- //
- // If spin-lock can be acquired, it's the first time entering here.
- //
- if (AcquireSpinLockOrFail (&ReservedVectors[ExceptionType].SpinLock)) {
- //
- // The new exception handler registered by RegisterCpuInterruptHandler() is executed AFTER original handler.
- // Save the original handler to stack but skip running the new handler so the original handler is executed
- // firstly.
- //
- ReservedVectors[ExceptionType].ApicId = GetApicId ();
- ArchSaveExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData);
- ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;
- ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler;
- return;
- }
+ case EFI_VECTOR_HANDOFF_HOOK_BEFORE:
//
- // If spin-lock cannot be acquired, it's the second time entering here.
- // 'break' instead of 'return' is used so the new exception handler can be executed.
+ // The new exception handler registered by RegisterCpuInterruptHandler() is executed BEFORE original handler.
+ // Save the original handler to stack so the assembly code can jump to it instead of returning from handler.
//
- if (ReservedVectors[ExceptionType].ApicId == GetApicId ()) {
+ ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;
+ ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler;
+ break;
+ case EFI_VECTOR_HANDOFF_HOOK_AFTER:
+ while (TRUE) {
//
- // Old IDT handler has been executed, then restore CPU exception content to
- // run new exception handler.
+ // If spin-lock can be acquired, it's the first time entering here.
//
- ArchRestoreExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData);
+ if (AcquireSpinLockOrFail (&ReservedVectors[ExceptionType].SpinLock)) {
+ //
+ // The new exception handler registered by RegisterCpuInterruptHandler() is executed AFTER original handler.
+ // Save the original handler to stack but skip running the new handler so the original handler is executed
+ // firstly.
+ //
+ ReservedVectors[ExceptionType].ApicId = GetApicId ();
+ ArchSaveExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData);
+ ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;
+ ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler;
+ return;
+ }
+
//
- // Release spin lock for ApicId
+ // If spin-lock cannot be acquired, it's the second time entering here.
+ // 'break' instead of 'return' is used so the new exception handler can be executed.
//
- ReleaseSpinLock (&ReservedVectors[ExceptionType].SpinLock);
- break;
+ if (ReservedVectors[ExceptionType].ApicId == GetApicId ()) {
+ //
+ // Old IDT handler has been executed, then restore CPU exception content to
+ // run new exception handler.
+ //
+ ArchRestoreExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData);
+ //
+ // Release spin lock for ApicId
+ //
+ ReleaseSpinLock (&ReservedVectors[ExceptionType].SpinLock);
+ break;
+ }
+
+ CpuPause ();
}
- CpuPause ();
- }
- break;
- case 0xffffffff:
- break;
- default:
- //
- // It should never reach here
- //
- CpuDeadLoop ();
- break;
+
+ break;
+ case 0xffffffff:
+ break;
+ default:
+ //
+ // It should never reach here
+ //
+ CpuDeadLoop ();
+ break;
}
- if (ExternalInterruptHandler != NULL &&
- ExternalInterruptHandler[ExceptionType] != NULL) {
- (ExternalInterruptHandler[ExceptionType]) (ExceptionType, SystemContext);
+ if ((ExternalInterruptHandler != NULL) &&
+ (ExternalInterruptHandler[ExceptionType] != NULL))
+ {
+ (ExternalInterruptHandler[ExceptionType])(ExceptionType, SystemContext);
} else if (ExceptionType < CPU_EXCEPTION_NUM) {
//
// Get Spinlock to display CPU information
@@ -114,6 +118,7 @@ CommonExceptionHandlerWorker ( while (!AcquireSpinLockOrFail (&ExceptionHandlerData->DisplayMessageSpinLock)) {
CpuPause ();
}
+
//
// Initialize the serial port before dumping.
//
@@ -151,10 +156,10 @@ UpdateIdtTable ( IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
)
{
- UINT16 CodeSegment;
- UINTN Index;
- UINTN InterruptHandler;
- RESERVED_VECTORS_DATA *ReservedVectors;
+ UINT16 CodeSegment;
+ UINTN Index;
+ UINTN InterruptHandler;
+ RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = ExceptionHandlerData->ReservedVectors;
//
@@ -162,47 +167,47 @@ UpdateIdtTable ( //
CodeSegment = AsmReadCs ();
- for (Index = 0; Index < ExceptionHandlerData->IdtEntryCount; Index ++) {
+ for (Index = 0; Index < ExceptionHandlerData->IdtEntryCount; Index++) {
IdtTable[Index].Bits.Selector = CodeSegment;
//
// Check reserved vectors attributes
//
switch (ReservedVectors[Index].Attribute) {
- case EFI_VECTOR_HANDOFF_DO_NOT_HOOK:
- //
- // Keep original IDT entry
- //
- continue;
- case EFI_VECTOR_HANDOFF_HOOK_AFTER:
- InitializeSpinLock (&ReservedVectors[Index].SpinLock);
- CopyMem (
- (VOID *) ReservedVectors[Index].HookAfterStubHeaderCode,
- (VOID *) TemplateMap->HookAfterStubHeaderStart,
- TemplateMap->ExceptionStubHeaderSize
- );
- AsmVectorNumFixup (
- (VOID *) ReservedVectors[Index].HookAfterStubHeaderCode,
- (UINT8) Index,
- (VOID *) TemplateMap->HookAfterStubHeaderStart
- );
+ case EFI_VECTOR_HANDOFF_DO_NOT_HOOK:
+ //
+ // Keep original IDT entry
+ //
+ continue;
+ case EFI_VECTOR_HANDOFF_HOOK_AFTER:
+ InitializeSpinLock (&ReservedVectors[Index].SpinLock);
+ CopyMem (
+ (VOID *)ReservedVectors[Index].HookAfterStubHeaderCode,
+ (VOID *)TemplateMap->HookAfterStubHeaderStart,
+ TemplateMap->ExceptionStubHeaderSize
+ );
+ AsmVectorNumFixup (
+ (VOID *)ReservedVectors[Index].HookAfterStubHeaderCode,
+ (UINT8)Index,
+ (VOID *)TemplateMap->HookAfterStubHeaderStart
+ );
//
// Go on the following code
//
- case EFI_VECTOR_HANDOFF_HOOK_BEFORE:
- //
- // Save original IDT handler address
- //
- ReservedVectors[Index].ExceptonHandler = ArchGetIdtHandler (&IdtTable[Index]);
+ case EFI_VECTOR_HANDOFF_HOOK_BEFORE:
+ //
+ // Save original IDT handler address
+ //
+ ReservedVectors[Index].ExceptonHandler = ArchGetIdtHandler (&IdtTable[Index]);
//
// Go on the following code
//
- default:
- //
- // Update new IDT entry
- //
- InterruptHandler = TemplateMap->ExceptionStart + Index * TemplateMap->ExceptionStubHeaderSize;
- ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);
- break;
+ default:
+ //
+ // Update new IDT entry
+ //
+ InterruptHandler = TemplateMap->ExceptionStart + Index * TemplateMap->ExceptionStubHeaderSize;
+ ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);
+ break;
}
}
}
@@ -221,19 +226,19 @@ UpdateIdtTable ( **/
EFI_STATUS
InitializeCpuExceptionHandlersWorker (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
- IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData
)
{
- EFI_STATUS Status;
- IA32_DESCRIPTOR IdtDescriptor;
- UINTN IdtEntryCount;
- EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
- IA32_IDT_GATE_DESCRIPTOR *IdtTable;
- RESERVED_VECTORS_DATA *ReservedVectors;
+ EFI_STATUS Status;
+ IA32_DESCRIPTOR IdtDescriptor;
+ UINTN IdtEntryCount;
+ EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = ExceptionHandlerData->ReservedVectors;
- SetMem ((VOID *) ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);
+ SetMem ((VOID *)ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);
if (VectorInfo != NULL) {
Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_EXCEPTION_NUM);
if (EFI_ERROR (Status)) {
@@ -253,7 +258,7 @@ InitializeCpuExceptionHandlersWorker ( IdtEntryCount = CPU_EXCEPTION_NUM;
}
- IdtTable = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base;
+ IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;
AsmGetTemplateAddressMap (&TemplateMap);
ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE);
@@ -282,33 +287,33 @@ InitializeCpuExceptionHandlersWorker ( **/
EFI_STATUS
RegisterCpuInterruptHandlerWorker (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
- IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
+ IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
)
{
- UINTN EnabledInterruptNum;
- RESERVED_VECTORS_DATA *ReservedVectors;
- EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
+ UINTN EnabledInterruptNum;
+ RESERVED_VECTORS_DATA *ReservedVectors;
+ EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
EnabledInterruptNum = ExceptionHandlerData->IdtEntryCount;
ReservedVectors = ExceptionHandlerData->ReservedVectors;
ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler;
- if (InterruptType < 0 || InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum ||
- ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK) {
+ if ((InterruptType < 0) || (InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum) ||
+ (ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK))
+ {
return EFI_UNSUPPORTED;
}
- if (InterruptHandler == NULL && ExternalInterruptHandler[InterruptType] == NULL) {
+ if ((InterruptHandler == NULL) && (ExternalInterruptHandler[InterruptType] == NULL)) {
return EFI_INVALID_PARAMETER;
}
- if (InterruptHandler != NULL && ExternalInterruptHandler[InterruptType] != NULL) {
+ if ((InterruptHandler != NULL) && (ExternalInterruptHandler[InterruptType] != NULL)) {
return EFI_ALREADY_STARTED;
}
ExternalInterruptHandler[InterruptType] = InterruptHandler;
return EFI_SUCCESS;
}
-
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c index 01b5a2f1f4..c614d5b0b6 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c @@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/VmgExitLib.h>
#include "CpuExceptionCommon.h"
-CONST UINTN mDoFarReturnFlag = 0;
+CONST UINTN mDoFarReturnFlag = 0;
/**
Common exception handler.
@@ -21,8 +21,8 @@ CONST UINTN mDoFarReturnFlag = 0; VOID
EFIAPI
CommonExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
if (ExceptionType == VC_EXCEPTION) {
@@ -79,26 +79,27 @@ CommonExceptionHandler ( EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlers (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
- EFI_STATUS Status;
- RESERVED_VECTORS_DATA ReservedVectorData[CPU_EXCEPTION_NUM];
- IA32_DESCRIPTOR IdtDescriptor;
- UINTN IdtEntryCount;
- UINT16 CodeSegment;
- EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
- IA32_IDT_GATE_DESCRIPTOR *IdtTable;
- UINTN Index;
- UINTN InterruptHandler;
+ EFI_STATUS Status;
+ RESERVED_VECTORS_DATA ReservedVectorData[CPU_EXCEPTION_NUM];
+ IA32_DESCRIPTOR IdtDescriptor;
+ UINTN IdtEntryCount;
+ UINT16 CodeSegment;
+ EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ UINTN Index;
+ UINTN InterruptHandler;
if (VectorInfo != NULL) {
- SetMem ((VOID *) ReservedVectorData, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);
+ SetMem ((VOID *)ReservedVectorData, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);
Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectorData, CPU_EXCEPTION_NUM);
if (EFI_ERROR (Status)) {
return EFI_INVALID_PARAMETER;
}
}
+
//
// Read IDT descriptor and calculate IDT size
//
@@ -110,6 +111,7 @@ InitializeCpuExceptionHandlers ( //
IdtEntryCount = CPU_EXCEPTION_NUM;
}
+
//
// Use current CS as the segment selector of interrupt gate in IDT
//
@@ -117,7 +119,7 @@ InitializeCpuExceptionHandlers ( AsmGetTemplateAddressMap (&TemplateMap);
IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;
- for (Index = 0; Index < IdtEntryCount; Index ++) {
+ for (Index = 0; Index < IdtEntryCount; Index++) {
IdtTable[Index].Bits.Selector = CodeSegment;
//
// Check reserved vectors attributes if has, only EFI_VECTOR_HANDOFF_DO_NOT_HOOK
@@ -128,12 +130,14 @@ InitializeCpuExceptionHandlers ( continue;
}
}
+
//
// Update IDT entry
//
InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize;
ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);
}
+
return EFI_SUCCESS;
}
@@ -156,7 +160,7 @@ InitializeCpuExceptionHandlers ( EFI_STATUS
EFIAPI
InitializeCpuInterruptHandlers (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
return EFI_UNSUPPORTED;
@@ -188,8 +192,8 @@ InitializeCpuInterruptHandlers ( EFI_STATUS
EFIAPI
RegisterCpuInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
return EFI_UNSUPPORTED;
@@ -220,8 +224,8 @@ RegisterCpuInterruptHandler ( EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlersEx (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
- IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
)
{
return InitializeCpuExceptionHandlers (VectorInfo);
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c index e7977d49b7..77ee74579f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c @@ -9,16 +9,17 @@ #include <PiSmm.h>
#include "CpuExceptionCommon.h"
-CONST UINTN mDoFarReturnFlag = 1;
+CONST UINTN mDoFarReturnFlag = 1;
//
// Spin lock for CPU information display
//
-SPIN_LOCK mDisplayMessageSpinLock;
+SPIN_LOCK mDisplayMessageSpinLock;
+
+RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM];
+EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];
+EXCEPTION_HANDLER_DATA mExceptionHandlerData;
-RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM];
-EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];
-EXCEPTION_HANDLER_DATA mExceptionHandlerData;
/**
Common exception handler.
@@ -28,8 +29,8 @@ EXCEPTION_HANDLER_DATA mExceptionHandlerData; VOID
EFIAPI
CommonExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
CommonExceptionHandlerWorker (ExceptionType, SystemContext, &mExceptionHandlerData);
@@ -54,7 +55,7 @@ CommonExceptionHandler ( EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlers (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
mExceptionHandlerData.ReservedVectors = mReservedVectorsData;
@@ -82,7 +83,7 @@ InitializeCpuExceptionHandlers ( EFI_STATUS
EFIAPI
InitializeCpuInterruptHandlers (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
return EFI_UNSUPPORTED;
@@ -114,8 +115,8 @@ InitializeCpuInterruptHandlers ( EFI_STATUS
EFIAPI
RegisterCpuInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData);
@@ -146,8 +147,8 @@ RegisterCpuInterruptHandler ( EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlersEx (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
- IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
)
{
return InitializeCpuExceptionHandlers (VectorInfo);
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c index d3da16e4df..cd7dccd481 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -17,8 +17,8 @@ **/
VOID
ArchUpdateIdtEntry (
- OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
- IN UINTN InterruptHandler
+ OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
+ IN UINTN InterruptHandler
)
{
IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
@@ -35,11 +35,11 @@ ArchUpdateIdtEntry ( **/
UINTN
ArchGetIdtHandler (
- IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
+ IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
)
{
- return IdtEntry->Bits.OffsetLow + (((UINTN) IdtEntry->Bits.OffsetHigh) << 16) +
- (((UINTN) IdtEntry->Bits.OffsetUpper) << 32);
+ return IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh) << 16) +
+ (((UINTN)IdtEntry->Bits.OffsetUpper) << 32);
}
/**
@@ -51,13 +51,13 @@ ArchGetIdtHandler ( **/
VOID
ArchSaveExceptionContext (
- IN UINTN ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext,
- IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN UINTN ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext,
+ IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
)
{
- IA32_EFLAGS32 Eflags;
- RESERVED_VECTORS_DATA *ReservedVectors;
+ IA32_EFLAGS32 Eflags;
+ RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = ExceptionHandlerData->ReservedVectors;
//
@@ -74,13 +74,13 @@ ArchSaveExceptionContext ( //
// Clear IF flag to avoid old IDT handler enable interrupt by IRET
//
- Eflags.UintN = SystemContext.SystemContextX64->Rflags;
- Eflags.Bits.IF = 0;
+ Eflags.UintN = SystemContext.SystemContextX64->Rflags;
+ Eflags.Bits.IF = 0;
SystemContext.SystemContextX64->Rflags = Eflags.UintN;
//
// Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin.
//
- SystemContext.SystemContextX64->Rip = (UINTN) ReservedVectors[ExceptionType].HookAfterStubHeaderCode;
+ SystemContext.SystemContextX64->Rip = (UINTN)ReservedVectors[ExceptionType].HookAfterStubHeaderCode;
}
/**
@@ -92,14 +92,14 @@ ArchSaveExceptionContext ( **/
VOID
ArchRestoreExceptionContext (
- IN UINTN ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext,
- IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
+ IN UINTN ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext,
+ IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
)
{
- RESERVED_VECTORS_DATA *ReservedVectors;
+ RESERVED_VECTORS_DATA *ReservedVectors;
- ReservedVectors = ExceptionHandlerData->ReservedVectors;
+ ReservedVectors = ExceptionHandlerData->ReservedVectors;
SystemContext.SystemContextX64->Ss = ReservedVectors[ExceptionType].OldSs;
SystemContext.SystemContextX64->Rsp = ReservedVectors[ExceptionType].OldSp;
SystemContext.SystemContextX64->Rflags = ReservedVectors[ExceptionType].OldFlags;
@@ -121,31 +121,32 @@ ArchRestoreExceptionContext ( **/
EFI_STATUS
ArchSetupExceptionStack (
- IN CPU_EXCEPTION_INIT_DATA *StackSwitchData
+ IN CPU_EXCEPTION_INIT_DATA *StackSwitchData
)
{
- IA32_DESCRIPTOR Gdtr;
- IA32_DESCRIPTOR Idtr;
- IA32_IDT_GATE_DESCRIPTOR *IdtTable;
- IA32_TSS_DESCRIPTOR *TssDesc;
- IA32_TASK_STATE_SEGMENT *Tss;
- UINTN StackTop;
- UINTN Index;
- UINTN Vector;
- UINTN TssBase;
- UINTN GdtSize;
-
- if (StackSwitchData == NULL ||
- StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV ||
- StackSwitchData->X64.KnownGoodStackTop == 0 ||
- StackSwitchData->X64.KnownGoodStackSize == 0 ||
- StackSwitchData->X64.StackSwitchExceptions == NULL ||
- StackSwitchData->X64.StackSwitchExceptionNumber == 0 ||
- StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM ||
- StackSwitchData->X64.GdtTable == NULL ||
- StackSwitchData->X64.IdtTable == NULL ||
- StackSwitchData->X64.ExceptionTssDesc == NULL ||
- StackSwitchData->X64.ExceptionTss == NULL) {
+ IA32_DESCRIPTOR Gdtr;
+ IA32_DESCRIPTOR Idtr;
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;
+ IA32_TSS_DESCRIPTOR *TssDesc;
+ IA32_TASK_STATE_SEGMENT *Tss;
+ UINTN StackTop;
+ UINTN Index;
+ UINTN Vector;
+ UINTN TssBase;
+ UINTN GdtSize;
+
+ if ((StackSwitchData == NULL) ||
+ (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||
+ (StackSwitchData->X64.KnownGoodStackTop == 0) ||
+ (StackSwitchData->X64.KnownGoodStackSize == 0) ||
+ (StackSwitchData->X64.StackSwitchExceptions == NULL) ||
+ (StackSwitchData->X64.StackSwitchExceptionNumber == 0) ||
+ (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||
+ (StackSwitchData->X64.GdtTable == NULL) ||
+ (StackSwitchData->X64.IdtTable == NULL) ||
+ (StackSwitchData->X64.ExceptionTssDesc == NULL) ||
+ (StackSwitchData->X64.ExceptionTss == NULL))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -163,7 +164,8 @@ ArchSetupExceptionStack ( }
if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) >
- ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize)) {
+ ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -173,6 +175,7 @@ ArchSetupExceptionStack ( if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {
return EFI_INVALID_PARAMETER;
}
+
if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {
return EFI_INVALID_PARAMETER;
}
@@ -196,13 +199,14 @@ ArchSetupExceptionStack ( (UINTN)(StackSwitchData->X64.GdtTable);
if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) {
CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
- Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable;
+ Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable;
Gdtr.Limit = (UINT16)GdtSize - 1;
}
if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) {
Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable;
}
+
if (StackSwitchData->X64.IdtTableSize > 0) {
Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1);
}
@@ -213,16 +217,16 @@ ArchSetupExceptionStack ( //
TssBase = (UINTN)Tss;
- TssDesc->Uint128.Uint64 = 0;
- TssDesc->Uint128.Uint64_1= 0;
- TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;
- TssDesc->Bits.BaseLow = (UINT16)TssBase;
- TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
- TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
- TssDesc->Bits.P = 1;
- TssDesc->Bits.LimitHigh = 0;
- TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
- TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
+ TssDesc->Uint128.Uint64 = 0;
+ TssDesc->Uint128.Uint64_1 = 0;
+ TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1;
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;
+ TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
+ TssDesc->Bits.P = 1;
+ TssDesc->Bits.LimitHigh = 0;
+ TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
+ TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
//
// Fixup exception task descriptor and task-state segment
@@ -236,16 +240,18 @@ ArchSetupExceptionStack ( // Fixup IST
//
Tss->IST[Index] = StackTop;
- StackTop -= StackSwitchData->X64.KnownGoodStackSize;
+ StackTop -= StackSwitchData->X64.KnownGoodStackSize;
//
// Set the IST field to enable corresponding IST
//
Vector = StackSwitchData->X64.StackSwitchExceptions[Index];
- if (Vector >= CPU_EXCEPTION_NUM ||
- Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) {
+ if ((Vector >= CPU_EXCEPTION_NUM) ||
+ (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))
+ {
continue;
}
+
IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1);
}
@@ -276,8 +282,8 @@ ArchSetupExceptionStack ( VOID
EFIAPI
DumpCpuContext (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
InternalPrintMessage (
@@ -304,8 +310,10 @@ DumpCpuContext ( (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_SGX) != 0
);
}
+
InternalPrintMessage ("\n");
}
+
InternalPrintMessage (
"RIP - %016lx, CS - %016lx, RFLAGS - %016lx\n",
SystemContext.SystemContextX64->Rip,
@@ -406,8 +414,8 @@ DumpCpuContext ( **/
VOID
DumpImageAndCpuContent (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
DumpCpuContext (ExceptionType, SystemContext);
@@ -415,7 +423,8 @@ DumpImageAndCpuContent ( // Dump module image base and module entry point by RIP
//
if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) &&
- ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0)) {
+ ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0))
+ {
//
// The RIP in SystemContext could not be used
// if it is page fault with I/D set.
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h index c3a07862ea..008670cb0d 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h @@ -10,9 +10,9 @@ #define _ARCH_CPU_INTERRUPT_DEFS_H_
typedef struct {
- EFI_SYSTEM_CONTEXT_X64 SystemContext;
- BOOLEAN ExceptionDataFlag;
- UINTN OldIdtHandler;
+ EFI_SYSTEM_CONTEXT_X64 SystemContext;
+ BOOLEAN ExceptionDataFlag;
+ UINTN OldIdtHandler;
} EXCEPTION_HANDLER_CONTEXT;
//
@@ -24,20 +24,20 @@ typedef struct { } CPU_STATUS_CODE_TEMPLATE;
typedef struct {
- SPIN_LOCK SpinLock;
- UINT32 ApicId;
- UINT32 Attribute;
- UINTN ExceptonHandler;
- UINTN OldSs;
- UINTN OldSp;
- UINTN OldFlags;
- UINTN OldCs;
- UINTN OldIp;
- UINTN ExceptionData;
- UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
+ SPIN_LOCK SpinLock;
+ UINT32 ApicId;
+ UINT32 Attribute;
+ UINTN ExceptonHandler;
+ UINTN OldSs;
+ UINTN OldSp;
+ UINTN OldFlags;
+ UINTN OldCs;
+ UINTN OldIp;
+ UINTN ExceptionData;
+ UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
} RESERVED_VECTORS_DATA;
-#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
-#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
+#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
+#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
#endif
diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c index 6ddf917bad..98363bd8f7 100644 --- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c +++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c @@ -38,4 +38,3 @@ InternalGetPerformanceCounterFrequency ( {
return CpuidCoreClockCalculateTscFrequency ();
}
-
diff --git a/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c b/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c index bce02eeef9..1955b90e54 100644 --- a/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c +++ b/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c @@ -13,7 +13,9 @@ #include <Library/DebugLib.h>
#include <Register/Cpuid.h>
-GUID mCpuCrystalFrequencyHobGuid = { 0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a } };
+GUID mCpuCrystalFrequencyHobGuid = {
+ 0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a }
+};
/**
Internal function to retrieves the 64-bit frequency in Hz.
@@ -41,11 +43,11 @@ CpuidCoreClockCalculateTscFrequency ( VOID
)
{
- UINT64 TscFrequency;
- UINT64 CoreXtalFrequency;
- UINT32 RegEax;
- UINT32 RegEbx;
- UINT32 RegEcx;
+ UINT64 TscFrequency;
+ UINT64 CoreXtalFrequency;
+ UINT32 RegEax;
+ UINT32 RegEbx;
+ UINT32 RegEcx;
//
// Use CPUID leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Information
@@ -57,11 +59,12 @@ CpuidCoreClockCalculateTscFrequency ( //
// If EAX or EBX returns 0, the XTAL ratio is not enumerated.
//
- if (RegEax == 0 || RegEbx ==0 ) {
+ if ((RegEax == 0) || (RegEbx == 0)) {
ASSERT (RegEax != 0);
ASSERT (RegEbx != 0);
return 0;
}
+
//
// If ECX returns 0, the XTAL frequency is not enumerated.
// And PcdCpuCoreCrystalClockFrequency defined should base on processor series.
@@ -69,7 +72,7 @@ CpuidCoreClockCalculateTscFrequency ( if (RegEcx == 0) {
CoreXtalFrequency = PcdGet64 (PcdCpuCoreCrystalClockFrequency);
} else {
- CoreXtalFrequency = (UINT64) RegEcx;
+ CoreXtalFrequency = (UINT64)RegEcx;
}
//
@@ -99,7 +102,7 @@ InternalCpuDelay ( //
// The target timer count is calculated here
//
- Ticks = AsmReadTsc() + Delay;
+ Ticks = AsmReadTsc () + Delay;
//
// Wait until time out
@@ -107,8 +110,8 @@ InternalCpuDelay ( // Thus, this function must be called within 10 years of reset since
// Intel guarantees a minimum of 10 years before the TSC wraps.
//
- while (AsmReadTsc() <= Ticks) {
- CpuPause();
+ while (AsmReadTsc () <= Ticks) {
+ CpuPause ();
}
}
@@ -128,7 +131,6 @@ MicroSecondDelay ( IN UINTN MicroSeconds
)
{
-
InternalCpuDelay (
DivU64x32 (
MultU64x64 (
@@ -136,8 +138,8 @@ MicroSecondDelay ( InternalGetPerformanceCounterFrequency ()
),
1000000u
- )
- );
+ )
+ );
return MicroSeconds;
}
@@ -158,7 +160,6 @@ NanoSecondDelay ( IN UINTN NanoSeconds
)
{
-
InternalCpuDelay (
DivU64x32 (
MultU64x64 (
@@ -166,8 +167,8 @@ NanoSecondDelay ( InternalGetPerformanceCounterFrequency ()
),
1000000000u
- )
- );
+ )
+ );
return NanoSeconds;
}
@@ -230,6 +231,7 @@ GetPerformanceCounterProperties ( if (EndValue != NULL) {
*EndValue = 0xffffffffffffffffULL;
}
+
return InternalGetPerformanceCounterFrequency ();
}
@@ -269,9 +271,9 @@ GetTimeInNanoSecond ( // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,
// i.e. highest bit set in Remainder should <= 33.
//
- Shift = MAX (0, HighBitSet64 (Remainder) - 33);
- Remainder = RShiftU64 (Remainder, (UINTN) Shift);
- Frequency = RShiftU64 (Frequency, (UINTN) Shift);
+ Shift = MAX (0, HighBitSet64 (Remainder) - 33);
+ Remainder = RShiftU64 (Remainder, (UINTN)Shift);
+ Frequency = RShiftU64 (Frequency, (UINTN)Shift);
NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
return NanoSeconds;
diff --git a/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c b/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c index 03a43fdae7..767ec80f8a 100644 --- a/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c +++ b/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c @@ -25,7 +25,7 @@ GetProcessorMicrocodeSignature ( VOID
)
{
- MSR_IA32_BIOS_SIGN_ID_REGISTER BiosSignIdMsr;
+ MSR_IA32_BIOS_SIGN_ID_REGISTER BiosSignIdMsr;
AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0);
AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL);
@@ -44,12 +44,12 @@ GetProcessorMicrocodeCpuId ( EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId
)
{
- MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr;
+ MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr;
ASSERT (MicrocodeCpuId != NULL);
- PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
- MicrocodeCpuId->PlatformId = (UINT8) PlatformIdMsr.Bits.PlatformId;
+ PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
+ MicrocodeCpuId->PlatformId = (UINT8)PlatformIdMsr.Bits.PlatformId;
AsmCpuid (CPUID_VERSION_INFO, &MicrocodeCpuId->ProcessorSignature, NULL, NULL, NULL);
}
@@ -71,10 +71,10 @@ GetProcessorMicrocodeCpuId ( UINT32
EFIAPI
GetMicrocodeLength (
- IN CPU_MICROCODE_HEADER *Microcode
+ IN CPU_MICROCODE_HEADER *Microcode
)
{
- UINT32 TotalSize;
+ UINT32 TotalSize;
ASSERT (Microcode != NULL);
@@ -82,6 +82,7 @@ GetMicrocodeLength ( if (Microcode->DataSize != 0) {
TotalSize = Microcode->TotalSize;
}
+
return TotalSize;
}
@@ -95,12 +96,12 @@ GetMicrocodeLength ( VOID
EFIAPI
LoadMicrocode (
- IN CPU_MICROCODE_HEADER *Microcode
+ IN CPU_MICROCODE_HEADER *Microcode
)
{
ASSERT (Microcode != NULL);
- AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, (UINT64) (UINTN) (Microcode + 1));
+ AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, (UINT64)(UINTN)(Microcode + 1));
}
/**
@@ -119,13 +120,13 @@ LoadMicrocode ( **/
BOOLEAN
IsProcessorMatchedMicrocode (
- IN UINT32 ProcessorSignature,
- IN UINT32 ProcessorFlags,
- IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,
- IN UINTN MicrocodeCpuIdCount
+ IN UINT32 ProcessorSignature,
+ IN UINT32 ProcessorFlags,
+ IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,
+ IN UINTN MicrocodeCpuIdCount
)
{
- UINTN Index;
+ UINTN Index;
if (MicrocodeCpuIdCount == 0) {
return TRUE;
@@ -133,7 +134,8 @@ IsProcessorMatchedMicrocode ( for (Index = 0; Index < MicrocodeCpuIdCount; Index++) {
if ((ProcessorSignature == MicrocodeCpuId[Index].ProcessorSignature) &&
- (ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0) {
+ ((ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0))
+ {
return TRUE;
}
}
@@ -182,22 +184,22 @@ IsProcessorMatchedMicrocode ( BOOLEAN
EFIAPI
IsValidMicrocode (
- IN CPU_MICROCODE_HEADER *Microcode,
- IN UINTN MicrocodeLength,
- IN UINT32 MinimumRevision,
- IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds,
- IN UINTN MicrocodeCpuIdCount,
- IN BOOLEAN VerifyChecksum
+ IN CPU_MICROCODE_HEADER *Microcode,
+ IN UINTN MicrocodeLength,
+ IN UINT32 MinimumRevision,
+ IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds,
+ IN UINTN MicrocodeCpuIdCount,
+ IN BOOLEAN VerifyChecksum
)
{
- UINTN Index;
- UINT32 DataSize;
- UINT32 TotalSize;
- CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable;
- CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader;
- UINT32 ExtendedTableLength;
- UINT32 Sum32;
- BOOLEAN Match;
+ UINTN Index;
+ UINT32 DataSize;
+ UINT32 TotalSize;
+ CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable;
+ CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader;
+ UINT32 ExtendedTableLength;
+ UINT32 Sum32;
+ BOOLEAN Match;
ASSERT (Microcode != NULL);
@@ -206,7 +208,7 @@ IsValidMicrocode ( // the input microcode buffer is so small that even cannot contain the header.
// the input microcode buffer is so large that exceeds MAX_ADDRESS.
//
- if ((MicrocodeLength < sizeof (CPU_MICROCODE_HEADER)) || (MicrocodeLength > (MAX_ADDRESS - (UINTN) Microcode))) {
+ if ((MicrocodeLength < sizeof (CPU_MICROCODE_HEADER)) || (MicrocodeLength > (MAX_ADDRESS - (UINTN)Microcode))) {
return FALSE;
}
@@ -249,7 +251,7 @@ IsValidMicrocode ( //
// The summation of all DWORDs in microcode should be zero.
//
- if (VerifyChecksum && (CalculateSum32 ((UINT32 *) Microcode, TotalSize) != 0)) {
+ if (VerifyChecksum && (CalculateSum32 ((UINT32 *)Microcode, TotalSize) != 0)) {
return FALSE;
}
@@ -272,29 +274,34 @@ IsValidMicrocode ( if ((ExtendedTableLength < sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) || ((ExtendedTableLength % 4) != 0)) {
return FALSE;
}
+
//
// Extended Table exist, check if the CPU in support list
//
- ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINTN) (Microcode + 1) + DataSize);
+ ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *)((UINTN)(Microcode + 1) + DataSize);
if (ExtendedTableHeader->ExtendedSignatureCount > MAX_UINT32 / sizeof (CPU_MICROCODE_EXTENDED_TABLE)) {
return FALSE;
}
+
if (ExtendedTableHeader->ExtendedSignatureCount * sizeof (CPU_MICROCODE_EXTENDED_TABLE)
- > ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) {
+ > ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER))
+ {
return FALSE;
}
+
//
// Check the extended table checksum
//
- if (VerifyChecksum && (CalculateSum32 ((UINT32 *) ExtendedTableHeader, ExtendedTableLength) != 0)) {
+ if (VerifyChecksum && (CalculateSum32 ((UINT32 *)ExtendedTableHeader, ExtendedTableLength) != 0)) {
return FALSE;
}
- ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTableHeader + 1);
- for (Index = 0; Index < ExtendedTableHeader->ExtendedSignatureCount; Index ++) {
+ ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *)(ExtendedTableHeader + 1);
+ for (Index = 0; Index < ExtendedTableHeader->ExtendedSignatureCount; Index++) {
if (VerifyChecksum &&
(ExtendedTable[Index].ProcessorSignature.Uint32 + ExtendedTable[Index].ProcessorFlag
- + ExtendedTable[Index].Checksum != Sum32)) {
+ + ExtendedTable[Index].Checksum != Sum32))
+ {
//
// The extended table entry is valid when the summation of Processor Signature, Processor Flags
// and Checksum equal to the coresponding summation from primary header. Because:
@@ -308,6 +315,7 @@ IsValidMicrocode ( //
continue;
}
+
Match = IsProcessorMatchedMicrocode (
ExtendedTable[Index].ProcessorSignature.Uint32,
ExtendedTable[Index].ProcessorFlag,
@@ -318,5 +326,6 @@ IsValidMicrocode ( return TRUE;
}
}
+
return FALSE;
}
diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c index 93fc63bf93..9d9206d209 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -18,21 +18,21 @@ #include <Protocol/Timer.h>
-#define AP_SAFE_STACK_SIZE 128
+#define AP_SAFE_STACK_SIZE 128
-CPU_MP_DATA *mCpuMpData = NULL;
-EFI_EVENT mCheckAllApsEvent = NULL;
-EFI_EVENT mMpInitExitBootServicesEvent = NULL;
-EFI_EVENT mLegacyBootEvent = NULL;
-volatile BOOLEAN mStopCheckAllApsStatus = TRUE;
-VOID *mReservedApLoopFunc = NULL;
-UINTN mReservedTopOfApStack;
-volatile UINT32 mNumberToFinish = 0;
+CPU_MP_DATA *mCpuMpData = NULL;
+EFI_EVENT mCheckAllApsEvent = NULL;
+EFI_EVENT mMpInitExitBootServicesEvent = NULL;
+EFI_EVENT mLegacyBootEvent = NULL;
+volatile BOOLEAN mStopCheckAllApsStatus = TRUE;
+VOID *mReservedApLoopFunc = NULL;
+UINTN mReservedTopOfApStack;
+volatile UINT32 mNumberToFinish = 0;
//
// Begin wakeup buffer allocation below 0x88000
//
-STATIC EFI_PHYSICAL_ADDRESS mSevEsDxeWakeupBuffer = 0x88000;
+STATIC EFI_PHYSICAL_ADDRESS mSevEsDxeWakeupBuffer = 0x88000;
/**
Enable Debug Agent to support source debugging on AP function.
@@ -70,7 +70,7 @@ GetCpuMpData ( **/
VOID
SaveCpuMpData (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
)
{
mCpuMpData = CpuMpData;
@@ -86,12 +86,12 @@ SaveCpuMpData ( **/
UINTN
GetWakeupBuffer (
- IN UINTN WakeupBufferSize
+ IN UINTN WakeupBufferSize
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS StartAddress;
- EFI_MEMORY_TYPE MemoryType;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS StartAddress;
+ EFI_MEMORY_TYPE MemoryType;
if (PcdGetBool (PcdSevEsIsEnabled)) {
MemoryType = EfiReservedMemoryType;
@@ -115,6 +115,7 @@ GetWakeupBuffer ( } else {
StartAddress = 0x88000;
}
+
Status = gBS->AllocatePages (
AllocateMaxAddress,
MemoryType,
@@ -123,7 +124,7 @@ GetWakeupBuffer ( );
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) {
- StartAddress = (EFI_PHYSICAL_ADDRESS) -1;
+ StartAddress = (EFI_PHYSICAL_ADDRESS)-1;
} else if (PcdGetBool (PcdSevEsIsEnabled)) {
//
// Next SEV-ES wakeup buffer allocation must be below this allocation
@@ -131,10 +132,14 @@ GetWakeupBuffer ( mSevEsDxeWakeupBuffer = StartAddress;
}
- DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
- (UINTN) StartAddress, WakeupBufferSize));
+ DEBUG ((
+ DEBUG_INFO,
+ "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
+ (UINTN)StartAddress,
+ WakeupBufferSize
+ ));
- return (UINTN) StartAddress;
+ return (UINTN)StartAddress;
}
/**
@@ -151,19 +156,19 @@ GetWakeupBuffer ( **/
UINTN
GetModeTransitionBuffer (
- IN UINTN BufferSize
+ IN UINTN BufferSize
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS StartAddress;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS StartAddress;
StartAddress = BASE_4GB - 1;
- Status = gBS->AllocatePages (
- AllocateMaxAddress,
- EfiBootServicesCode,
- EFI_SIZE_TO_PAGES (BufferSize),
- &StartAddress
- );
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiBootServicesCode,
+ EFI_SIZE_TO_PAGES (BufferSize),
+ &StartAddress
+ );
if (EFI_ERROR (Status)) {
StartAddress = 0;
}
@@ -194,27 +199,27 @@ GetSevEsAPMemory ( // Allocate 1 page for AP jump table page
//
StartAddress = BASE_4GB - 1;
- Status = gBS->AllocatePages (
- AllocateMaxAddress,
- EfiReservedMemoryType,
- 1,
- &StartAddress
- );
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiReservedMemoryType,
+ 1,
+ &StartAddress
+ );
ASSERT_EFI_ERROR (Status);
- DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory = %lx\n", (UINTN) StartAddress));
+ DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory = %lx\n", (UINTN)StartAddress));
//
// Save the SevEsAPMemory as the AP jump table.
//
Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
- Ghcb = Msr.Ghcb;
+ Ghcb = Msr.Ghcb;
VmgInit (Ghcb, &InterruptState);
- VmgExit (Ghcb, SVM_EXIT_AP_JUMP_TABLE, 0, (UINT64) (UINTN) StartAddress);
+ VmgExit (Ghcb, SVM_EXIT_AP_JUMP_TABLE, 0, (UINT64)(UINTN)StartAddress);
VmgDone (Ghcb, InterruptState);
- return (UINTN) StartAddress;
+ return (UINTN)StartAddress;
}
/**
@@ -226,9 +231,9 @@ CheckAndUpdateApsStatus ( VOID
)
{
- UINTN ProcessorNumber;
- EFI_STATUS Status;
- CPU_MP_DATA *CpuMpData;
+ UINTN ProcessorNumber;
+ EFI_STATUS Status;
+ CPU_MP_DATA *CpuMpData;
CpuMpData = GetCpuMpData ();
@@ -236,13 +241,12 @@ CheckAndUpdateApsStatus ( // First, check whether pending StartupAllAPs() exists.
//
if (CpuMpData->WaitEvent != NULL) {
-
Status = CheckAllAPs ();
//
// If all APs finish for StartupAllAPs(), signal the WaitEvent for it.
//
if (Status != EFI_NOT_READY) {
- Status = gBS->SignalEvent (CpuMpData->WaitEvent);
+ Status = gBS->SignalEvent (CpuMpData->WaitEvent);
CpuMpData->WaitEvent = NULL;
}
}
@@ -251,7 +255,6 @@ CheckAndUpdateApsStatus ( // Second, check whether pending StartupThisAPs() callings exist.
//
for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) {
-
if (CpuMpData->CpuData[ProcessorNumber].WaitEvent == NULL) {
continue;
}
@@ -260,7 +263,7 @@ CheckAndUpdateApsStatus ( if (Status != EFI_NOT_READY) {
gBS->SignalEvent (CpuMpData->CpuData[ProcessorNumber].WaitEvent);
- CpuMpData->CpuData[ProcessorNumber].WaitEvent = NULL;
+ CpuMpData->CpuData[ProcessorNumber].WaitEvent = NULL;
}
}
}
@@ -279,8 +282,8 @@ CheckAndUpdateApsStatus ( VOID
EFIAPI
CheckApsStatus (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
//
@@ -307,18 +310,20 @@ GetProtectedMode16CS ( UINTN GdtEntryCount;
UINT16 Index;
- Index = (UINT16) -1;
+ Index = (UINT16)-1;
AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
- GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;
+ GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) {
- if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 0) {
+ if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 0)) {
break;
}
}
+
GdtEntry++;
}
+
ASSERT (Index != GdtEntryCount);
return Index * 8;
}
@@ -340,15 +345,17 @@ GetProtectedModeCS ( AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
- GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;
+ GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) {
- if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) {
+ if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) {
break;
}
}
+
GdtEntry++;
}
+
ASSERT (Index != GdtEntryCount);
return Index * 8;
}
@@ -364,11 +371,11 @@ RelocateApLoop ( IN OUT VOID *Buffer
)
{
- CPU_MP_DATA *CpuMpData;
- BOOLEAN MwaitSupport;
- ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc;
- UINTN ProcessorNumber;
- UINTN StackStart;
+ CPU_MP_DATA *CpuMpData;
+ BOOLEAN MwaitSupport;
+ ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc;
+ UINTN ProcessorNumber;
+ UINTN StackStart;
MpInitLibWhoAmI (&ProcessorNumber);
CpuMpData = GetCpuMpData ();
@@ -378,13 +385,14 @@ RelocateApLoop ( } else {
StackStart = mReservedTopOfApStack;
}
- AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP) (UINTN) mReservedApLoopFunc;
+
+ AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoopFunc;
AsmRelocateApLoopFunc (
MwaitSupport,
CpuMpData->ApTargetCState,
CpuMpData->PmCodeSegment,
StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE,
- (UINTN) &mNumberToFinish,
+ (UINTN)&mNumberToFinish,
CpuMpData->Pm16CodeSegment,
CpuMpData->SevEsAPBuffer,
CpuMpData->WakeupBuffer
@@ -406,32 +414,32 @@ RelocateApLoop ( VOID
EFIAPI
MpInitChangeApLoopCallback (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- CPU_MP_DATA *CpuMpData;
+ CPU_MP_DATA *CpuMpData;
- CpuMpData = GetCpuMpData ();
- CpuMpData->PmCodeSegment = GetProtectedModeCS ();
+ CpuMpData = GetCpuMpData ();
+ CpuMpData->PmCodeSegment = GetProtectedModeCS ();
CpuMpData->Pm16CodeSegment = GetProtectedMode16CS ();
- CpuMpData->ApLoopMode = PcdGet8 (PcdCpuApLoopMode);
- mNumberToFinish = CpuMpData->CpuCount - 1;
+ CpuMpData->ApLoopMode = PcdGet8 (PcdCpuApLoopMode);
+ mNumberToFinish = CpuMpData->CpuCount - 1;
WakeUpAP (CpuMpData, TRUE, 0, RelocateApLoop, NULL, TRUE);
while (mNumberToFinish > 0) {
CpuPause ();
}
- if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer != (UINTN) -1)) {
+ if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer != (UINTN)-1)) {
//
// There are APs present. Re-use reserved memory area below 1MB from
// WakeupBuffer as the area to be used for transitioning to 16-bit mode
// in support of booting of the AP by an OS.
//
CopyMem (
- (VOID *) CpuMpData->WakeupBuffer,
- (VOID *) (CpuMpData->AddressMap.RendezvousFunnelAddress +
- CpuMpData->AddressMap.SwitchToRealPM16ModeOffset),
+ (VOID *)CpuMpData->WakeupBuffer,
+ (VOID *)(CpuMpData->AddressMap.RendezvousFunnelAddress +
+ CpuMpData->AddressMap.SwitchToRealPM16ModeOffset),
CpuMpData->AddressMap.SwitchToRealPM16ModeSize
);
}
@@ -446,16 +454,16 @@ MpInitChangeApLoopCallback ( **/
VOID
InitMpGlobalData (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS Address;
- UINTN ApSafeBufferSize;
- UINTN Index;
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemDesc;
- UINTN StackBase;
- CPU_INFO_IN_HOB *CpuInfoInHob;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS Address;
+ UINTN ApSafeBufferSize;
+ UINTN Index;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemDesc;
+ UINTN StackBase;
+ CPU_INFO_IN_HOB *CpuInfoInHob;
SaveCpuMpData (CpuMpData);
@@ -485,7 +493,7 @@ InitMpGlobalData ( //
CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
for (Index = 0; Index < CpuMpData->CpuCount; ++Index) {
- if (CpuInfoInHob != NULL && CpuInfoInHob[Index].ApTopOfStack != 0) {
+ if ((CpuInfoInHob != NULL) && (CpuInfoInHob[Index].ApTopOfStack != 0)) {
StackBase = (UINTN)CpuInfoInHob[Index].ApTopOfStack - CpuMpData->CpuApStackSize;
} else {
StackBase = CpuMpData->Buffer + Index * CpuMpData->CpuApStackSize;
@@ -501,8 +509,12 @@ InitMpGlobalData ( );
ASSERT_EFI_ERROR (Status);
- DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n",
- (UINT64)StackBase, (UINT64)Index));
+ DEBUG ((
+ DEBUG_INFO,
+ "Stack Guard set at %lx [cpu%lu]!\n",
+ (UINT64)StackBase,
+ (UINT64)Index
+ ));
}
}
@@ -514,9 +526,11 @@ InitMpGlobalData ( // Allocating it in advance since memory services are not available in
// Exit Boot Services callback function.
//
- ApSafeBufferSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (
- CpuMpData->AddressMap.RelocateApLoopFuncSize
- ));
+ ApSafeBufferSize = EFI_PAGES_TO_SIZE (
+ EFI_SIZE_TO_PAGES (
+ CpuMpData->AddressMap.RelocateApLoopFuncSize
+ )
+ );
Address = BASE_4GB - 1;
Status = gBS->AllocatePages (
AllocateMaxAddress,
@@ -526,7 +540,7 @@ InitMpGlobalData ( );
ASSERT_EFI_ERROR (Status);
- mReservedApLoopFunc = (VOID *) (UINTN) Address;
+ mReservedApLoopFunc = (VOID *)(UINTN)Address;
ASSERT (mReservedApLoopFunc != NULL);
//
@@ -545,9 +559,11 @@ InitMpGlobalData ( );
}
- ApSafeBufferSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (
- CpuMpData->CpuCount * AP_SAFE_STACK_SIZE
- ));
+ ApSafeBufferSize = EFI_PAGES_TO_SIZE (
+ EFI_SIZE_TO_PAGES (
+ CpuMpData->CpuCount * AP_SAFE_STACK_SIZE
+ )
+ );
Address = BASE_4GB - 1;
Status = gBS->AllocatePages (
AllocateMaxAddress,
@@ -557,7 +573,7 @@ InitMpGlobalData ( );
ASSERT_EFI_ERROR (Status);
- mReservedTopOfApStack = (UINTN) Address + ApSafeBufferSize;
+ mReservedTopOfApStack = (UINTN)Address + ApSafeBufferSize;
ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) == 0);
CopyMem (
mReservedApLoopFunc,
@@ -684,15 +700,15 @@ InitMpGlobalData ( EFI_STATUS
EFIAPI
MpInitLibStartupAllAPs (
- IN EFI_AP_PROCEDURE Procedure,
- IN BOOLEAN SingleThread,
- IN EFI_EVENT WaitEvent OPTIONAL,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL,
- OUT UINTN **FailedCpuList OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN BOOLEAN SingleThread,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT UINTN **FailedCpuList OPTIONAL
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Temporarily stop checkAllApsStatus for avoid resource dead-lock.
@@ -791,15 +807,15 @@ MpInitLibStartupAllAPs ( EFI_STATUS
EFIAPI
MpInitLibStartupThisAP (
- IN EFI_AP_PROCEDURE Procedure,
- IN UINTN ProcessorNumber,
- IN EFI_EVENT WaitEvent OPTIONAL,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL,
- OUT BOOLEAN *Finished OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN ProcessorNumber,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT BOOLEAN *Finished OPTIONAL
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// temporarily stop checkAllApsStatus for avoid resource dead-lock.
@@ -849,19 +865,19 @@ MpInitLibStartupThisAP ( EFI_STATUS
EFIAPI
MpInitLibSwitchBSP (
- IN UINTN ProcessorNumber,
- IN BOOLEAN EnableOldBSP
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableOldBSP
)
{
- EFI_STATUS Status;
- EFI_TIMER_ARCH_PROTOCOL *Timer;
- UINT64 TimerPeriod;
+ EFI_STATUS Status;
+ EFI_TIMER_ARCH_PROTOCOL *Timer;
+ UINT64 TimerPeriod;
TimerPeriod = 0;
//
// Locate Timer Arch Protocol
//
- Status = gBS->LocateProtocol (&gEfiTimerArchProtocolGuid, NULL, (VOID **) &Timer);
+ Status = gBS->LocateProtocol (&gEfiTimerArchProtocolGuid, NULL, (VOID **)&Timer);
if (EFI_ERROR (Status)) {
Timer = NULL;
}
@@ -922,13 +938,13 @@ MpInitLibSwitchBSP ( EFI_STATUS
EFIAPI
MpInitLibEnableDisableAP (
- IN UINTN ProcessorNumber,
- IN BOOLEAN EnableAP,
- IN UINT32 *HealthFlag OPTIONAL
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableAP,
+ IN UINT32 *HealthFlag OPTIONAL
)
{
- EFI_STATUS Status;
- BOOLEAN TempStopCheckState;
+ EFI_STATUS Status;
+ BOOLEAN TempStopCheckState;
TempStopCheckState = FALSE;
//
@@ -961,7 +977,7 @@ MpInitLibEnableDisableAP ( **/
EFI_STATUS
PlatformShadowMicrocode (
- IN OUT CPU_MP_DATA *CpuMpData
+ IN OUT CPU_MP_DATA *CpuMpData
)
{
//
diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/MpInitLib/Microcode.c index 105a9f84bf..f9f070fa8b 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -18,17 +18,17 @@ **/
VOID
MicrocodeDetect (
- IN CPU_MP_DATA *CpuMpData,
- IN UINTN ProcessorNumber
+ IN CPU_MP_DATA *CpuMpData,
+ IN UINTN ProcessorNumber
)
{
- CPU_MICROCODE_HEADER *Microcode;
- UINTN MicrocodeEnd;
- CPU_AP_DATA *BspData;
- UINT32 LatestRevision;
- CPU_MICROCODE_HEADER *LatestMicrocode;
- UINT32 ThreadId;
- EDKII_PEI_MICROCODE_CPU_ID MicrocodeCpuId;
+ CPU_MICROCODE_HEADER *Microcode;
+ UINTN MicrocodeEnd;
+ CPU_AP_DATA *BspData;
+ UINT32 LatestRevision;
+ CPU_MICROCODE_HEADER *LatestMicrocode;
+ UINT32 ThreadId;
+ EDKII_PEI_MICROCODE_CPU_ID MicrocodeCpuId;
if (CpuMpData->MicrocodePatchRegionSize == 0) {
//
@@ -47,7 +47,7 @@ MicrocodeDetect ( GetProcessorMicrocodeCpuId (&MicrocodeCpuId);
- if (ProcessorNumber != (UINTN) CpuMpData->BspNumber) {
+ if (ProcessorNumber != (UINTN)CpuMpData->BspNumber) {
//
// Direct use microcode of BSP if AP is the same as BSP.
// Assume BSP calls this routine() before AP.
@@ -55,8 +55,9 @@ MicrocodeDetect ( BspData = &(CpuMpData->CpuData[CpuMpData->BspNumber]);
if ((BspData->ProcessorSignature == MicrocodeCpuId.ProcessorSignature) &&
(BspData->PlatformId == MicrocodeCpuId.PlatformId) &&
- (BspData->MicrocodeEntryAddr != 0)) {
- LatestMicrocode = (CPU_MICROCODE_HEADER *)(UINTN) BspData->MicrocodeEntryAddr;
+ (BspData->MicrocodeEntryAddr != 0))
+ {
+ LatestMicrocode = (CPU_MICROCODE_HEADER *)(UINTN)BspData->MicrocodeEntryAddr;
LatestRevision = LatestMicrocode->UpdateRevision;
goto LoadMicrocode;
}
@@ -69,11 +70,11 @@ MicrocodeDetect ( //
LatestRevision = 0;
LatestMicrocode = NULL;
- Microcode = (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->MicrocodePatchAddress;
- MicrocodeEnd = (UINTN) Microcode + (UINTN) CpuMpData->MicrocodePatchRegionSize;
+ Microcode = (CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->MicrocodePatchAddress;
+ MicrocodeEnd = (UINTN)Microcode + (UINTN)CpuMpData->MicrocodePatchRegionSize;
do {
- if (!IsValidMicrocode (Microcode, MicrocodeEnd - (UINTN) Microcode, LatestRevision, &MicrocodeCpuId, 1, TRUE)) {
+ if (!IsValidMicrocode (Microcode, MicrocodeEnd - (UINTN)Microcode, LatestRevision, &MicrocodeCpuId, 1, TRUE)) {
//
// It is the padding data between the microcode patches for microcode patches alignment.
// Because the microcode patch is the multiple of 1-KByte, the padding data should not
@@ -81,14 +82,15 @@ MicrocodeDetect ( // alignment value should be larger than 1-KByte. We could skip SIZE_1KB padding data to
// find the next possible microcode patch header.
//
- Microcode = (CPU_MICROCODE_HEADER *) ((UINTN) Microcode + SIZE_1KB);
+ Microcode = (CPU_MICROCODE_HEADER *)((UINTN)Microcode + SIZE_1KB);
continue;
}
+
LatestMicrocode = Microcode;
LatestRevision = LatestMicrocode->UpdateRevision;
- Microcode = (CPU_MICROCODE_HEADER *) (((UINTN) Microcode) + GetMicrocodeLength (Microcode));
- } while ((UINTN) Microcode < MicrocodeEnd);
+ Microcode = (CPU_MICROCODE_HEADER *)(((UINTN)Microcode) + GetMicrocodeLength (Microcode));
+ } while ((UINTN)Microcode < MicrocodeEnd);
LoadMicrocode:
if (LatestRevision != 0) {
@@ -97,7 +99,7 @@ LoadMicrocode: // patch header) for each processor even it's the same as the loaded one.
// It will be used when building the microcode patch cache HOB.
//
- CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr = (UINTN) LatestMicrocode;
+ CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr = (UINTN)LatestMicrocode;
}
if (LatestRevision > GetProcessorMicrocodeSignature ()) {
@@ -109,6 +111,7 @@ LoadMicrocode: //
LoadMicrocode (LatestMicrocode);
}
+
//
// It's possible that the microcode fails to load. Just capture the CPU microcode revision after loading.
//
@@ -129,15 +132,15 @@ LoadMicrocode: **/
VOID
ShadowMicrocodePatchWorker (
- IN OUT CPU_MP_DATA *CpuMpData,
- IN MICROCODE_PATCH_INFO *Patches,
- IN UINTN PatchCount,
- IN UINTN TotalLoadSize
+ IN OUT CPU_MP_DATA *CpuMpData,
+ IN MICROCODE_PATCH_INFO *Patches,
+ IN UINTN PatchCount,
+ IN UINTN TotalLoadSize
)
{
- UINTN Index;
- VOID *MicrocodePatchInRam;
- UINT8 *Walker;
+ UINTN Index;
+ VOID *MicrocodePatchInRam;
+ UINT8 *Walker;
ASSERT ((Patches != NULL) && (PatchCount != 0));
@@ -152,7 +155,7 @@ ShadowMicrocodePatchWorker ( for (Walker = MicrocodePatchInRam, Index = 0; Index < PatchCount; Index++) {
CopyMem (
Walker,
- (VOID *) Patches[Index].Address,
+ (VOID *)Patches[Index].Address,
Patches[Index].Size
);
Walker += Patches[Index].Size;
@@ -161,13 +164,15 @@ ShadowMicrocodePatchWorker ( //
// Update the microcode patch related fields in CpuMpData
//
- CpuMpData->MicrocodePatchAddress = (UINTN) MicrocodePatchInRam;
+ CpuMpData->MicrocodePatchAddress = (UINTN)MicrocodePatchInRam;
CpuMpData->MicrocodePatchRegionSize = TotalLoadSize;
DEBUG ((
DEBUG_INFO,
"%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n",
- __FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize
+ __FUNCTION__,
+ CpuMpData->MicrocodePatchAddress,
+ CpuMpData->MicrocodePatchRegionSize
));
return;
@@ -181,19 +186,19 @@ ShadowMicrocodePatchWorker ( **/
VOID
ShadowMicrocodePatchByPcd (
- IN OUT CPU_MP_DATA *CpuMpData
+ IN OUT CPU_MP_DATA *CpuMpData
)
{
- UINTN Index;
- CPU_MICROCODE_HEADER *MicrocodeEntryPoint;
- UINTN MicrocodeEnd;
- UINTN TotalSize;
- MICROCODE_PATCH_INFO *PatchInfoBuffer;
- UINTN MaxPatchNumber;
- UINTN PatchCount;
- UINTN TotalLoadSize;
- EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds;
- BOOLEAN Valid;
+ UINTN Index;
+ CPU_MICROCODE_HEADER *MicrocodeEntryPoint;
+ UINTN MicrocodeEnd;
+ UINTN TotalSize;
+ MICROCODE_PATCH_INFO *PatchInfoBuffer;
+ UINTN MaxPatchNumber;
+ UINTN PatchCount;
+ UINTN TotalLoadSize;
+ EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds;
+ BOOLEAN Valid;
//
// Initialize the microcode patch related fields in CpuMpData as the values
@@ -203,10 +208,10 @@ ShadowMicrocodePatchByPcd ( CpuMpData->MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress);
CpuMpData->MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize);
- MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->MicrocodePatchAddress;
- MicrocodeEnd = (UINTN) MicrocodeEntryPoint +
- (UINTN) CpuMpData->MicrocodePatchRegionSize;
- if ((MicrocodeEntryPoint == NULL) || ((UINTN) MicrocodeEntryPoint == MicrocodeEnd)) {
+ MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->MicrocodePatchAddress;
+ MicrocodeEnd = (UINTN)MicrocodeEntryPoint +
+ (UINTN)CpuMpData->MicrocodePatchRegionSize;
+ if ((MicrocodeEntryPoint == NULL) || ((UINTN)MicrocodeEntryPoint == MicrocodeEnd)) {
//
// There is no microcode patches
//
@@ -242,7 +247,7 @@ ShadowMicrocodePatchByPcd ( do {
Valid = IsValidMicrocode (
MicrocodeEntryPoint,
- MicrocodeEnd - (UINTN) MicrocodeEntryPoint,
+ MicrocodeEnd - (UINTN)MicrocodeEntryPoint,
0,
MicrocodeCpuIds,
CpuMpData->CpuCount,
@@ -252,7 +257,7 @@ ShadowMicrocodePatchByPcd ( //
// Padding data between the microcode patches, skip 1KB to check next entry.
//
- MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEntryPoint) + SIZE_1KB);
+ MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)(((UINTN)MicrocodeEntryPoint) + SIZE_1KB);
continue;
}
@@ -277,6 +282,7 @@ ShadowMicrocodePatchByPcd ( if (PatchInfoBuffer == NULL) {
goto OnExit;
}
+
MaxPatchNumber = MaxPatchNumber * 2;
}
@@ -285,21 +291,23 @@ ShadowMicrocodePatchByPcd ( //
// Store the information of this microcode patch
//
- PatchInfoBuffer[PatchCount - 1].Address = (UINTN) MicrocodeEntryPoint;
+ PatchInfoBuffer[PatchCount - 1].Address = (UINTN)MicrocodeEntryPoint;
PatchInfoBuffer[PatchCount - 1].Size = TotalSize;
- TotalLoadSize += TotalSize;
+ TotalLoadSize += TotalSize;
//
// Process the next microcode patch
//
- MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) ((UINTN) MicrocodeEntryPoint + TotalSize);
- } while ((UINTN) MicrocodeEntryPoint < MicrocodeEnd);
+ MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)((UINTN)MicrocodeEntryPoint + TotalSize);
+ } while ((UINTN)MicrocodeEntryPoint < MicrocodeEnd);
if (PatchCount != 0) {
DEBUG ((
DEBUG_INFO,
"%a: 0x%x microcode patches will be loaded into memory, with size 0x%x.\n",
- __FUNCTION__, PatchCount, TotalLoadSize
+ __FUNCTION__,
+ PatchCount,
+ TotalLoadSize
));
ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, TotalLoadSize);
@@ -309,6 +317,7 @@ OnExit: if (PatchInfoBuffer != NULL) {
FreePool (PatchInfoBuffer);
}
+
FreePages (MicrocodeCpuIds, EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * sizeof (EDKII_PEI_MICROCODE_CPU_ID)));
}
@@ -319,10 +328,10 @@ OnExit: **/
VOID
ShadowMicrocodeUpdatePatch (
- IN OUT CPU_MP_DATA *CpuMpData
+ IN OUT CPU_MP_DATA *CpuMpData
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = PlatformShadowMicrocode (CpuMpData);
if (EFI_ERROR (Status)) {
@@ -347,16 +356,16 @@ ShadowMicrocodeUpdatePatch ( **/
BOOLEAN
GetMicrocodePatchInfoFromHob (
- UINT64 *Address,
- UINT64 *RegionSize
+ UINT64 *Address,
+ UINT64 *RegionSize
)
{
- EFI_HOB_GUID_TYPE *GuidHob;
- EDKII_MICROCODE_PATCH_HOB *MicrocodePathHob;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EDKII_MICROCODE_PATCH_HOB *MicrocodePathHob;
GuidHob = GetFirstGuidHob (&gEdkiiMicrocodePatchHobGuid);
if (GuidHob == NULL) {
- DEBUG((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __FUNCTION__));
return FALSE;
}
@@ -365,9 +374,12 @@ GetMicrocodePatchInfoFromHob ( *Address = MicrocodePathHob->MicrocodePatchAddress;
*RegionSize = MicrocodePathHob->MicrocodePatchRegionSize;
- DEBUG((
- DEBUG_INFO, "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n",
- __FUNCTION__, *Address, *RegionSize
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n",
+ __FUNCTION__,
+ *Address,
+ *RegionSize
));
return TRUE;
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index b390c558d4..2d8e9512ab 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -13,8 +13,7 @@ #include <Register/Amd/Fam17Msr.h>
#include <Register/Amd/Ghcb.h>
-EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;
-
+EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;
/**
The function will check if BSP Execute Disable is enabled.
@@ -38,7 +37,7 @@ IsBspExecuteDisableEnabled ( BOOLEAN Enabled;
IA32_CR0 Cr0;
- Enabled = FALSE;
+ Enabled = FALSE;
Cr0.UintN = AsmReadCr0 ();
if (Cr0.Bits.PG != 0) {
//
@@ -78,12 +77,12 @@ IsBspExecuteDisableEnabled ( VOID
EFIAPI
FutureBSPProc (
- IN VOID *Buffer
+ IN VOID *Buffer
)
{
- CPU_MP_DATA *DataInHob;
+ CPU_MP_DATA *DataInHob;
- DataInHob = (CPU_MP_DATA *) Buffer;
+ DataInHob = (CPU_MP_DATA *)Buffer;
AsmExchangeRole (&DataInHob->APInfo, &DataInHob->BSPInfo);
}
@@ -96,7 +95,7 @@ FutureBSPProc ( **/
CPU_STATE
GetApState (
- IN CPU_AP_DATA *CpuData
+ IN CPU_AP_DATA *CpuData
)
{
return CpuData->State;
@@ -110,8 +109,8 @@ GetApState ( **/
VOID
SetApState (
- IN CPU_AP_DATA *CpuData,
- IN CPU_STATE State
+ IN CPU_AP_DATA *CpuData,
+ IN CPU_STATE State
)
{
AcquireSpinLock (&CpuData->ApLock);
@@ -126,7 +125,7 @@ SetApState ( **/
VOID
SaveLocalApicTimerSetting (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
)
{
//
@@ -148,7 +147,7 @@ SaveLocalApicTimerSetting ( **/
VOID
SyncLocalApicTimerSetting (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
)
{
//
@@ -173,10 +172,10 @@ SyncLocalApicTimerSetting ( **/
VOID
SaveVolatileRegisters (
- OUT CPU_VOLATILE_REGISTERS *VolatileRegisters
+ OUT CPU_VOLATILE_REGISTERS *VolatileRegisters
)
{
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
VolatileRegisters->Cr0 = AsmReadCr0 ();
VolatileRegisters->Cr3 = AsmReadCr3 ();
@@ -210,12 +209,12 @@ SaveVolatileRegisters ( **/
VOID
RestoreVolatileRegisters (
- IN CPU_VOLATILE_REGISTERS *VolatileRegisters,
- IN BOOLEAN IsRestoreDr
+ IN CPU_VOLATILE_REGISTERS *VolatileRegisters,
+ IN BOOLEAN IsRestoreDr
)
{
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- IA32_TSS_DESCRIPTOR *Tss;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ IA32_TSS_DESCRIPTOR *Tss;
AsmWriteCr3 (VolatileRegisters->Cr3);
AsmWriteCr4 (VolatileRegisters->Cr4);
@@ -239,8 +238,9 @@ RestoreVolatileRegisters ( AsmWriteGdtr (&VolatileRegisters->Gdtr);
AsmWriteIdtr (&VolatileRegisters->Idtr);
- if (VolatileRegisters->Tr != 0 &&
- VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) {
+ if ((VolatileRegisters->Tr != 0) &&
+ (VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit))
+ {
Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base +
VolatileRegisters->Tr);
if (Tss->Bits.P == 1) {
@@ -261,7 +261,7 @@ IsMwaitSupport ( VOID
)
{
- CPUID_VERSION_INFO_ECX VersionInfoEcx;
+ CPUID_VERSION_INFO_ECX VersionInfoEcx;
AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, &VersionInfoEcx.Uint32, NULL);
return (VersionInfoEcx.Bits.MONITOR == 1) ? TRUE : FALSE;
@@ -276,11 +276,11 @@ IsMwaitSupport ( **/
UINT8
GetApLoopMode (
- OUT UINT32 *MonitorFilterSize
+ OUT UINT32 *MonitorFilterSize
)
{
- UINT8 ApLoopMode;
- CPUID_MONITOR_MWAIT_EBX MonitorMwaitEbx;
+ UINT8 ApLoopMode;
+ CPUID_MONITOR_MWAIT_EBX MonitorMwaitEbx;
ASSERT (MonitorFilterSize != NULL);
@@ -328,20 +328,20 @@ GetApLoopMode ( **/
VOID
SortApicId (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
)
{
- UINTN Index1;
- UINTN Index2;
- UINTN Index3;
- UINT32 ApicId;
- CPU_INFO_IN_HOB CpuInfo;
- UINT32 ApCount;
- CPU_INFO_IN_HOB *CpuInfoInHob;
- volatile UINT32 *StartupApSignal;
-
- ApCount = CpuMpData->CpuCount - 1;
- CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
+ UINTN Index1;
+ UINTN Index2;
+ UINTN Index3;
+ UINT32 ApicId;
+ CPU_INFO_IN_HOB CpuInfo;
+ UINT32 ApCount;
+ CPU_INFO_IN_HOB *CpuInfoInHob;
+ volatile UINT32 *StartupApSignal;
+
+ ApCount = CpuMpData->CpuCount - 1;
+ CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
if (ApCount != 0) {
for (Index1 = 0; Index1 < ApCount; Index1++) {
Index3 = Index1;
@@ -355,6 +355,7 @@ SortApicId ( ApicId = CpuInfoInHob[Index2].ApicId;
}
}
+
if (Index3 != Index1) {
CopyMem (&CpuInfo, &CpuInfoInHob[Index3], sizeof (CPU_INFO_IN_HOB));
CopyMem (
@@ -367,7 +368,7 @@ SortApicId ( //
// Also exchange the StartupApSignal.
//
- StartupApSignal = CpuMpData->CpuData[Index3].StartupApSignal;
+ StartupApSignal = CpuMpData->CpuData[Index3].StartupApSignal;
CpuMpData->CpuData[Index3].StartupApSignal =
CpuMpData->CpuData[Index1].StartupApSignal;
CpuMpData->CpuData[Index1].StartupApSignal = StartupApSignal;
@@ -380,7 +381,7 @@ SortApicId ( ApicId = GetInitialApicId ();
for (Index1 = 0; Index1 < CpuMpData->CpuCount; Index1++) {
if (CpuInfoInHob[Index1].ApicId == ApicId) {
- CpuMpData->BspNumber = (UINT32) Index1;
+ CpuMpData->BspNumber = (UINT32)Index1;
break;
}
}
@@ -416,8 +417,8 @@ ApInitializeSync ( UINTN ProcessorNumber;
EFI_STATUS Status;
- CpuMpData = (CPU_MP_DATA *) Buffer;
- Status = GetProcessorNumber (CpuMpData, &ProcessorNumber);
+ CpuMpData = (CPU_MP_DATA *)Buffer;
+ Status = GetProcessorNumber (CpuMpData, &ProcessorNumber);
ASSERT_EFI_ERROR (Status);
//
// Load microcode on AP
@@ -440,20 +441,20 @@ ApInitializeSync ( **/
EFI_STATUS
GetProcessorNumber (
- IN CPU_MP_DATA *CpuMpData,
- OUT UINTN *ProcessorNumber
+ IN CPU_MP_DATA *CpuMpData,
+ OUT UINTN *ProcessorNumber
)
{
- UINTN TotalProcessorNumber;
- UINTN Index;
- CPU_INFO_IN_HOB *CpuInfoInHob;
- UINT32 CurrentApicId;
+ UINTN TotalProcessorNumber;
+ UINTN Index;
+ CPU_INFO_IN_HOB *CpuInfoInHob;
+ UINT32 CurrentApicId;
- CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
+ CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
TotalProcessorNumber = CpuMpData->CpuCount;
- CurrentApicId = GetApicId ();
- for (Index = 0; Index < TotalProcessorNumber; Index ++) {
+ CurrentApicId = GetApicId ();
+ for (Index = 0; Index < TotalProcessorNumber; Index++) {
if (CpuInfoInHob[Index].ApicId == CurrentApicId) {
*ProcessorNumber = Index;
return EFI_SUCCESS;
@@ -472,12 +473,12 @@ GetProcessorNumber ( **/
UINTN
CollectProcessorCount (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
)
{
- UINTN Index;
- CPU_INFO_IN_HOB *CpuInfoInHob;
- BOOLEAN X2Apic;
+ UINTN Index;
+ CPU_INFO_IN_HOB *CpuInfoInHob;
+ BOOLEAN X2Apic;
//
// Send 1st broadcast IPI to APs to wakeup APs
@@ -504,7 +505,7 @@ CollectProcessorCount ( //
X2Apic = TRUE;
} else {
- CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
+ CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
if (CpuInfoInHob[Index].InitialApicId >= 0xFF) {
X2Apic = TRUE;
@@ -525,6 +526,7 @@ CollectProcessorCount ( while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) {
CpuPause ();
}
+
//
// Enable x2APIC on BSP
//
@@ -536,6 +538,7 @@ CollectProcessorCount ( SetApState (&CpuMpData->CpuData[Index], CpuStateIdle);
}
}
+
DEBUG ((DEBUG_INFO, "APIC MODE is %d\n", GetApicMode ()));
//
// Sort BSP/Aps by CPU APIC ID in ascending order
@@ -558,16 +561,16 @@ CollectProcessorCount ( **/
VOID
InitializeApData (
- IN OUT CPU_MP_DATA *CpuMpData,
- IN UINTN ProcessorNumber,
- IN UINT32 BistData,
- IN UINT64 ApTopOfStack
+ IN OUT CPU_MP_DATA *CpuMpData,
+ IN UINTN ProcessorNumber,
+ IN UINT32 BistData,
+ IN UINT64 ApTopOfStack
)
{
- CPU_INFO_IN_HOB *CpuInfoInHob;
- MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr;
+ CPU_INFO_IN_HOB *CpuInfoInHob;
+ MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr;
- CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
+ CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId ();
CpuInfoInHob[ProcessorNumber].ApicId = GetApicId ();
CpuInfoInHob[ProcessorNumber].Health = BistData;
@@ -580,7 +583,7 @@ InitializeApData ( // NOTE: PlatformId is not relevant on AMD platforms.
//
if (!StandardSignatureIsAuthenticAMD ()) {
- PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
+ PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
CpuMpData->CpuData[ProcessorNumber].PlatformId = (UINT8)PlatformIdMsr.Bits.PlatformId;
}
@@ -592,7 +595,7 @@ InitializeApData ( NULL
);
- InitializeSpinLock(&CpuMpData->CpuData[ProcessorNumber].ApLock);
+ InitializeSpinLock (&CpuMpData->CpuData[ProcessorNumber].ApLock);
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle);
}
@@ -613,18 +616,21 @@ GetProtectedMode16CS ( UINTN GdtEntryCount;
UINT16 Index;
- Index = (UINT16) -1;
+ Index = (UINT16)-1;
AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
- GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;
+ GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) {
- if (GdtEntry->Bits.L == 0 &&
- GdtEntry->Bits.DB == 0 &&
- GdtEntry->Bits.Type > 8) {
+ if ((GdtEntry->Bits.L == 0) &&
+ (GdtEntry->Bits.DB == 0) &&
+ (GdtEntry->Bits.Type > 8))
+ {
break;
}
+
GdtEntry++;
}
+
ASSERT (Index != GdtEntryCount);
return Index * 8;
}
@@ -646,18 +652,21 @@ GetProtectedMode32CS ( UINTN GdtEntryCount;
UINT16 Index;
- Index = (UINT16) -1;
+ Index = (UINT16)-1;
AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
- GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;
+ GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) {
- if (GdtEntry->Bits.L == 0 &&
- GdtEntry->Bits.DB == 1 &&
- GdtEntry->Bits.Type > 8) {
+ if ((GdtEntry->Bits.L == 0) &&
+ (GdtEntry->Bits.DB == 1) &&
+ (GdtEntry->Bits.Type > 8))
+ {
break;
}
+
GdtEntry++;
}
+
ASSERT (Index != GdtEntryCount);
return Index * 8;
}
@@ -674,16 +683,16 @@ GetProtectedMode32CS ( STATIC
VOID
MpInitLibSevEsAPReset (
- IN GHCB *Ghcb,
- IN CPU_MP_DATA *CpuMpData
+ IN GHCB *Ghcb,
+ IN CPU_MP_DATA *CpuMpData
)
{
- EFI_STATUS Status;
- UINTN ProcessorNumber;
- UINT16 Code16, Code32;
- AP_RESET *APResetFn;
- UINTN BufferStart;
- UINTN StackStart;
+ EFI_STATUS Status;
+ UINTN ProcessorNumber;
+ UINT16 Code16, Code32;
+ AP_RESET *APResetFn;
+ UINTN BufferStart;
+ UINTN StackStart;
Status = GetProcessorNumber (CpuMpData, &ProcessorNumber);
ASSERT_EFI_ERROR (Status);
@@ -692,14 +701,14 @@ MpInitLibSevEsAPReset ( Code32 = GetProtectedMode32CS ();
if (CpuMpData->WakeupBufferHigh != 0) {
- APResetFn = (AP_RESET *) (CpuMpData->WakeupBufferHigh + CpuMpData->AddressMap.SwitchToRealNoNxOffset);
+ APResetFn = (AP_RESET *)(CpuMpData->WakeupBufferHigh + CpuMpData->AddressMap.SwitchToRealNoNxOffset);
} else {
- APResetFn = (AP_RESET *) (CpuMpData->MpCpuExchangeInfo->BufferStart + CpuMpData->AddressMap.SwitchToRealOffset);
+ APResetFn = (AP_RESET *)(CpuMpData->MpCpuExchangeInfo->BufferStart + CpuMpData->AddressMap.SwitchToRealOffset);
}
BufferStart = CpuMpData->MpCpuExchangeInfo->BufferStart;
- StackStart = CpuMpData->SevEsAPResetStackStart -
- (AP_RESET_STACK_SIZE * ProcessorNumber);
+ StackStart = CpuMpData->SevEsAPResetStackStart -
+ (AP_RESET_STACK_SIZE * ProcessorNumber);
//
// This call never returns.
@@ -716,19 +725,19 @@ MpInitLibSevEsAPReset ( VOID
EFIAPI
ApWakeupFunction (
- IN MP_CPU_EXCHANGE_INFO *ExchangeInfo,
- IN UINTN ApIndex
+ IN MP_CPU_EXCHANGE_INFO *ExchangeInfo,
+ IN UINTN ApIndex
)
{
- CPU_MP_DATA *CpuMpData;
- UINTN ProcessorNumber;
- EFI_AP_PROCEDURE Procedure;
- VOID *Parameter;
- UINT32 BistData;
- volatile UINT32 *ApStartupSignalBuffer;
- CPU_INFO_IN_HOB *CpuInfoInHob;
- UINT64 ApTopOfStack;
- UINTN CurrentApicMode;
+ CPU_MP_DATA *CpuMpData;
+ UINTN ProcessorNumber;
+ EFI_AP_PROCEDURE Procedure;
+ VOID *Parameter;
+ UINT32 BistData;
+ volatile UINT32 *ApStartupSignalBuffer;
+ CPU_INFO_IN_HOB *CpuInfoInHob;
+ UINT64 ApTopOfStack;
+ UINTN CurrentApicMode;
//
// AP finished assembly code and begin to execute C code
@@ -753,8 +762,8 @@ ApWakeupFunction ( //
// This is first time AP wakeup, get BIST information from AP stack
//
- ApTopOfStack = CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpData->CpuApStackSize;
- BistData = *(UINT32 *) ((UINTN) ApTopOfStack - sizeof (UINTN));
+ ApTopOfStack = CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpData->CpuApStackSize;
+ BistData = *(UINT32 *)((UINTN)ApTopOfStack - sizeof (UINTN));
//
// CpuMpData->CpuData[0].VolatileRegisters is initialized based on BSP environment,
// to initialize AP in InitConfig path.
@@ -773,7 +782,7 @@ ApWakeupFunction ( //
ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;
InterlockedCompareExchange32 (
- (UINT32 *) ApStartupSignalBuffer,
+ (UINT32 *)ApStartupSignalBuffer,
WAKEUP_AP_SIGNAL,
0
);
@@ -788,7 +797,7 @@ ApWakeupFunction ( // different IDT shared by all APs.
//
RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALSE);
- } else {
+ } else {
if (CpuMpData->ApLoopMode == ApInHltLoop) {
//
// Restore AP's volatile registers saved before AP is halted
@@ -806,7 +815,7 @@ ApWakeupFunction ( if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateReady) {
Procedure = (EFI_AP_PROCEDURE)CpuMpData->CpuData[ProcessorNumber].ApFunction;
- Parameter = (VOID *) CpuMpData->CpuData[ProcessorNumber].ApFunctionArgument;
+ Parameter = (VOID *)CpuMpData->CpuData[ProcessorNumber].ApFunctionArgument;
if (Procedure != NULL) {
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateBusy);
//
@@ -817,19 +826,20 @@ ApWakeupFunction ( // Invoke AP function here
//
Procedure (Parameter);
- CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
+ CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
if (CpuMpData->SwitchBspFlag) {
//
// Re-get the processor number due to BSP/AP maybe exchange in AP function
//
GetProcessorNumber (CpuMpData, &ProcessorNumber);
- CpuMpData->CpuData[ProcessorNumber].ApFunction = 0;
+ CpuMpData->CpuData[ProcessorNumber].ApFunction = 0;
CpuMpData->CpuData[ProcessorNumber].ApFunctionArgument = 0;
- ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;
- CpuInfoInHob[ProcessorNumber].ApTopOfStack = CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack;
+ ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;
+ CpuInfoInHob[ProcessorNumber].ApTopOfStack = CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack;
} else {
- if (CpuInfoInHob[ProcessorNumber].ApicId != GetApicId () ||
- CpuInfoInHob[ProcessorNumber].InitialApicId != GetInitialApicId ()) {
+ if ((CpuInfoInHob[ProcessorNumber].ApicId != GetApicId ()) ||
+ (CpuInfoInHob[ProcessorNumber].InitialApicId != GetInitialApicId ()))
+ {
if (CurrentApicMode != GetApicMode ()) {
//
// If APIC mode change happened during AP function execution,
@@ -847,6 +857,7 @@ ApWakeupFunction ( }
}
}
+
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateFinished);
}
}
@@ -861,7 +872,7 @@ ApWakeupFunction ( //
// AP finished executing C code
//
- InterlockedIncrement ((UINT32 *) &CpuMpData->FinishedCount);
+ InterlockedIncrement ((UINT32 *)&CpuMpData->FinishedCount);
if (CpuMpData->InitFlag == ApInitConfig) {
//
@@ -870,7 +881,7 @@ ApWakeupFunction ( // performs another INIT-SIPI-SIPI sequence.
//
if (!CpuMpData->SevEsIsEnabled) {
- InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting);
+ InterlockedDecrement ((UINT32 *)&CpuMpData->MpCpuExchangeInfo->NumApsExecuting);
}
}
@@ -890,11 +901,11 @@ ApWakeupFunction ( BOOLEAN DoDecrement;
BOOLEAN InterruptState;
- DoDecrement = (BOOLEAN) (CpuMpData->InitFlag == ApInitConfig);
+ DoDecrement = (BOOLEAN)(CpuMpData->InitFlag == ApInitConfig);
while (TRUE) {
Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
- Ghcb = Msr.Ghcb;
+ Ghcb = Msr.Ghcb;
VmgInit (Ghcb, &InterruptState);
@@ -905,7 +916,7 @@ ApWakeupFunction ( // Perform the delayed decrement just before issuing the first
// VMGEXIT with AP_RESET_HOLD.
//
- InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting);
+ InterlockedDecrement ((UINT32 *)&CpuMpData->MpCpuExchangeInfo->NumApsExecuting);
}
Status = VmgExit (Ghcb, SVM_EXIT_AP_RESET_HOLD, 0, 0);
@@ -928,16 +939,18 @@ ApWakeupFunction ( } else {
CpuSleep ();
}
+
CpuPause ();
}
}
+
while (TRUE) {
DisableInterrupts ();
if (CpuMpData->ApLoopMode == ApInMwaitLoop) {
//
// Place AP in MWAIT-loop
//
- AsmMonitor ((UINTN) ApStartupSignalBuffer, 0, 0);
+ AsmMonitor ((UINTN)ApStartupSignalBuffer, 0, 0);
if (*ApStartupSignalBuffer != WAKEUP_AP_SIGNAL) {
//
// Check AP start-up signal again.
@@ -973,7 +986,7 @@ ApWakeupFunction ( **/
VOID
WaitApWakeup (
- IN volatile UINT32 *ApStartupSignalBuffer
+ IN volatile UINT32 *ApStartupSignalBuffer
)
{
//
@@ -981,10 +994,11 @@ WaitApWakeup ( // Otherwise, write StartupApSignal again till AP waken up.
//
while (InterlockedCompareExchange32 (
- (UINT32 *) ApStartupSignalBuffer,
- WAKEUP_AP_SIGNAL,
- WAKEUP_AP_SIGNAL
- ) != 0) {
+ (UINT32 *)ApStartupSignalBuffer,
+ WAKEUP_AP_SIGNAL,
+ WAKEUP_AP_SIGNAL
+ ) != 0)
+ {
CpuPause ();
}
}
@@ -997,30 +1011,30 @@ WaitApWakeup ( **/
VOID
FillExchangeInfoData (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
)
{
- volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo;
- UINTN Size;
- IA32_SEGMENT_DESCRIPTOR *Selector;
- IA32_CR4 Cr4;
+ volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo;
+ UINTN Size;
+ IA32_SEGMENT_DESCRIPTOR *Selector;
+ IA32_CR4 Cr4;
- ExchangeInfo = CpuMpData->MpCpuExchangeInfo;
- ExchangeInfo->StackStart = CpuMpData->Buffer;
- ExchangeInfo->StackSize = CpuMpData->CpuApStackSize;
- ExchangeInfo->BufferStart = CpuMpData->WakeupBuffer;
- ExchangeInfo->ModeOffset = CpuMpData->AddressMap.ModeEntryOffset;
+ ExchangeInfo = CpuMpData->MpCpuExchangeInfo;
+ ExchangeInfo->StackStart = CpuMpData->Buffer;
+ ExchangeInfo->StackSize = CpuMpData->CpuApStackSize;
+ ExchangeInfo->BufferStart = CpuMpData->WakeupBuffer;
+ ExchangeInfo->ModeOffset = CpuMpData->AddressMap.ModeEntryOffset;
- ExchangeInfo->CodeSegment = AsmReadCs ();
- ExchangeInfo->DataSegment = AsmReadDs ();
+ ExchangeInfo->CodeSegment = AsmReadCs ();
+ ExchangeInfo->DataSegment = AsmReadDs ();
- ExchangeInfo->Cr3 = AsmReadCr3 ();
+ ExchangeInfo->Cr3 = AsmReadCr3 ();
- ExchangeInfo->CFunction = (UINTN) ApWakeupFunction;
+ ExchangeInfo->CFunction = (UINTN)ApWakeupFunction;
ExchangeInfo->ApIndex = 0;
ExchangeInfo->NumApsExecuting = 0;
- ExchangeInfo->InitFlag = (UINTN) CpuMpData->InitFlag;
- ExchangeInfo->CpuInfo = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
+ ExchangeInfo->InitFlag = (UINTN)CpuMpData->InitFlag;
+ ExchangeInfo->CpuInfo = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
ExchangeInfo->CpuMpData = CpuMpData;
ExchangeInfo->EnableExecuteDisable = IsBspExecuteDisableEnabled ();
@@ -1035,32 +1049,33 @@ FillExchangeInfoData ( // Using latter way is simpler because it also eliminates the needs to
// check whether platform wants to enable it.
//
- Cr4.UintN = AsmReadCr4 ();
- ExchangeInfo->Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
+ Cr4.UintN = AsmReadCr4 ();
+ ExchangeInfo->Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
DEBUG ((DEBUG_INFO, "%a: 5-Level Paging = %d\n", gEfiCallerBaseName, ExchangeInfo->Enable5LevelPaging));
- ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled;
- ExchangeInfo->GhcbBase = (UINTN) CpuMpData->GhcbBase;
+ ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled;
+ ExchangeInfo->GhcbBase = (UINTN)CpuMpData->GhcbBase;
//
// Get the BSP's data of GDT and IDT
//
- AsmReadGdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->GdtrProfile);
- AsmReadIdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->IdtrProfile);
+ AsmReadGdtr ((IA32_DESCRIPTOR *)&ExchangeInfo->GdtrProfile);
+ AsmReadIdtr ((IA32_DESCRIPTOR *)&ExchangeInfo->IdtrProfile);
//
// Find a 32-bit code segment
//
Selector = (IA32_SEGMENT_DESCRIPTOR *)ExchangeInfo->GdtrProfile.Base;
- Size = ExchangeInfo->GdtrProfile.Limit + 1;
+ Size = ExchangeInfo->GdtrProfile.Limit + 1;
while (Size > 0) {
- if (Selector->Bits.L == 0 && Selector->Bits.Type >= 8) {
+ if ((Selector->Bits.L == 0) && (Selector->Bits.Type >= 8)) {
ExchangeInfo->ModeTransitionSegment =
(UINT16)((UINTN)Selector - ExchangeInfo->GdtrProfile.Base);
break;
}
+
Selector += 1;
- Size -= sizeof (IA32_SEGMENT_DESCRIPTOR);
+ Size -= sizeof (IA32_SEGMENT_DESCRIPTOR);
}
//
@@ -1069,8 +1084,8 @@ FillExchangeInfoData ( //
if (CpuMpData->WakeupBufferHigh != 0) {
Size = CpuMpData->AddressMap.RendezvousFunnelSize +
- CpuMpData->AddressMap.SwitchToRealSize -
- CpuMpData->AddressMap.ModeTransitionOffset;
+ CpuMpData->AddressMap.SwitchToRealSize -
+ CpuMpData->AddressMap.ModeTransitionOffset;
CopyMem (
(VOID *)CpuMpData->WakeupBufferHigh,
CpuMpData->AddressMap.RendezvousFunnelAddress +
@@ -1081,12 +1096,12 @@ FillExchangeInfoData ( ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData->WakeupBufferHigh;
} else {
ExchangeInfo->ModeTransitionMemory = (UINT32)
- (ExchangeInfo->BufferStart + CpuMpData->AddressMap.ModeTransitionOffset);
+ (ExchangeInfo->BufferStart + CpuMpData->AddressMap.ModeTransitionOffset);
}
ExchangeInfo->ModeHighMemory = ExchangeInfo->ModeTransitionMemory +
- (UINT32)ExchangeInfo->ModeOffset -
- (UINT32)CpuMpData->AddressMap.ModeTransitionOffset;
+ (UINT32)ExchangeInfo->ModeOffset -
+ (UINT32)CpuMpData->AddressMap.ModeTransitionOffset;
ExchangeInfo->ModeHighSegment = (UINT16)ExchangeInfo->CodeSegment;
}
@@ -1100,9 +1115,9 @@ FillExchangeInfoData ( **/
VOID
TimedWaitForApFinish (
- IN CPU_MP_DATA *CpuMpData,
- IN UINT32 FinishedApLimit,
- IN UINT32 TimeLimit
+ IN CPU_MP_DATA *CpuMpData,
+ IN UINT32 FinishedApLimit,
+ IN UINT32 TimeLimit
);
/**
@@ -1111,20 +1126,20 @@ TimedWaitForApFinish ( @param[in] CpuMpData The pointer to CPU MP Data structure.
**/
VOID
-BackupAndPrepareWakeupBuffer(
- IN CPU_MP_DATA *CpuMpData
+BackupAndPrepareWakeupBuffer (
+ IN CPU_MP_DATA *CpuMpData
)
{
CopyMem (
- (VOID *) CpuMpData->BackupBuffer,
- (VOID *) CpuMpData->WakeupBuffer,
+ (VOID *)CpuMpData->BackupBuffer,
+ (VOID *)CpuMpData->WakeupBuffer,
CpuMpData->BackupBufferSize
);
CopyMem (
- (VOID *) CpuMpData->WakeupBuffer,
- (VOID *) CpuMpData->AddressMap.RendezvousFunnelAddress,
+ (VOID *)CpuMpData->WakeupBuffer,
+ (VOID *)CpuMpData->AddressMap.RendezvousFunnelAddress,
CpuMpData->AddressMap.RendezvousFunnelSize +
- CpuMpData->AddressMap.SwitchToRealSize
+ CpuMpData->AddressMap.SwitchToRealSize
);
}
@@ -1134,13 +1149,13 @@ BackupAndPrepareWakeupBuffer( @param[in] CpuMpData The pointer to CPU MP Data structure.
**/
VOID
-RestoreWakeupBuffer(
- IN CPU_MP_DATA *CpuMpData
+RestoreWakeupBuffer (
+ IN CPU_MP_DATA *CpuMpData
)
{
CopyMem (
- (VOID *) CpuMpData->WakeupBuffer,
- (VOID *) CpuMpData->BackupBuffer,
+ (VOID *)CpuMpData->WakeupBuffer,
+ (VOID *)CpuMpData->BackupBuffer,
CpuMpData->BackupBufferSize
);
}
@@ -1161,8 +1176,8 @@ GetApResetVectorSize ( UINTN Size;
Size = AddressMap->RendezvousFunnelSize +
- AddressMap->SwitchToRealSize +
- sizeof (MP_CPU_EXCHANGE_INFO);
+ AddressMap->SwitchToRealSize +
+ sizeof (MP_CPU_EXCHANGE_INFO);
return Size;
}
@@ -1174,21 +1189,21 @@ GetApResetVectorSize ( **/
VOID
AllocateResetVector (
- IN OUT CPU_MP_DATA *CpuMpData
+ IN OUT CPU_MP_DATA *CpuMpData
)
{
- UINTN ApResetVectorSize;
- UINTN ApResetStackSize;
+ UINTN ApResetVectorSize;
+ UINTN ApResetStackSize;
- if (CpuMpData->WakeupBuffer == (UINTN) -1) {
+ if (CpuMpData->WakeupBuffer == (UINTN)-1) {
ApResetVectorSize = GetApResetVectorSize (&CpuMpData->AddressMap);
CpuMpData->WakeupBuffer = GetWakeupBuffer (ApResetVectorSize);
- CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN)
- (CpuMpData->WakeupBuffer +
- CpuMpData->AddressMap.RendezvousFunnelSize +
- CpuMpData->AddressMap.SwitchToRealSize);
- CpuMpData->WakeupBufferHigh = GetModeTransitionBuffer (
+ CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *)(UINTN)
+ (CpuMpData->WakeupBuffer +
+ CpuMpData->AddressMap.RendezvousFunnelSize +
+ CpuMpData->AddressMap.SwitchToRealSize);
+ CpuMpData->WakeupBufferHigh = GetModeTransitionBuffer (
CpuMpData->AddressMap.RendezvousFunnelSize +
CpuMpData->AddressMap.SwitchToRealSize -
CpuMpData->AddressMap.ModeTransitionOffset
@@ -1228,6 +1243,7 @@ AllocateResetVector ( }
}
}
+
BackupAndPrepareWakeupBuffer (CpuMpData);
}
@@ -1238,7 +1254,7 @@ AllocateResetVector ( **/
VOID
FreeResetVector (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
)
{
//
@@ -1259,10 +1275,10 @@ FreeResetVector ( **/
VOID
AllocateSevEsAPMemory (
- IN OUT CPU_MP_DATA *CpuMpData
+ IN OUT CPU_MP_DATA *CpuMpData
)
{
- if (CpuMpData->SevEsAPBuffer == (UINTN) -1) {
+ if (CpuMpData->SevEsAPBuffer == (UINTN)-1) {
CpuMpData->SevEsAPBuffer =
CpuMpData->SevEsIsEnabled ? GetSevEsAPMemory () : 0;
}
@@ -1278,11 +1294,11 @@ SetSevEsJumpTable ( IN UINTN SipiVector
)
{
- SEV_ES_AP_JMP_FAR *JmpFar;
- UINT32 Offset, InsnByte;
- UINT8 LoNib, HiNib;
+ SEV_ES_AP_JMP_FAR *JmpFar;
+ UINT32 Offset, InsnByte;
+ UINT8 LoNib, HiNib;
- JmpFar = (SEV_ES_AP_JMP_FAR *) (UINTN) FixedPcdGet32 (PcdSevEsWorkAreaBase);
+ JmpFar = (SEV_ES_AP_JMP_FAR *)(UINTN)FixedPcdGet32 (PcdSevEsWorkAreaBase);
ASSERT (JmpFar != NULL);
//
@@ -1290,10 +1306,10 @@ SetSevEsJumpTable ( // This will be set to a value derived from the SIPI vector and will
// be the memory address used for the far jump below.
//
- Offset = FixedPcdGet32 (PcdSevEsWorkAreaBase);
+ Offset = FixedPcdGet32 (PcdSevEsWorkAreaBase);
Offset += sizeof (JmpFar->InsnBuffer);
- LoNib = (UINT8) Offset;
- HiNib = (UINT8) (Offset >> 8);
+ LoNib = (UINT8)Offset;
+ HiNib = (UINT8)(Offset >> 8);
//
// Program the workarea (which is the initial AP boot address) with
@@ -1302,7 +1318,7 @@ SetSevEsJumpTable ( //
// JMP FAR [CS:XXYY] => 2E FF 2E YY XX
//
- InsnByte = 0;
+ InsnByte = 0;
JmpFar->InsnBuffer[InsnByte++] = 0x2E; // CS override prefix
JmpFar->InsnBuffer[InsnByte++] = 0xFF; // JMP (FAR)
JmpFar->InsnBuffer[InsnByte++] = 0x2E; // ModRM (JMP memory location)
@@ -1313,8 +1329,8 @@ SetSevEsJumpTable ( // Program the Segment/Rip based on the SIPI vector (always at least
// 16-byte aligned, so Rip is set to 0).
//
- JmpFar->Rip = 0;
- JmpFar->Segment = (UINT16) (SipiVector >> 4);
+ JmpFar->Rip = 0;
+ JmpFar->Segment = (UINT16)(SipiVector >> 4);
}
/**
@@ -1330,25 +1346,26 @@ SetSevEsJumpTable ( **/
VOID
WakeUpAP (
- IN CPU_MP_DATA *CpuMpData,
- IN BOOLEAN Broadcast,
- IN UINTN ProcessorNumber,
- IN EFI_AP_PROCEDURE Procedure OPTIONAL,
- IN VOID *ProcedureArgument OPTIONAL,
- IN BOOLEAN WakeUpDisabledAps
+ IN CPU_MP_DATA *CpuMpData,
+ IN BOOLEAN Broadcast,
+ IN UINTN ProcessorNumber,
+ IN EFI_AP_PROCEDURE Procedure OPTIONAL,
+ IN VOID *ProcedureArgument OPTIONAL,
+ IN BOOLEAN WakeUpDisabledAps
)
{
- volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo;
- UINTN Index;
- CPU_AP_DATA *CpuData;
- BOOLEAN ResetVectorRequired;
- CPU_INFO_IN_HOB *CpuInfoInHob;
+ volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo;
+ UINTN Index;
+ CPU_AP_DATA *CpuData;
+ BOOLEAN ResetVectorRequired;
+ CPU_INFO_IN_HOB *CpuInfoInHob;
CpuMpData->FinishedCount = 0;
- ResetVectorRequired = FALSE;
+ ResetVectorRequired = FALSE;
if (CpuMpData->WakeUpByInitSipiSipi ||
- CpuMpData->InitFlag != ApInitDone) {
+ (CpuMpData->InitFlag != ApInitDone))
+ {
ResetVectorRequired = TRUE;
AllocateResetVector (CpuMpData);
AllocateSevEsAPMemory (CpuMpData);
@@ -1375,18 +1392,19 @@ WakeUpAP ( // the AP procedure will be skipped for disabled AP because AP state
// is not CpuStateReady.
//
- if (GetApState (CpuData) == CpuStateDisabled && !WakeUpDisabledAps) {
+ if ((GetApState (CpuData) == CpuStateDisabled) && !WakeUpDisabledAps) {
continue;
}
- CpuData->ApFunction = (UINTN) Procedure;
- CpuData->ApFunctionArgument = (UINTN) ProcedureArgument;
+ CpuData->ApFunction = (UINTN)Procedure;
+ CpuData->ApFunctionArgument = (UINTN)ProcedureArgument;
SetApState (CpuData, CpuStateReady);
if (CpuMpData->InitFlag != ApInitConfig) {
- *(UINT32 *) CpuData->StartupApSignal = WAKEUP_AP_SIGNAL;
+ *(UINT32 *)CpuData->StartupApSignal = WAKEUP_AP_SIGNAL;
}
}
}
+
if (ResetVectorRequired) {
//
// For SEV-ES, the initial AP boot address will be defined by
@@ -1400,8 +1418,9 @@ WakeUpAP ( //
// Wakeup all APs
//
- SendInitSipiSipiAllExcludingSelf ((UINT32) ExchangeInfo->BufferStart);
+ SendInitSipiSipiAllExcludingSelf ((UINT32)ExchangeInfo->BufferStart);
}
+
if (CpuMpData->InitFlag == ApInitConfig) {
if (PcdGet32 (PcdCpuBootLogicalProcessorNumber) > 0) {
//
@@ -1462,7 +1481,7 @@ WakeUpAP ( );
while (CpuMpData->MpCpuExchangeInfo->NumApsExecuting != 0) {
- CpuPause();
+ CpuPause ();
}
}
} else {
@@ -1477,17 +1496,17 @@ WakeUpAP ( }
}
} else {
- CpuData = &CpuMpData->CpuData[ProcessorNumber];
- CpuData->ApFunction = (UINTN) Procedure;
- CpuData->ApFunctionArgument = (UINTN) ProcedureArgument;
+ CpuData = &CpuMpData->CpuData[ProcessorNumber];
+ CpuData->ApFunction = (UINTN)Procedure;
+ CpuData->ApFunctionArgument = (UINTN)ProcedureArgument;
SetApState (CpuData, CpuStateReady);
//
// Wakeup specified AP
//
ASSERT (CpuMpData->InitFlag != ApInitConfig);
- *(UINT32 *) CpuData->StartupApSignal = WAKEUP_AP_SIGNAL;
+ *(UINT32 *)CpuData->StartupApSignal = WAKEUP_AP_SIGNAL;
if (ResetVectorRequired) {
- CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
+ CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
//
// For SEV-ES, the initial AP boot address will be defined by
@@ -1500,9 +1519,10 @@ WakeUpAP ( SendInitSipiSipi (
CpuInfoInHob[ProcessorNumber].ApicId,
- (UINT32) ExchangeInfo->BufferStart
+ (UINT32)ExchangeInfo->BufferStart
);
}
+
//
// Wait specified AP waken up
//
@@ -1542,8 +1562,8 @@ CalculateTimeout ( OUT UINT64 *CurrentTime
)
{
- UINT64 TimeoutInSeconds;
- UINT64 TimestampCounterFreq;
+ UINT64 TimeoutInSeconds;
+ UINT64 TimestampCounterFreq;
//
// Read the current value of the performance counter
@@ -1628,25 +1648,30 @@ CheckTimeout ( if (Timeout == 0) {
return FALSE;
}
+
GetPerformanceCounterProperties (&Start, &End);
Cycle = End - Start;
if (Cycle < 0) {
Cycle = -Cycle;
}
+
Cycle++;
- CurrentTime = GetPerformanceCounter();
- Delta = (INT64) (CurrentTime - *PreviousTime);
+ CurrentTime = GetPerformanceCounter ();
+ Delta = (INT64)(CurrentTime - *PreviousTime);
if (Start > End) {
Delta = -Delta;
}
+
if (Delta < 0) {
Delta += Cycle;
}
- *TotalTime += Delta;
+
+ *TotalTime += Delta;
*PreviousTime = CurrentTime;
if (*TotalTime > Timeout) {
return TRUE;
}
+
return FALSE;
}
@@ -1660,9 +1685,9 @@ CheckTimeout ( **/
VOID
TimedWaitForApFinish (
- IN CPU_MP_DATA *CpuMpData,
- IN UINT32 FinishedApLimit,
- IN UINT32 TimeLimit
+ IN CPU_MP_DATA *CpuMpData,
+ IN UINT32 FinishedApLimit,
+ IN UINT32 TimeLimit
)
{
//
@@ -1673,7 +1698,7 @@ TimedWaitForApFinish ( return;
}
- CpuMpData->TotalTime = 0;
+ CpuMpData->TotalTime = 0;
CpuMpData->ExpectedTime = CalculateTimeout (
TimeLimit,
&CpuMpData->CurrentTime
@@ -1683,7 +1708,8 @@ TimedWaitForApFinish ( &CpuMpData->CurrentTime,
&CpuMpData->TotalTime,
CpuMpData->ExpectedTime
- )) {
+ ))
+ {
CpuPause ();
}
@@ -1712,10 +1738,10 @@ TimedWaitForApFinish ( **/
VOID
ResetProcessorToIdleState (
- IN UINTN ProcessorNumber
+ IN UINTN ProcessorNumber
)
{
- CPU_MP_DATA *CpuMpData;
+ CPU_MP_DATA *CpuMpData;
CpuMpData = GetCpuMpData ();
@@ -1724,6 +1750,7 @@ ResetProcessorToIdleState ( while (CpuMpData->FinishedCount < 1) {
CpuPause ();
}
+
CpuMpData->InitFlag = ApInitDone;
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle);
@@ -1742,11 +1769,11 @@ ResetProcessorToIdleState ( **/
EFI_STATUS
GetNextWaitingProcessorNumber (
- OUT UINTN *NextProcessorNumber
+ OUT UINTN *NextProcessorNumber
)
{
- UINTN ProcessorNumber;
- CPU_MP_DATA *CpuMpData;
+ UINTN ProcessorNumber;
+ CPU_MP_DATA *CpuMpData;
CpuMpData = GetCpuMpData ();
@@ -1773,11 +1800,11 @@ GetNextWaitingProcessorNumber ( **/
EFI_STATUS
CheckThisAP (
- IN UINTN ProcessorNumber
+ IN UINTN ProcessorNumber
)
{
- CPU_MP_DATA *CpuMpData;
- CPU_AP_DATA *CpuData;
+ CPU_MP_DATA *CpuMpData;
+ CPU_AP_DATA *CpuData;
CpuMpData = GetCpuMpData ();
CpuData = &CpuMpData->CpuData[ProcessorNumber];
@@ -1790,10 +1817,11 @@ CheckThisAP ( //
// If the AP finishes for StartupThisAP(), return EFI_SUCCESS.
//
- if (GetApState(CpuData) == CpuStateFinished) {
+ if (GetApState (CpuData) == CpuStateFinished) {
if (CpuData->Finished != NULL) {
*(CpuData->Finished) = TRUE;
}
+
SetApState (CpuData, CpuStateIdle);
return EFI_SUCCESS;
} else {
@@ -1804,6 +1832,7 @@ CheckThisAP ( if (CpuData->Finished != NULL) {
*(CpuData->Finished) = FALSE;
}
+
//
// Reset failed AP to idle state
//
@@ -1812,6 +1841,7 @@ CheckThisAP ( return EFI_TIMEOUT;
}
}
+
return EFI_NOT_READY;
}
@@ -1830,12 +1860,12 @@ CheckAllAPs ( VOID
)
{
- UINTN ProcessorNumber;
- UINTN NextProcessorNumber;
- UINTN ListIndex;
- EFI_STATUS Status;
- CPU_MP_DATA *CpuMpData;
- CPU_AP_DATA *CpuData;
+ UINTN ProcessorNumber;
+ UINTN NextProcessorNumber;
+ UINTN ListIndex;
+ EFI_STATUS Status;
+ CPU_MP_DATA *CpuMpData;
+ CPU_AP_DATA *CpuData;
CpuMpData = GetCpuMpData ();
@@ -1855,10 +1885,10 @@ CheckAllAPs ( // Only BSP and corresponding AP access this unit of CPU Data. This means the AP will not modify the
// value of state after setting the it to CpuStateIdle, so BSP can safely make use of its value.
//
- if (GetApState(CpuData) == CpuStateFinished) {
- CpuMpData->RunningCount --;
+ if (GetApState (CpuData) == CpuStateFinished) {
+ CpuMpData->RunningCount--;
CpuMpData->CpuData[ProcessorNumber].Waiting = FALSE;
- SetApState(CpuData, CpuStateIdle);
+ SetApState (CpuData, CpuStateIdle);
//
// If in Single Thread mode, then search for the next waiting AP for execution.
@@ -1870,12 +1900,12 @@ CheckAllAPs ( WakeUpAP (
CpuMpData,
FALSE,
- (UINT32) NextProcessorNumber,
+ (UINT32)NextProcessorNumber,
CpuMpData->Procedure,
CpuMpData->ProcArguments,
TRUE
);
- }
+ }
}
}
}
@@ -1891,18 +1921,21 @@ CheckAllAPs ( // If timeout expires, report timeout.
//
if (CheckTimeout (
- &CpuMpData->CurrentTime,
- &CpuMpData->TotalTime,
- CpuMpData->ExpectedTime)
- ) {
+ &CpuMpData->CurrentTime,
+ &CpuMpData->TotalTime,
+ CpuMpData->ExpectedTime
+ )
+ )
+ {
//
// If FailedCpuList is not NULL, record all failed APs in it.
//
if (CpuMpData->FailedCpuList != NULL) {
*CpuMpData->FailedCpuList =
- AllocatePool ((CpuMpData->RunningCount + 1) * sizeof (UINTN));
+ AllocatePool ((CpuMpData->RunningCount + 1) * sizeof (UINTN));
ASSERT (*CpuMpData->FailedCpuList != NULL);
}
+
ListIndex = 0;
for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) {
@@ -1920,11 +1953,14 @@ CheckAllAPs ( }
}
}
+
if (CpuMpData->FailedCpuList != NULL) {
(*CpuMpData->FailedCpuList)[ListIndex] = END_OF_CPU_LIST;
}
+
return EFI_TIMEOUT;
}
+
return EFI_NOT_READY;
}
@@ -1967,16 +2003,17 @@ MpInitLibInitialize ( OldCpuMpData = GetCpuMpDataFromGuidedHob ();
if (OldCpuMpData == NULL) {
- MaxLogicalProcessorNumber = PcdGet32(PcdCpuMaxLogicalProcessorNumber);
+ MaxLogicalProcessorNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
} else {
MaxLogicalProcessorNumber = OldCpuMpData->CpuCount;
}
+
ASSERT (MaxLogicalProcessorNumber != 0);
AsmGetAddressMap (&AddressMap);
ApResetVectorSize = GetApResetVectorSize (&AddressMap);
- ApStackSize = PcdGet32(PcdCpuApStackSize);
- ApLoopMode = GetApLoopMode (&MonitorFilterSize);
+ ApStackSize = PcdGet32 (PcdCpuApStackSize);
+ ApLoopMode = GetApLoopMode (&MonitorFilterSize);
//
// Save BSP's Control registers for APs.
@@ -1993,7 +2030,7 @@ MpInitLibInitialize ( MpBuffer = AllocatePages (EFI_SIZE_TO_PAGES (BufferSize));
ASSERT (MpBuffer != NULL);
ZeroMem (MpBuffer, BufferSize);
- Buffer = (UINTN) MpBuffer;
+ Buffer = (UINTN)MpBuffer;
//
// The layout of the Buffer is as below:
@@ -2016,31 +2053,33 @@ MpInitLibInitialize ( // CPU_INFO_IN_HOB (N)
// +--------------------+
//
- MonitorBuffer = (UINT8 *) (Buffer + ApStackSize * MaxLogicalProcessorNumber);
- BackupBufferAddr = (UINTN) MonitorBuffer + MonitorFilterSize * MaxLogicalProcessorNumber;
- ApIdtBase = ALIGN_VALUE (BackupBufferAddr + ApResetVectorSize, 8);
- CpuMpData = (CPU_MP_DATA *) (ApIdtBase + VolatileRegisters.Idtr.Limit + 1);
+ MonitorBuffer = (UINT8 *)(Buffer + ApStackSize * MaxLogicalProcessorNumber);
+ BackupBufferAddr = (UINTN)MonitorBuffer + MonitorFilterSize * MaxLogicalProcessorNumber;
+ ApIdtBase = ALIGN_VALUE (BackupBufferAddr + ApResetVectorSize, 8);
+ CpuMpData = (CPU_MP_DATA *)(ApIdtBase + VolatileRegisters.Idtr.Limit + 1);
CpuMpData->Buffer = Buffer;
CpuMpData->CpuApStackSize = ApStackSize;
CpuMpData->BackupBuffer = BackupBufferAddr;
CpuMpData->BackupBufferSize = ApResetVectorSize;
- CpuMpData->WakeupBuffer = (UINTN) -1;
+ CpuMpData->WakeupBuffer = (UINTN)-1;
CpuMpData->CpuCount = 1;
CpuMpData->BspNumber = 0;
CpuMpData->WaitEvent = NULL;
CpuMpData->SwitchBspFlag = FALSE;
- CpuMpData->CpuData = (CPU_AP_DATA *) (CpuMpData + 1);
- CpuMpData->CpuInfoInHob = (UINT64) (UINTN) (CpuMpData->CpuData + MaxLogicalProcessorNumber);
- InitializeSpinLock(&CpuMpData->MpLock);
+ CpuMpData->CpuData = (CPU_AP_DATA *)(CpuMpData + 1);
+ CpuMpData->CpuInfoInHob = (UINT64)(UINTN)(CpuMpData->CpuData + MaxLogicalProcessorNumber);
+ InitializeSpinLock (&CpuMpData->MpLock);
CpuMpData->SevEsIsEnabled = PcdGetBool (PcdSevEsIsEnabled);
- CpuMpData->SevEsAPBuffer = (UINTN) -1;
+ CpuMpData->SevEsAPBuffer = (UINTN)-1;
CpuMpData->GhcbBase = PcdGet64 (PcdGhcbBase);
//
// Make sure no memory usage outside of the allocated buffer.
//
- ASSERT ((CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProcessorNumber) ==
- Buffer + BufferSize);
+ ASSERT (
+ (CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProcessorNumber) ==
+ Buffer + BufferSize
+ );
//
// Duplicate BSP's IDT to APs.
@@ -2076,6 +2115,7 @@ MpInitLibInitialize ( CpuMpData->CpuData[Index].StartupApSignal =
(UINT32 *)(MonitorBuffer + MonitorFilterSize * Index);
}
+
//
// Enable the local APIC for Virtual Wire Mode.
//
@@ -2094,13 +2134,13 @@ MpInitLibInitialize ( // from HOB
//
OldCpuMpData->NewCpuMpData = CpuMpData;
- CpuMpData->CpuCount = OldCpuMpData->CpuCount;
- CpuMpData->BspNumber = OldCpuMpData->BspNumber;
- CpuMpData->CpuInfoInHob = OldCpuMpData->CpuInfoInHob;
- CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
+ CpuMpData->CpuCount = OldCpuMpData->CpuCount;
+ CpuMpData->BspNumber = OldCpuMpData->BspNumber;
+ CpuMpData->CpuInfoInHob = OldCpuMpData->CpuInfoInHob;
+ CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
- InitializeSpinLock(&CpuMpData->CpuData[Index].ApLock);
- CpuMpData->CpuData[Index].CpuHealthy = (CpuInfoInHob[Index].Health == 0)? TRUE:FALSE;
+ InitializeSpinLock (&CpuMpData->CpuData[Index].ApLock);
+ CpuMpData->CpuData[Index].CpuHealthy = (CpuInfoInHob[Index].Health == 0) ? TRUE : FALSE;
CpuMpData->CpuData[Index].ApFunction = 0;
}
}
@@ -2108,7 +2148,8 @@ MpInitLibInitialize ( if (!GetMicrocodePatchInfoFromHob (
&CpuMpData->MicrocodePatchAddress,
&CpuMpData->MicrocodePatchRegionSize
- )) {
+ ))
+ {
//
// The microcode patch information cache HOB does not exist, which means
// the microcode patches data has not been loaded into memory yet
@@ -2137,6 +2178,7 @@ MpInitLibInitialize ( //
CpuMpData->InitFlag = ApInitReconfig;
}
+
WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE);
//
// Wait for all APs finished initialization
@@ -2144,9 +2186,11 @@ MpInitLibInitialize ( while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) {
CpuPause ();
}
+
if (OldCpuMpData != NULL) {
CpuMpData->InitFlag = ApInitDone;
}
+
for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
SetApState (&CpuMpData->CpuData[Index], CpuStateIdle);
}
@@ -2156,26 +2200,32 @@ MpInitLibInitialize ( // Dump the microcode revision for each core.
//
DEBUG_CODE_BEGIN ();
- UINT32 ThreadId;
- UINT32 ExpectedMicrocodeRevision;
- CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
- for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
- GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId);
- if (ThreadId == 0) {
- //
- // MicrocodeDetect() loads microcode in first thread of each core, so,
- // CpuMpData->CpuData[Index].MicrocodeEntryAddr is initialized only for first thread of each core.
- //
- ExpectedMicrocodeRevision = 0;
- if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) {
- ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision;
- }
- DEBUG ((
- DEBUG_INFO, "CPU[%04d]: Microcode revision = %08x, expected = %08x\n",
- Index, CpuMpData->CpuData[Index].MicrocodeRevision, ExpectedMicrocodeRevision
- ));
+ UINT32 ThreadId;
+ UINT32 ExpectedMicrocodeRevision;
+
+ CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
+ for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
+ GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId);
+ if (ThreadId == 0) {
+ //
+ // MicrocodeDetect() loads microcode in first thread of each core, so,
+ // CpuMpData->CpuData[Index].MicrocodeEntryAddr is initialized only for first thread of each core.
+ //
+ ExpectedMicrocodeRevision = 0;
+ if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) {
+ ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision;
}
+
+ DEBUG ((
+ DEBUG_INFO,
+ "CPU[%04d]: Microcode revision = %08x, expected = %08x\n",
+ Index,
+ CpuMpData->CpuData[Index].MicrocodeRevision,
+ ExpectedMicrocodeRevision
+ ));
}
+ }
+
DEBUG_CODE_END ();
//
// Initialize global data for MP support
@@ -2210,19 +2260,19 @@ MpInitLibGetProcessorInfo ( OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL
)
{
- CPU_MP_DATA *CpuMpData;
- UINTN CallerNumber;
- CPU_INFO_IN_HOB *CpuInfoInHob;
- UINTN OriginalProcessorNumber;
+ CPU_MP_DATA *CpuMpData;
+ UINTN CallerNumber;
+ CPU_INFO_IN_HOB *CpuInfoInHob;
+ UINTN OriginalProcessorNumber;
- CpuMpData = GetCpuMpData ();
- CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
+ CpuMpData = GetCpuMpData ();
+ CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
//
// Lower 24 bits contains the actual processor number.
//
OriginalProcessorNumber = ProcessorNumber;
- ProcessorNumber &= BIT24 - 1;
+ ProcessorNumber &= BIT24 - 1;
//
// Check whether caller processor is BSP
@@ -2240,14 +2290,16 @@ MpInitLibGetProcessorInfo ( return EFI_NOT_FOUND;
}
- ProcessorInfoBuffer->ProcessorId = (UINT64) CpuInfoInHob[ProcessorNumber].ApicId;
+ ProcessorInfoBuffer->ProcessorId = (UINT64)CpuInfoInHob[ProcessorNumber].ApicId;
ProcessorInfoBuffer->StatusFlag = 0;
if (ProcessorNumber == CpuMpData->BspNumber) {
ProcessorInfoBuffer->StatusFlag |= PROCESSOR_AS_BSP_BIT;
}
+
if (CpuMpData->CpuData[ProcessorNumber].CpuHealthy) {
ProcessorInfoBuffer->StatusFlag |= PROCESSOR_HEALTH_STATUS_BIT;
}
+
if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateDisabled) {
ProcessorInfoBuffer->StatusFlag &= ~PROCESSOR_ENABLED_BIT;
} else {
@@ -2296,8 +2348,8 @@ MpInitLibGetProcessorInfo ( **/
EFI_STATUS
SwitchBSPWorker (
- IN UINTN ProcessorNumber,
- IN BOOLEAN EnableOldBSP
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableOldBSP
)
{
CPU_MP_DATA *CpuMpData;
@@ -2370,7 +2422,7 @@ SwitchBSPWorker ( //
// Clear the BSP bit of MSR_IA32_APIC_BASE
//
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.BSP = 0;
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
@@ -2384,7 +2436,7 @@ SwitchBSPWorker ( //
// Set the BSP bit of MSR_IA32_APIC_BASE on new BSP
//
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.BSP = 1;
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
ProgramVirtualWireMode ();
@@ -2405,10 +2457,11 @@ SwitchBSPWorker ( } else {
SetApState (&CpuMpData->CpuData[CallerNumber], CpuStateIdle);
}
+
//
// Save new BSP number
//
- CpuMpData->BspNumber = (UINT32) ProcessorNumber;
+ CpuMpData->BspNumber = (UINT32)ProcessorNumber;
//
// Restore interrupt state.
@@ -2438,13 +2491,13 @@ SwitchBSPWorker ( **/
EFI_STATUS
EnableDisableApWorker (
- IN UINTN ProcessorNumber,
- IN BOOLEAN EnableAP,
- IN UINT32 *HealthFlag OPTIONAL
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableAP,
+ IN UINT32 *HealthFlag OPTIONAL
)
{
- CPU_MP_DATA *CpuMpData;
- UINTN CallerNumber;
+ CPU_MP_DATA *CpuMpData;
+ UINTN CallerNumber;
CpuMpData = GetCpuMpData ();
@@ -2472,7 +2525,7 @@ EnableDisableApWorker ( if (HealthFlag != NULL) {
CpuMpData->CpuData[ProcessorNumber].CpuHealthy =
- (BOOLEAN) ((*HealthFlag & PROCESSOR_HEALTH_STATUS_BIT) != 0);
+ (BOOLEAN)((*HealthFlag & PROCESSOR_HEALTH_STATUS_BIT) != 0);
}
return EFI_SUCCESS;
@@ -2497,10 +2550,10 @@ EnableDisableApWorker ( EFI_STATUS
EFIAPI
MpInitLibWhoAmI (
- OUT UINTN *ProcessorNumber
+ OUT UINTN *ProcessorNumber
)
{
- CPU_MP_DATA *CpuMpData;
+ CPU_MP_DATA *CpuMpData;
if (ProcessorNumber == NULL) {
return EFI_INVALID_PARAMETER;
@@ -2534,15 +2587,15 @@ MpInitLibWhoAmI ( EFI_STATUS
EFIAPI
MpInitLibGetNumberOfProcessors (
- OUT UINTN *NumberOfProcessors OPTIONAL,
- OUT UINTN *NumberOfEnabledProcessors OPTIONAL
+ OUT UINTN *NumberOfProcessors OPTIONAL,
+ OUT UINTN *NumberOfEnabledProcessors OPTIONAL
)
{
- CPU_MP_DATA *CpuMpData;
- UINTN CallerNumber;
- UINTN ProcessorNumber;
- UINTN EnabledProcessorNumber;
- UINTN Index;
+ CPU_MP_DATA *CpuMpData;
+ UINTN CallerNumber;
+ UINTN ProcessorNumber;
+ UINTN EnabledProcessorNumber;
+ UINTN Index;
CpuMpData = GetCpuMpData ();
@@ -2562,13 +2615,14 @@ MpInitLibGetNumberOfProcessors ( EnabledProcessorNumber = 0;
for (Index = 0; Index < ProcessorNumber; Index++) {
if (GetApState (&CpuMpData->CpuData[Index]) != CpuStateDisabled) {
- EnabledProcessorNumber ++;
+ EnabledProcessorNumber++;
}
}
if (NumberOfProcessors != NULL) {
*NumberOfProcessors = ProcessorNumber;
}
+
if (NumberOfEnabledProcessors != NULL) {
*NumberOfEnabledProcessors = EnabledProcessorNumber;
}
@@ -2576,7 +2630,6 @@ MpInitLibGetNumberOfProcessors ( return EFI_SUCCESS;
}
-
/**
Worker function to execute a caller provided function on all enabled APs.
@@ -2611,23 +2664,23 @@ MpInitLibGetNumberOfProcessors ( **/
EFI_STATUS
StartupAllCPUsWorker (
- IN EFI_AP_PROCEDURE Procedure,
- IN BOOLEAN SingleThread,
- IN BOOLEAN ExcludeBsp,
- IN EFI_EVENT WaitEvent OPTIONAL,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL,
- OUT UINTN **FailedCpuList OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN BOOLEAN SingleThread,
+ IN BOOLEAN ExcludeBsp,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT UINTN **FailedCpuList OPTIONAL
)
{
- EFI_STATUS Status;
- CPU_MP_DATA *CpuMpData;
- UINTN ProcessorCount;
- UINTN ProcessorNumber;
- UINTN CallerNumber;
- CPU_AP_DATA *CpuData;
- BOOLEAN HasEnabledAp;
- CPU_STATE ApState;
+ EFI_STATUS Status;
+ CPU_MP_DATA *CpuMpData;
+ UINTN ProcessorCount;
+ UINTN ProcessorNumber;
+ UINTN CallerNumber;
+ CPU_AP_DATA *CpuData;
+ BOOLEAN HasEnabledAp;
+ CPU_STATE ApState;
CpuMpData = GetCpuMpData ();
@@ -2635,7 +2688,7 @@ StartupAllCPUsWorker ( *FailedCpuList = NULL;
}
- if (CpuMpData->CpuCount == 1 && ExcludeBsp) {
+ if ((CpuMpData->CpuCount == 1) && ExcludeBsp) {
return EFI_NOT_STARTED;
}
@@ -2687,7 +2740,7 @@ StartupAllCPUsWorker ( CpuMpData->RunningCount = 0;
for (ProcessorNumber = 0; ProcessorNumber < ProcessorCount; ProcessorNumber++) {
- CpuData = &CpuMpData->CpuData[ProcessorNumber];
+ CpuData = &CpuMpData->CpuData[ProcessorNumber];
CpuData->Waiting = FALSE;
if (ProcessorNumber != CpuMpData->BspNumber) {
if (CpuData->State == CpuStateIdle) {
@@ -2709,8 +2762,8 @@ StartupAllCPUsWorker ( TimeoutInMicroseconds,
&CpuMpData->CurrentTime
);
- CpuMpData->TotalTime = 0;
- CpuMpData->WaitEvent = WaitEvent;
+ CpuMpData->TotalTime = 0;
+ CpuMpData->WaitEvent = WaitEvent;
if (!SingleThread) {
WakeUpAP (CpuMpData, TRUE, 0, Procedure, ProcedureArgument, FALSE);
@@ -2719,6 +2772,7 @@ StartupAllCPUsWorker ( if (ProcessorNumber == CallerNumber) {
continue;
}
+
if (CpuMpData->CpuData[ProcessorNumber].Waiting) {
WakeUpAP (CpuMpData, FALSE, ProcessorNumber, Procedure, ProcedureArgument, TRUE);
break;
@@ -2768,18 +2822,18 @@ StartupAllCPUsWorker ( **/
EFI_STATUS
StartupThisAPWorker (
- IN EFI_AP_PROCEDURE Procedure,
- IN UINTN ProcessorNumber,
- IN EFI_EVENT WaitEvent OPTIONAL,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL,
- OUT BOOLEAN *Finished OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN ProcessorNumber,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT BOOLEAN *Finished OPTIONAL
)
{
- EFI_STATUS Status;
- CPU_MP_DATA *CpuMpData;
- CPU_AP_DATA *CpuData;
- UINTN CallerNumber;
+ EFI_STATUS Status;
+ CPU_MP_DATA *CpuMpData;
+ CPU_AP_DATA *CpuData;
+ UINTN CallerNumber;
CpuMpData = GetCpuMpData ();
@@ -2833,7 +2887,7 @@ StartupThisAPWorker ( // BSP saves data for CheckAPsStatus(), and returns EFI_SUCCESS.
// CheckAPsStatus() will check completion and timeout periodically.
//
- CpuData = &CpuMpData->CpuData[ProcessorNumber];
+ CpuData = &CpuMpData->CpuData[ProcessorNumber];
CpuData->WaitEvent = WaitEvent;
CpuData->Finished = Finished;
CpuData->ExpectedTime = CalculateTimeout (TimeoutInMicroseconds, &CpuData->CurrentTime);
@@ -2865,16 +2919,17 @@ GetCpuMpDataFromGuidedHob ( VOID
)
{
- EFI_HOB_GUID_TYPE *GuidHob;
- VOID *DataInHob;
- CPU_MP_DATA *CpuMpData;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ VOID *DataInHob;
+ CPU_MP_DATA *CpuMpData;
CpuMpData = NULL;
- GuidHob = GetFirstGuidHob (&mCpuInitMpLibHobGuid);
+ GuidHob = GetFirstGuidHob (&mCpuInitMpLibHobGuid);
if (GuidHob != NULL) {
DataInHob = GET_GUID_HOB_DATA (GuidHob);
- CpuMpData = (CPU_MP_DATA *) (*(UINTN *) DataInHob);
+ CpuMpData = (CPU_MP_DATA *)(*(UINTN *)DataInHob);
}
+
return CpuMpData;
}
@@ -2907,9 +2962,9 @@ GetCpuMpDataFromGuidedHob ( EFI_STATUS
EFIAPI
MpInitLibStartupAllCPUs (
- IN EFI_AP_PROCEDURE Procedure,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL
)
{
return StartupAllCPUsWorker (
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h index 98a207c628..a647772088 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -36,7 +36,7 @@ #include <Guid/MicrocodePatchHob.h>
-#define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P')
+#define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P')
#define CPU_INIT_MP_LIB_HOB_GUID \
{ \
@@ -46,14 +46,14 @@ //
// The MP data for switch BSP
//
-#define CPU_SWITCH_STATE_IDLE 0
-#define CPU_SWITCH_STATE_STORED 1
-#define CPU_SWITCH_STATE_LOADED 2
+#define CPU_SWITCH_STATE_IDLE 0
+#define CPU_SWITCH_STATE_STORED 1
+#define CPU_SWITCH_STATE_LOADED 2
//
// Default maximum number of entries to store the microcode patches information
//
-#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8
+#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8
//
// Data structure for microcode patch information
@@ -67,10 +67,10 @@ typedef struct { // CPU exchange information for switch BSP
//
typedef struct {
- UINT8 State; // offset 0
- UINTN StackPointer; // offset 4 / 8
- IA32_DESCRIPTOR Gdtr; // offset 8 / 16
- IA32_DESCRIPTOR Idtr; // offset 14 / 26
+ UINT8 State; // offset 0
+ UINTN StackPointer; // offset 4 / 8
+ IA32_DESCRIPTOR Gdtr; // offset 8 / 16
+ IA32_DESCRIPTOR Idtr; // offset 14 / 26
} CPU_EXCHANGE_ROLE_INFO;
//
@@ -111,41 +111,41 @@ typedef enum { // CPU volatile registers around INIT-SIPI-SIPI
//
typedef struct {
- UINTN Cr0;
- UINTN Cr3;
- UINTN Cr4;
- UINTN Dr0;
- UINTN Dr1;
- UINTN Dr2;
- UINTN Dr3;
- UINTN Dr6;
- UINTN Dr7;
- IA32_DESCRIPTOR Gdtr;
- IA32_DESCRIPTOR Idtr;
- UINT16 Tr;
+ UINTN Cr0;
+ UINTN Cr3;
+ UINTN Cr4;
+ UINTN Dr0;
+ UINTN Dr1;
+ UINTN Dr2;
+ UINTN Dr3;
+ UINTN Dr6;
+ UINTN Dr7;
+ IA32_DESCRIPTOR Gdtr;
+ IA32_DESCRIPTOR Idtr;
+ UINT16 Tr;
} CPU_VOLATILE_REGISTERS;
//
// AP related data
//
typedef struct {
- SPIN_LOCK ApLock;
- volatile UINT32 *StartupApSignal;
- volatile UINTN ApFunction;
- volatile UINTN ApFunctionArgument;
- BOOLEAN CpuHealthy;
- volatile CPU_STATE State;
- CPU_VOLATILE_REGISTERS VolatileRegisters;
- BOOLEAN Waiting;
- BOOLEAN *Finished;
- UINT64 ExpectedTime;
- UINT64 CurrentTime;
- UINT64 TotalTime;
- EFI_EVENT WaitEvent;
- UINT32 ProcessorSignature;
- UINT8 PlatformId;
- UINT64 MicrocodeEntryAddr;
- UINT32 MicrocodeRevision;
+ SPIN_LOCK ApLock;
+ volatile UINT32 *StartupApSignal;
+ volatile UINTN ApFunction;
+ volatile UINTN ApFunctionArgument;
+ BOOLEAN CpuHealthy;
+ volatile CPU_STATE State;
+ CPU_VOLATILE_REGISTERS VolatileRegisters;
+ BOOLEAN Waiting;
+ BOOLEAN *Finished;
+ UINT64 ExpectedTime;
+ UINT64 CurrentTime;
+ UINT64 TotalTime;
+ EFI_EVENT WaitEvent;
+ UINT32 ProcessorSignature;
+ UINT8 PlatformId;
+ UINT64 MicrocodeEntryAddr;
+ UINT32 MicrocodeRevision;
} CPU_AP_DATA;
//
@@ -156,10 +156,10 @@ typedef struct { //
#pragma pack (1)
typedef struct {
- UINT32 InitialApicId;
- UINT32 ApicId;
- UINT32 Health;
- UINT64 ApTopOfStack;
+ UINT32 InitialApicId;
+ UINT32 ApicId;
+ UINT32 Health;
+ UINT64 ApTopOfStack;
} CPU_INFO_IN_HOB;
#pragma pack ()
@@ -169,20 +169,20 @@ typedef struct { // It is natural aligned by design.
//
typedef struct {
- UINT8 *RendezvousFunnelAddress;
- UINTN ModeEntryOffset;
- UINTN RendezvousFunnelSize;
- UINT8 *RelocateApLoopFuncAddress;
- UINTN RelocateApLoopFuncSize;
- UINTN ModeTransitionOffset;
- UINTN SwitchToRealSize;
- UINTN SwitchToRealOffset;
- UINTN SwitchToRealNoNxOffset;
- UINTN SwitchToRealPM16ModeOffset;
- UINTN SwitchToRealPM16ModeSize;
+ UINT8 *RendezvousFunnelAddress;
+ UINTN ModeEntryOffset;
+ UINTN RendezvousFunnelSize;
+ UINT8 *RelocateApLoopFuncAddress;
+ UINTN RelocateApLoopFuncSize;
+ UINTN ModeTransitionOffset;
+ UINTN SwitchToRealSize;
+ UINTN SwitchToRealOffset;
+ UINTN SwitchToRealNoNxOffset;
+ UINTN SwitchToRealPM16ModeOffset;
+ UINTN SwitchToRealPM16ModeSize;
} MP_ASSEMBLY_ADDRESS_MAP;
-typedef struct _CPU_MP_DATA CPU_MP_DATA;
+typedef struct _CPU_MP_DATA CPU_MP_DATA;
#pragma pack(1)
@@ -192,33 +192,33 @@ typedef struct _CPU_MP_DATA CPU_MP_DATA; // into this structure are used in assembly code in this module
//
typedef struct {
- UINTN StackStart;
- UINTN StackSize;
- UINTN CFunction;
- IA32_DESCRIPTOR GdtrProfile;
- IA32_DESCRIPTOR IdtrProfile;
- UINTN BufferStart;
- UINTN ModeOffset;
- UINTN ApIndex;
- UINTN CodeSegment;
- UINTN DataSegment;
- UINTN EnableExecuteDisable;
- UINTN Cr3;
- UINTN InitFlag;
- CPU_INFO_IN_HOB *CpuInfo;
- UINTN NumApsExecuting;
- CPU_MP_DATA *CpuMpData;
- UINTN InitializeFloatingPointUnitsAddress;
- UINT32 ModeTransitionMemory;
- UINT16 ModeTransitionSegment;
- UINT32 ModeHighMemory;
- UINT16 ModeHighSegment;
+ UINTN StackStart;
+ UINTN StackSize;
+ UINTN CFunction;
+ IA32_DESCRIPTOR GdtrProfile;
+ IA32_DESCRIPTOR IdtrProfile;
+ UINTN BufferStart;
+ UINTN ModeOffset;
+ UINTN ApIndex;
+ UINTN CodeSegment;
+ UINTN DataSegment;
+ UINTN EnableExecuteDisable;
+ UINTN Cr3;
+ UINTN InitFlag;
+ CPU_INFO_IN_HOB *CpuInfo;
+ UINTN NumApsExecuting;
+ CPU_MP_DATA *CpuMpData;
+ UINTN InitializeFloatingPointUnitsAddress;
+ UINT32 ModeTransitionMemory;
+ UINT16 ModeTransitionSegment;
+ UINT32 ModeHighMemory;
+ UINT16 ModeHighSegment;
//
// Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.
//
- BOOLEAN Enable5LevelPaging;
- BOOLEAN SevEsIsEnabled;
- UINTN GhcbBase;
+ BOOLEAN Enable5LevelPaging;
+ BOOLEAN SevEsIsEnabled;
+ UINTN GhcbBase;
} MP_CPU_EXCHANGE_INFO;
#pragma pack()
@@ -227,55 +227,55 @@ typedef struct { // CPU MP Data save in memory
//
struct _CPU_MP_DATA {
- UINT64 CpuInfoInHob;
- UINT32 CpuCount;
- UINT32 BspNumber;
+ UINT64 CpuInfoInHob;
+ UINT32 CpuCount;
+ UINT32 BspNumber;
//
// The above fields data will be passed from PEI to DXE
// Please make sure the fields offset same in the different
// architecture.
//
- SPIN_LOCK MpLock;
- UINTN Buffer;
- UINTN CpuApStackSize;
- MP_ASSEMBLY_ADDRESS_MAP AddressMap;
- UINTN WakeupBuffer;
- UINTN WakeupBufferHigh;
- UINTN BackupBuffer;
- UINTN BackupBufferSize;
-
- volatile UINT32 FinishedCount;
- UINT32 RunningCount;
- BOOLEAN SingleThread;
- EFI_AP_PROCEDURE Procedure;
- VOID *ProcArguments;
- BOOLEAN *Finished;
- UINT64 ExpectedTime;
- UINT64 CurrentTime;
- UINT64 TotalTime;
- EFI_EVENT WaitEvent;
- UINTN **FailedCpuList;
-
- AP_INIT_STATE InitFlag;
- BOOLEAN SwitchBspFlag;
- UINTN NewBspNumber;
- CPU_EXCHANGE_ROLE_INFO BSPInfo;
- CPU_EXCHANGE_ROLE_INFO APInfo;
- MTRR_SETTINGS MtrrTable;
- UINT8 ApLoopMode;
- UINT8 ApTargetCState;
- UINT16 PmCodeSegment;
- UINT16 Pm16CodeSegment;
- CPU_AP_DATA *CpuData;
- volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo;
-
- UINT32 CurrentTimerCount;
- UINTN DivideValue;
- UINT8 Vector;
- BOOLEAN PeriodicMode;
- BOOLEAN TimerInterruptState;
- UINT64 MicrocodePatchAddress;
- UINT64 MicrocodePatchRegionSize;
+ SPIN_LOCK MpLock;
+ UINTN Buffer;
+ UINTN CpuApStackSize;
+ MP_ASSEMBLY_ADDRESS_MAP AddressMap;
+ UINTN WakeupBuffer;
+ UINTN WakeupBufferHigh;
+ UINTN BackupBuffer;
+ UINTN BackupBufferSize;
+
+ volatile UINT32 FinishedCount;
+ UINT32 RunningCount;
+ BOOLEAN SingleThread;
+ EFI_AP_PROCEDURE Procedure;
+ VOID *ProcArguments;
+ BOOLEAN *Finished;
+ UINT64 ExpectedTime;
+ UINT64 CurrentTime;
+ UINT64 TotalTime;
+ EFI_EVENT WaitEvent;
+ UINTN **FailedCpuList;
+
+ AP_INIT_STATE InitFlag;
+ BOOLEAN SwitchBspFlag;
+ UINTN NewBspNumber;
+ CPU_EXCHANGE_ROLE_INFO BSPInfo;
+ CPU_EXCHANGE_ROLE_INFO APInfo;
+ MTRR_SETTINGS MtrrTable;
+ UINT8 ApLoopMode;
+ UINT8 ApTargetCState;
+ UINT16 PmCodeSegment;
+ UINT16 Pm16CodeSegment;
+ CPU_AP_DATA *CpuData;
+ volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo;
+
+ UINT32 CurrentTimerCount;
+ UINTN DivideValue;
+ UINT8 Vector;
+ BOOLEAN PeriodicMode;
+ BOOLEAN TimerInterruptState;
+ UINT64 MicrocodePatchAddress;
+ UINT64 MicrocodePatchRegionSize;
//
// Whether need to use Init-Sipi-Sipi to wake up the APs.
@@ -284,25 +284,25 @@ struct _CPU_MP_DATA { // will be hardcode change to HLT mode by PiSmmCpuDxeSmm
// driver.
//
- BOOLEAN WakeUpByInitSipiSipi;
+ BOOLEAN WakeUpByInitSipiSipi;
- BOOLEAN SevEsIsEnabled;
- UINTN SevEsAPBuffer;
- UINTN SevEsAPResetStackStart;
- CPU_MP_DATA *NewCpuMpData;
+ BOOLEAN SevEsIsEnabled;
+ UINTN SevEsAPBuffer;
+ UINTN SevEsAPResetStackStart;
+ CPU_MP_DATA *NewCpuMpData;
- UINT64 GhcbBase;
+ UINT64 GhcbBase;
};
-#define AP_SAFE_STACK_SIZE 128
-#define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE
+#define AP_SAFE_STACK_SIZE 128
+#define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE
#pragma pack(1)
typedef struct {
- UINT8 InsnBuffer[8];
- UINT16 Rip;
- UINT16 Segment;
+ UINT8 InsnBuffer[8];
+ UINT16 Rip;
+ UINT16 Segment;
} SEV_ES_AP_JMP_FAR;
#pragma pack()
@@ -322,14 +322,14 @@ typedef struct { **/
typedef
VOID
-(EFIAPI AP_RESET) (
+(EFIAPI AP_RESET)(
IN UINTN BufferStart,
IN UINT16 Code16,
IN UINT16 Code32,
IN UINTN StackStart
);
-extern EFI_GUID mCpuInitMpLibHobGuid;
+extern EFI_GUID mCpuInitMpLibHobGuid;
/**
Assembly code to place AP into safe loop mode.
@@ -347,7 +347,7 @@ extern EFI_GUID mCpuInitMpLibHobGuid; **/
typedef
VOID
-(EFIAPI * ASM_RELOCATE_AP_LOOP) (
+(EFIAPI *ASM_RELOCATE_AP_LOOP)(
IN BOOLEAN MwaitSupport,
IN UINTN ApTargetCState,
IN UINTN PmCodeSegment,
@@ -367,7 +367,7 @@ VOID VOID
EFIAPI
AsmGetAddressMap (
- OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap
+ OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap
);
/**
@@ -382,8 +382,8 @@ AsmGetAddressMap ( VOID
EFIAPI
AsmExchangeRole (
- IN CPU_EXCHANGE_ROLE_INFO *MyInfo,
- IN CPU_EXCHANGE_ROLE_INFO *OthersInfo
+ IN CPU_EXCHANGE_ROLE_INFO *MyInfo,
+ IN CPU_EXCHANGE_ROLE_INFO *OthersInfo
);
/**
@@ -403,10 +403,9 @@ GetCpuMpData ( **/
VOID
SaveCpuMpData (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
);
-
/**
Get available system memory below 1MB by specified size.
@@ -417,7 +416,7 @@ SaveCpuMpData ( **/
UINTN
GetWakeupBuffer (
- IN UINTN WakeupBufferSize
+ IN UINTN WakeupBufferSize
);
/**
@@ -434,7 +433,7 @@ GetWakeupBuffer ( **/
UINTN
GetModeTransitionBuffer (
- IN UINTN BufferSize
+ IN UINTN BufferSize
);
/**
@@ -463,12 +462,12 @@ GetSevEsAPMemory ( **/
VOID
WakeUpAP (
- IN CPU_MP_DATA *CpuMpData,
- IN BOOLEAN Broadcast,
- IN UINTN ProcessorNumber,
- IN EFI_AP_PROCEDURE Procedure OPTIONAL,
- IN VOID *ProcedureArgument OPTIONAL,
- IN BOOLEAN WakeUpDisabledAps OPTIONAL
+ IN CPU_MP_DATA *CpuMpData,
+ IN BOOLEAN Broadcast,
+ IN UINTN ProcessorNumber,
+ IN EFI_AP_PROCEDURE Procedure OPTIONAL,
+ IN VOID *ProcedureArgument OPTIONAL,
+ IN BOOLEAN WakeUpDisabledAps OPTIONAL
);
/**
@@ -478,7 +477,7 @@ WakeUpAP ( **/
VOID
InitMpGlobalData (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
);
/**
@@ -515,13 +514,13 @@ InitMpGlobalData ( **/
EFI_STATUS
StartupAllCPUsWorker (
- IN EFI_AP_PROCEDURE Procedure,
- IN BOOLEAN SingleThread,
- IN BOOLEAN ExcludeBsp,
- IN EFI_EVENT WaitEvent OPTIONAL,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL,
- OUT UINTN **FailedCpuList OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN BOOLEAN SingleThread,
+ IN BOOLEAN ExcludeBsp,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT UINTN **FailedCpuList OPTIONAL
);
/**
@@ -549,12 +548,12 @@ StartupAllCPUsWorker ( **/
EFI_STATUS
StartupThisAPWorker (
- IN EFI_AP_PROCEDURE Procedure,
- IN UINTN ProcessorNumber,
- IN EFI_EVENT WaitEvent OPTIONAL,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL,
- OUT BOOLEAN *Finished OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN ProcessorNumber,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT BOOLEAN *Finished OPTIONAL
);
/**
@@ -570,8 +569,8 @@ StartupThisAPWorker ( **/
EFI_STATUS
SwitchBSPWorker (
- IN UINTN ProcessorNumber,
- IN BOOLEAN EnableOldBSP
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableOldBSP
);
/**
@@ -590,9 +589,9 @@ SwitchBSPWorker ( **/
EFI_STATUS
EnableDisableApWorker (
- IN UINTN ProcessorNumber,
- IN BOOLEAN EnableAP,
- IN UINT32 *HealthFlag OPTIONAL
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableAP,
+ IN UINT32 *HealthFlag OPTIONAL
);
/**
@@ -618,7 +617,7 @@ GetCpuMpDataFromGuidedHob ( **/
EFI_STATUS
CheckThisAP (
- IN UINTN ProcessorNumber
+ IN UINTN ProcessorNumber
);
/**
@@ -655,8 +654,8 @@ CheckAndUpdateApsStatus ( **/
VOID
MicrocodeDetect (
- IN CPU_MP_DATA *CpuMpData,
- IN UINTN ProcessorNumber
+ IN CPU_MP_DATA *CpuMpData,
+ IN UINTN ProcessorNumber
);
/**
@@ -666,7 +665,7 @@ MicrocodeDetect ( **/
VOID
ShadowMicrocodeUpdatePatch (
- IN OUT CPU_MP_DATA *CpuMpData
+ IN OUT CPU_MP_DATA *CpuMpData
);
/**
@@ -686,8 +685,8 @@ ShadowMicrocodeUpdatePatch ( **/
BOOLEAN
GetMicrocodePatchInfoFromHob (
- UINT64 *Address,
- UINT64 *RegionSize
+ UINT64 *Address,
+ UINT64 *RegionSize
);
/**
@@ -721,8 +720,8 @@ EnableDebugAgent ( **/
EFI_STATUS
GetProcessorNumber (
- IN CPU_MP_DATA *CpuMpData,
- OUT UINTN *ProcessorNumber
+ IN CPU_MP_DATA *CpuMpData,
+ OUT UINTN *ProcessorNumber
);
/**
@@ -738,7 +737,7 @@ GetProcessorNumber ( **/
EFI_STATUS
PlatformShadowMicrocode (
- IN OUT CPU_MP_DATA *CpuMpData
+ IN OUT CPU_MP_DATA *CpuMpData
);
#endif
diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c index 90015c650c..ab79360bb9 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -11,7 +11,7 @@ #include <Guid/S3SmmInitDone.h>
#include <Ppi/ShadowMicrocode.h>
-STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB;
+STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB;
/**
S3 SMM Init Done notification function.
@@ -26,16 +26,15 @@ STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB; EFI_STATUS
EFIAPI
NotifyOnS3SmmInitDonePpi (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
- IN VOID *InvokePpi
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+ IN VOID *InvokePpi
);
-
//
// Global function
//
-EFI_PEI_NOTIFY_DESCRIPTOR mS3SmmInitDoneNotifyDesc = {
+EFI_PEI_NOTIFY_DESCRIPTOR mS3SmmInitDoneNotifyDesc = {
EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gEdkiiS3SmmInitDoneGuid,
NotifyOnS3SmmInitDonePpi
@@ -54,12 +53,12 @@ EFI_PEI_NOTIFY_DESCRIPTOR mS3SmmInitDoneNotifyDesc = { EFI_STATUS
EFIAPI
NotifyOnS3SmmInitDonePpi (
- IN EFI_PEI_SERVICES **PeiServices,
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
- IN VOID *InvokePpi
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+ IN VOID *InvokePpi
)
{
- CPU_MP_DATA *CpuMpData;
+ CPU_MP_DATA *CpuMpData;
CpuMpData = GetCpuMpData ();
@@ -76,7 +75,6 @@ NotifyOnS3SmmInitDonePpi ( return EFI_SUCCESS;
}
-
/**
Enable Debug Agent to support source debugging on AP function.
@@ -110,8 +108,9 @@ GetCpuMpData ( ASSERT (CpuMpData != NULL);
} else {
AsmReadIdtr (&Idtr);
- CpuMpData = (CPU_MP_DATA *) (Idtr.Base + Idtr.Limit + 1);
+ CpuMpData = (CPU_MP_DATA *)(Idtr.Base + Idtr.Limit + 1);
}
+
return CpuMpData;
}
@@ -122,17 +121,18 @@ GetCpuMpData ( **/
VOID
SaveCpuMpData (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
)
{
- UINT64 Data64;
+ UINT64 Data64;
+
//
// Build location of CPU MP DATA buffer in HOB
//
- Data64 = (UINT64) (UINTN) CpuMpData;
+ Data64 = (UINT64)(UINTN)CpuMpData;
BuildGuidDataHob (
&mCpuInitMpLibHobGuid,
- (VOID *) &Data64,
+ (VOID *)&Data64,
sizeof (UINT64)
);
}
@@ -148,15 +148,15 @@ SaveCpuMpData ( **/
BOOLEAN
CheckOverlapWithAllocatedBuffer (
- IN UINT64 WakeupBufferStart,
- IN UINT64 WakeupBufferEnd
+ IN UINT64 WakeupBufferStart,
+ IN UINT64 WakeupBufferEnd
)
{
- EFI_PEI_HOB_POINTERS Hob;
- EFI_HOB_MEMORY_ALLOCATION *MemoryHob;
- BOOLEAN Overlapped;
- UINT64 MemoryStart;
- UINT64 MemoryEnd;
+ EFI_PEI_HOB_POINTERS Hob;
+ EFI_HOB_MEMORY_ALLOCATION *MemoryHob;
+ BOOLEAN Overlapped;
+ UINT64 MemoryStart;
+ UINT64 MemoryEnd;
Overlapped = FALSE;
//
@@ -176,8 +176,10 @@ CheckOverlapWithAllocatedBuffer ( break;
}
}
+
Hob.Raw = GET_NEXT_HOB (Hob);
}
+
return Overlapped;
}
@@ -191,12 +193,12 @@ CheckOverlapWithAllocatedBuffer ( **/
UINTN
GetWakeupBuffer (
- IN UINTN WakeupBufferSize
+ IN UINTN WakeupBufferSize
)
{
- EFI_PEI_HOB_POINTERS Hob;
- UINT64 WakeupBufferStart;
- UINT64 WakeupBufferEnd;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINT64 WakeupBufferStart;
+ UINT64 WakeupBufferEnd;
WakeupBufferSize = (WakeupBufferSize + SIZE_4KB - 1) & ~(SIZE_4KB - 1);
@@ -216,14 +218,16 @@ GetWakeupBuffer ( (EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED |
EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED |
EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED
- )) == 0)
- ) {
+ )) == 0)
+ )
+ {
//
// Need memory under 1MB to be collected here
//
WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength;
if (PcdGetBool (PcdSevEsIsEnabled) &&
- WakeupBufferEnd > mSevEsPeiWakeupBuffer) {
+ (WakeupBufferEnd > mSevEsPeiWakeupBuffer))
+ {
//
// SEV-ES Wakeup buffer should be under 1MB and under any previous one
//
@@ -234,6 +238,7 @@ GetWakeupBuffer ( //
WakeupBufferEnd = BASE_1MB;
}
+
while (WakeupBufferEnd > WakeupBufferSize) {
//
// Wakeup buffer should be aligned on 4KB
@@ -242,6 +247,7 @@ GetWakeupBuffer ( if (WakeupBufferStart < Hob.ResourceDescriptor->PhysicalStart) {
break;
}
+
if (CheckOverlapWithAllocatedBuffer (WakeupBufferStart, WakeupBufferEnd)) {
//
// If this range is overlapped with existing allocated buffer, skip it
@@ -250,8 +256,13 @@ GetWakeupBuffer ( WakeupBufferEnd -= WakeupBufferSize;
continue;
}
- DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
- WakeupBufferStart, WakeupBufferSize));
+
+ DEBUG ((
+ DEBUG_INFO,
+ "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
+ WakeupBufferStart,
+ WakeupBufferSize
+ ));
if (PcdGetBool (PcdSevEsIsEnabled)) {
//
@@ -265,13 +276,14 @@ GetWakeupBuffer ( }
}
}
+
//
// Find the next HOB
//
Hob.Raw = GET_NEXT_HOB (Hob);
}
- return (UINTN) -1;
+ return (UINTN)-1;
}
/**
@@ -288,7 +300,7 @@ GetWakeupBuffer ( **/
UINTN
GetModeTransitionBuffer (
- IN UINTN BufferSize
+ IN UINTN BufferSize
)
{
//
@@ -336,17 +348,17 @@ CheckAndUpdateApsStatus ( **/
VOID
BuildMicrocodeCacheHob (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
)
{
- EDKII_MICROCODE_PATCH_HOB *MicrocodeHob;
- UINTN HobDataLength;
- UINT32 Index;
+ EDKII_MICROCODE_PATCH_HOB *MicrocodeHob;
+ UINTN HobDataLength;
+ UINT32 Index;
HobDataLength = sizeof (EDKII_MICROCODE_PATCH_HOB) +
sizeof (UINT64) * CpuMpData->CpuCount;
- MicrocodeHob = AllocatePool (HobDataLength);
+ MicrocodeHob = AllocatePool (HobDataLength);
if (MicrocodeHob == NULL) {
ASSERT (FALSE);
return;
@@ -387,7 +399,7 @@ BuildMicrocodeCacheHob ( **/
VOID
InitMpGlobalData (
- IN CPU_MP_DATA *CpuMpData
+ IN CPU_MP_DATA *CpuMpData
)
{
EFI_STATUS Status;
@@ -480,12 +492,12 @@ InitMpGlobalData ( EFI_STATUS
EFIAPI
MpInitLibStartupAllAPs (
- IN EFI_AP_PROCEDURE Procedure,
- IN BOOLEAN SingleThread,
- IN EFI_EVENT WaitEvent OPTIONAL,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL,
- OUT UINTN **FailedCpuList OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN BOOLEAN SingleThread,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT UINTN **FailedCpuList OPTIONAL
)
{
if (WaitEvent != NULL) {
@@ -577,12 +589,12 @@ MpInitLibStartupAllAPs ( EFI_STATUS
EFIAPI
MpInitLibStartupThisAP (
- IN EFI_AP_PROCEDURE Procedure,
- IN UINTN ProcessorNumber,
- IN EFI_EVENT WaitEvent OPTIONAL,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL,
- OUT BOOLEAN *Finished OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN ProcessorNumber,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT BOOLEAN *Finished OPTIONAL
)
{
if (WaitEvent != NULL) {
@@ -628,8 +640,8 @@ MpInitLibStartupThisAP ( EFI_STATUS
EFIAPI
MpInitLibSwitchBSP (
- IN UINTN ProcessorNumber,
- IN BOOLEAN EnableOldBSP
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableOldBSP
)
{
return SwitchBSPWorker (ProcessorNumber, EnableOldBSP);
@@ -668,9 +680,9 @@ MpInitLibSwitchBSP ( EFI_STATUS
EFIAPI
MpInitLibEnableDisableAP (
- IN UINTN ProcessorNumber,
- IN BOOLEAN EnableAP,
- IN UINT32 *HealthFlag OPTIONAL
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableAP,
+ IN UINT32 *HealthFlag OPTIONAL
)
{
return EnableDisableApWorker (ProcessorNumber, EnableAP, HealthFlag);
@@ -689,29 +701,29 @@ MpInitLibEnableDisableAP ( **/
EFI_STATUS
PlatformShadowMicrocode (
- IN OUT CPU_MP_DATA *CpuMpData
+ IN OUT CPU_MP_DATA *CpuMpData
)
{
- EFI_STATUS Status;
- EDKII_PEI_SHADOW_MICROCODE_PPI *ShadowMicrocodePpi;
- UINTN CpuCount;
- EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId;
- UINTN Index;
- UINTN BufferSize;
- VOID *Buffer;
+ EFI_STATUS Status;
+ EDKII_PEI_SHADOW_MICROCODE_PPI *ShadowMicrocodePpi;
+ UINTN CpuCount;
+ EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId;
+ UINTN Index;
+ UINTN BufferSize;
+ VOID *Buffer;
Status = PeiServicesLocatePpi (
&gEdkiiPeiShadowMicrocodePpiGuid,
0,
NULL,
- (VOID **) &ShadowMicrocodePpi
+ (VOID **)&ShadowMicrocodePpi
);
if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED;
}
- CpuCount = CpuMpData->CpuCount;
- MicrocodeCpuId = (EDKII_PEI_MICROCODE_CPU_ID *) AllocateZeroPool (sizeof (EDKII_PEI_MICROCODE_CPU_ID) * CpuCount);
+ CpuCount = CpuMpData->CpuCount;
+ MicrocodeCpuId = (EDKII_PEI_MICROCODE_CPU_ID *)AllocateZeroPool (sizeof (EDKII_PEI_MICROCODE_CPU_ID) * CpuCount);
if (MicrocodeCpuId == NULL) {
return EFI_OUT_OF_RESOURCES;
}
@@ -722,24 +734,26 @@ PlatformShadowMicrocode ( }
Status = ShadowMicrocodePpi->ShadowMicrocode (
- ShadowMicrocodePpi,
- CpuCount,
- MicrocodeCpuId,
- &BufferSize,
- &Buffer
- );
+ ShadowMicrocodePpi,
+ CpuCount,
+ MicrocodeCpuId,
+ &BufferSize,
+ &Buffer
+ );
FreePool (MicrocodeCpuId);
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
- CpuMpData->MicrocodePatchAddress = (UINTN) Buffer;
+ CpuMpData->MicrocodePatchAddress = (UINTN)Buffer;
CpuMpData->MicrocodePatchRegionSize = BufferSize;
DEBUG ((
DEBUG_INFO,
"%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n",
- __FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize
+ __FUNCTION__,
+ CpuMpData->MicrocodePatchAddress,
+ CpuMpData->MicrocodePatchRegionSize
));
return EFI_SUCCESS;
diff --git a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c index 7a461af9b1..86f9fbf903 100644 --- a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c +++ b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c @@ -63,8 +63,8 @@ MpInitLibInitialize ( EFI_STATUS
EFIAPI
MpInitLibGetNumberOfProcessors (
- OUT UINTN *NumberOfProcessors OPTIONAL,
- OUT UINTN *NumberOfEnabledProcessors OPTIONAL
+ OUT UINTN *NumberOfProcessors OPTIONAL,
+ OUT UINTN *NumberOfEnabledProcessors OPTIONAL
)
{
*NumberOfProcessors = 1;
@@ -103,13 +103,15 @@ MpInitLibGetProcessorInfo ( if (ProcessorInfoBuffer == NULL) {
return EFI_INVALID_PARAMETER;
}
+
if (ProcessorNumber != 0) {
return EFI_NOT_FOUND;
}
- ProcessorInfoBuffer->ProcessorId = 0;
- ProcessorInfoBuffer->StatusFlag = PROCESSOR_AS_BSP_BIT |
- PROCESSOR_ENABLED_BIT |
- PROCESSOR_HEALTH_STATUS_BIT;
+
+ ProcessorInfoBuffer->ProcessorId = 0;
+ ProcessorInfoBuffer->StatusFlag = PROCESSOR_AS_BSP_BIT |
+ PROCESSOR_ENABLED_BIT |
+ PROCESSOR_HEALTH_STATUS_BIT;
ProcessorInfoBuffer->Location.Package = 0;
ProcessorInfoBuffer->Location.Core = 0;
ProcessorInfoBuffer->Location.Thread = 0;
@@ -117,12 +119,13 @@ MpInitLibGetProcessorInfo ( GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);
if (GuidHob != NULL) {
SecPlatformInformation = GET_GUID_HOB_DATA (GuidHob);
- HealthData->Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32;
+ HealthData->Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32;
} else {
DEBUG ((DEBUG_INFO, "Does not find any HOB stored CPU BIST information!\n"));
HealthData->Uint32 = 0;
}
}
+
return EFI_SUCCESS;
}
@@ -204,12 +207,12 @@ MpInitLibGetProcessorInfo ( EFI_STATUS
EFIAPI
MpInitLibStartupAllAPs (
- IN EFI_AP_PROCEDURE Procedure,
- IN BOOLEAN SingleThread,
- IN EFI_EVENT WaitEvent OPTIONAL,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL,
- OUT UINTN **FailedCpuList OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN BOOLEAN SingleThread,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT UINTN **FailedCpuList OPTIONAL
)
{
return EFI_NOT_STARTED;
@@ -289,12 +292,12 @@ MpInitLibStartupAllAPs ( EFI_STATUS
EFIAPI
MpInitLibStartupThisAP (
- IN EFI_AP_PROCEDURE Procedure,
- IN UINTN ProcessorNumber,
- IN EFI_EVENT WaitEvent OPTIONAL,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL,
- OUT BOOLEAN *Finished OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN ProcessorNumber,
+ IN EFI_EVENT WaitEvent OPTIONAL,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL,
+ OUT BOOLEAN *Finished OPTIONAL
)
{
return EFI_INVALID_PARAMETER;
@@ -329,8 +332,8 @@ MpInitLibStartupThisAP ( EFI_STATUS
EFIAPI
MpInitLibSwitchBSP (
- IN UINTN ProcessorNumber,
- IN BOOLEAN EnableOldBSP
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableOldBSP
)
{
return EFI_UNSUPPORTED;
@@ -369,9 +372,9 @@ MpInitLibSwitchBSP ( EFI_STATUS
EFIAPI
MpInitLibEnableDisableAP (
- IN UINTN ProcessorNumber,
- IN BOOLEAN EnableAP,
- IN UINT32 *HealthFlag OPTIONAL
+ IN UINTN ProcessorNumber,
+ IN BOOLEAN EnableAP,
+ IN UINT32 *HealthFlag OPTIONAL
)
{
return EFI_UNSUPPORTED;
@@ -396,12 +399,13 @@ MpInitLibEnableDisableAP ( EFI_STATUS
EFIAPI
MpInitLibWhoAmI (
- OUT UINTN *ProcessorNumber
+ OUT UINTN *ProcessorNumber
)
{
if (ProcessorNumber == NULL) {
return EFI_INVALID_PARAMETER;
}
+
*ProcessorNumber = 0;
return EFI_SUCCESS;
}
@@ -427,9 +431,9 @@ MpInitLibWhoAmI ( EFI_STATUS
EFIAPI
MpInitLibStartupAllCPUs (
- IN EFI_AP_PROCEDURE Procedure,
- IN UINTN TimeoutInMicroseconds,
- IN VOID *ProcedureArgument OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN TimeoutInMicroseconds,
+ IN VOID *ProcedureArgument OPTIONAL
)
{
if (Procedure == NULL) {
diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c index 805a2f8d21..e5c862c83d 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -20,35 +20,35 @@ #include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
-#define OR_SEED 0x0101010101010101ull
-#define CLEAR_SEED 0xFFFFFFFFFFFFFFFFull
-#define MAX_WEIGHT MAX_UINT8
-#define SCRATCH_BUFFER_SIZE (4 * SIZE_4KB)
-#define MTRR_LIB_ASSERT_ALIGNED(B, L) ASSERT ((B & ~(L - 1)) == B);
+#define OR_SEED 0x0101010101010101ull
+#define CLEAR_SEED 0xFFFFFFFFFFFFFFFFull
+#define MAX_WEIGHT MAX_UINT8
+#define SCRATCH_BUFFER_SIZE (4 * SIZE_4KB)
+#define MTRR_LIB_ASSERT_ALIGNED(B, L) ASSERT ((B & ~(L - 1)) == B);
-#define M(x,y) ((x) * VertexCount + (y))
-#define O(x,y) ((y) * VertexCount + (x))
+#define M(x, y) ((x) * VertexCount + (y))
+#define O(x, y) ((y) * VertexCount + (x))
//
// Context to save and restore when MTRRs are programmed
//
typedef struct {
- UINTN Cr4;
- BOOLEAN InterruptState;
+ UINTN Cr4;
+ BOOLEAN InterruptState;
} MTRR_CONTEXT;
typedef struct {
- UINT64 Address;
- UINT64 Alignment;
- UINT64 Length;
- MTRR_MEMORY_CACHE_TYPE Type : 7;
+ UINT64 Address;
+ UINT64 Alignment;
+ UINT64 Length;
+ MTRR_MEMORY_CACHE_TYPE Type : 7;
//
// Temprary use for calculating the best MTRR settings.
//
- BOOLEAN Visited : 1;
- UINT8 Weight;
- UINT16 Previous;
+ BOOLEAN Visited : 1;
+ UINT8 Weight;
+ UINT16 Previous;
} MTRR_LIB_ADDRESS;
//
@@ -115,7 +115,7 @@ CONST FIXED_MTRR mMtrrLibFixedMtrrTable[] = { //
// Lookup table used to print MTRRs
//
-GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = {
"UC", // CacheUncacheable
"WC", // CacheWriteCombining
"R*", // Invalid
@@ -126,7 +126,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = { "R*" // Invalid
};
-
/**
Worker function prints all MTRRs for debugging.
@@ -138,7 +137,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = { **/
VOID
MtrrDebugPrintAllMtrrsWorker (
- IN MTRR_SETTINGS *MtrrSetting
+ IN MTRR_SETTINGS *MtrrSetting
);
/**
@@ -152,10 +151,10 @@ GetVariableMtrrCountWorker ( VOID
)
{
- MSR_IA32_MTRRCAP_REGISTER MtrrCap;
+ MSR_IA32_MTRRCAP_REGISTER MtrrCap;
MtrrCap.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
- ASSERT (MtrrCap.Bits.VCNT <= ARRAY_SIZE (((MTRR_VARIABLE_SETTINGS *) 0)->Mtrr));
+ ASSERT (MtrrCap.Bits.VCNT <= ARRAY_SIZE (((MTRR_VARIABLE_SETTINGS *)0)->Mtrr));
return MtrrCap.Bits.VCNT;
}
@@ -174,6 +173,7 @@ GetVariableMtrrCount ( if (!IsMtrrSupported ()) {
return 0;
}
+
return GetVariableMtrrCountWorker ();
}
@@ -191,7 +191,7 @@ GetFirmwareVariableMtrrCountWorker ( UINT32 VariableMtrrCount;
UINT32 ReservedMtrrNumber;
- VariableMtrrCount = GetVariableMtrrCountWorker ();
+ VariableMtrrCount = GetVariableMtrrCountWorker ();
ReservedMtrrNumber = PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);
if (VariableMtrrCount < ReservedMtrrNumber) {
return 0;
@@ -215,6 +215,7 @@ GetFirmwareVariableMtrrCount ( if (!IsMtrrSupported ()) {
return 0;
}
+
return GetFirmwareVariableMtrrCountWorker ();
}
@@ -232,10 +233,10 @@ GetFirmwareVariableMtrrCount ( **/
MTRR_MEMORY_CACHE_TYPE
MtrrGetDefaultMemoryTypeWorker (
- IN MTRR_SETTINGS *MtrrSetting
+ IN MTRR_SETTINGS *MtrrSetting
)
{
- MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
+ MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
if (MtrrSetting == NULL) {
DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
@@ -243,10 +244,9 @@ MtrrGetDefaultMemoryTypeWorker ( DefType.Uint64 = MtrrSetting->MtrrDefType;
}
- return (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;
+ return (MTRR_MEMORY_CACHE_TYPE)DefType.Bits.Type;
}
-
/**
Returns the default MTRR cache type for the system.
@@ -262,6 +262,7 @@ MtrrGetDefaultMemoryType ( if (!IsMtrrSupported ()) {
return CacheUncacheable;
}
+
return MtrrGetDefaultMemoryTypeWorker (NULL);
}
@@ -280,10 +281,11 @@ MtrrLibPreMtrrChange ( )
{
MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
+
//
// Disable interrupts and save current interrupt state
//
- MtrrContext->InterruptState = SaveAndDisableInterrupts();
+ MtrrContext->InterruptState = SaveAndDisableInterrupts ();
//
// Enter no fill cache mode, CD=1(Bit30), NW=0 (Bit29)
@@ -359,11 +361,12 @@ MtrrLibPostMtrrChange ( )
{
MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
+
//
// Enable Cache MTRR
//
- DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
- DefType.Bits.E = 1;
+ DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
+ DefType.Bits.E = 1;
DefType.Bits.FE = 1;
AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);
@@ -378,22 +381,21 @@ MtrrLibPostMtrrChange ( @retval The pointer of FixedSettings
**/
-MTRR_FIXED_SETTINGS*
+MTRR_FIXED_SETTINGS *
MtrrGetFixedMtrrWorker (
- OUT MTRR_FIXED_SETTINGS *FixedSettings
+ OUT MTRR_FIXED_SETTINGS *FixedSettings
)
{
UINT32 Index;
for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
- FixedSettings->Mtrr[Index] =
- AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);
+ FixedSettings->Mtrr[Index] =
+ AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);
}
return FixedSettings;
}
-
/**
This function gets the content in fixed MTRRs
@@ -402,10 +404,10 @@ MtrrGetFixedMtrrWorker ( @retval The pointer of FixedSettings
**/
-MTRR_FIXED_SETTINGS*
+MTRR_FIXED_SETTINGS *
EFIAPI
MtrrGetFixedMtrr (
- OUT MTRR_FIXED_SETTINGS *FixedSettings
+ OUT MTRR_FIXED_SETTINGS *FixedSettings
)
{
if (!IsMtrrSupported ()) {
@@ -415,7 +417,6 @@ MtrrGetFixedMtrr ( return MtrrGetFixedMtrrWorker (FixedSettings);
}
-
/**
Worker function will get the raw value in variable MTRRs
@@ -430,7 +431,7 @@ MtrrGetFixedMtrr ( @return The VariableSettings input pointer
**/
-MTRR_VARIABLE_SETTINGS*
+MTRR_VARIABLE_SETTINGS *
MtrrGetVariableMtrrWorker (
IN MTRR_SETTINGS *MtrrSetting,
IN UINT32 VariableMtrrCount,
@@ -453,7 +454,7 @@ MtrrGetVariableMtrrWorker ( }
}
- return VariableSettings;
+ return VariableSettings;
}
/**
@@ -493,12 +494,13 @@ MtrrLibProgramFixedMtrr ( for (MsrIndex = *LastMsrIndex + 1; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {
if ((*Base >= mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) &&
(*Base <
- (
- mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress +
- (8 * mMtrrLibFixedMtrrTable[MsrIndex].Length)
- )
- )
- ) {
+ (
+ mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress +
+ (8 * mMtrrLibFixedMtrrTable[MsrIndex].Length)
+ )
+ )
+ )
+ {
break;
}
}
@@ -514,6 +516,7 @@ MtrrLibProgramFixedMtrr ( //
return RETURN_UNSUPPORTED;
}
+
LeftByteShift = ((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) / mMtrrLibFixedMtrrTable[MsrIndex].Length;
ASSERT (LeftByteShift < 8);
@@ -530,6 +533,7 @@ MtrrLibProgramFixedMtrr ( //
return RETURN_UNSUPPORTED;
}
+
RightByteShift = 8 - LeftByteShift - (UINT32)(*Length) / mMtrrLibFixedMtrrTable[MsrIndex].Length;
//
// Update SubLength by actual length
@@ -538,14 +542,14 @@ MtrrLibProgramFixedMtrr ( }
*ClearMask = CLEAR_SEED;
- *OrMask = MultU64x32 (OR_SEED, (UINT32) Type);
+ *OrMask = MultU64x32 (OR_SEED, (UINT32)Type);
if (LeftByteShift != 0) {
//
// Clear the low bits by LeftByteShift
//
*ClearMask &= LShiftU64 (*ClearMask, LeftByteShift * 8);
- *OrMask &= LShiftU64 (*OrMask, LeftByteShift * 8);
+ *OrMask &= LShiftU64 (*OrMask, LeftByteShift * 8);
}
if (RightByteShift != 0) {
@@ -553,18 +557,17 @@ MtrrLibProgramFixedMtrr ( // Clear the high bits by RightByteShift
//
*ClearMask &= RShiftU64 (*ClearMask, RightByteShift * 8);
- *OrMask &= RShiftU64 (*OrMask, RightByteShift * 8);
+ *OrMask &= RShiftU64 (*OrMask, RightByteShift * 8);
}
*Length -= SubLength;
*Base += SubLength;
- *LastMsrIndex = MsrIndex;
+ *LastMsrIndex = MsrIndex;
return RETURN_SUCCESS;
}
-
/**
Worker function gets the attribute of variable MTRRs.
@@ -594,17 +597,18 @@ MtrrGetMemoryAttributeInVariableMtrrWorker ( ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * ARRAY_SIZE (VariableSettings->Mtrr));
for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) {
- if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {
+ if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {
VariableMtrr[Index].Msr = (UINT32)Index;
VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask);
VariableMtrr[Index].Length =
((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;
- VariableMtrr[Index].Type = (VariableSettings->Mtrr[Index].Base & 0x0ff);
- VariableMtrr[Index].Valid = TRUE;
- VariableMtrr[Index].Used = TRUE;
+ VariableMtrr[Index].Type = (VariableSettings->Mtrr[Index].Base & 0x0ff);
+ VariableMtrr[Index].Valid = TRUE;
+ VariableMtrr[Index].Used = TRUE;
UsedMtrr++;
}
}
+
return UsedMtrr;
}
@@ -636,14 +640,15 @@ MtrrLibGetRawVariableRanges ( ZeroMem (VariableMtrr, sizeof (MTRR_MEMORY_RANGE) * ARRAY_SIZE (VariableSettings->Mtrr));
for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) {
- if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {
+ if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {
VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask);
VariableMtrr[Index].Length =
((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;
- VariableMtrr[Index].Type = (MTRR_MEMORY_CACHE_TYPE)(VariableSettings->Mtrr[Index].Base & 0x0ff);
+ VariableMtrr[Index].Type = (MTRR_MEMORY_CACHE_TYPE)(VariableSettings->Mtrr[Index].Base & 0x0ff);
UsedMtrr++;
}
}
+
return UsedMtrr;
}
@@ -664,9 +669,9 @@ MtrrLibGetRawVariableRanges ( UINT32
EFIAPI
MtrrGetMemoryAttributeInVariableMtrr (
- IN UINT64 MtrrValidBitsMask,
- IN UINT64 MtrrValidAddressMask,
- OUT VARIABLE_MTRR *VariableMtrr
+ IN UINT64 MtrrValidBitsMask,
+ IN UINT64 MtrrValidAddressMask,
+ OUT VARIABLE_MTRR *VariableMtrr
)
{
MTRR_VARIABLE_SETTINGS VariableSettings;
@@ -701,9 +706,9 @@ MtrrGetMemoryAttributeInVariableMtrr ( **/
UINT64
MtrrLibBiggestAlignment (
- UINT64 Address,
- UINT64 Alignment0
-)
+ UINT64 Address,
+ UINT64 Alignment0
+ )
{
if (Address == 0) {
return Alignment0;
@@ -731,9 +736,9 @@ BOOLEAN MtrrLibTypeLeftPrecedeRight (
IN MTRR_MEMORY_CACHE_TYPE Left,
IN MTRR_MEMORY_CACHE_TYPE Right
-)
+ )
{
- return (BOOLEAN) (Left == CacheUncacheable || (Left == CacheWriteThrough && Right == CacheWriteBack));
+ return (BOOLEAN)(Left == CacheUncacheable || (Left == CacheWriteThrough && Right == CacheWriteBack));
}
/**
@@ -747,14 +752,13 @@ MtrrLibTypeLeftPrecedeRight ( **/
VOID
MtrrLibInitializeMtrrMask (
- OUT UINT64 *MtrrValidBitsMask,
- OUT UINT64 *MtrrValidAddressMask
+ OUT UINT64 *MtrrValidBitsMask,
+ OUT UINT64 *MtrrValidAddressMask
)
{
UINT32 MaxExtendedFunction;
CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
-
AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);
if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {
@@ -763,11 +767,10 @@ MtrrLibInitializeMtrrMask ( VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
}
- *MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
+ *MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
*MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL;
}
-
/**
Determines the real attribute of a memory range.
@@ -782,8 +785,8 @@ MtrrLibInitializeMtrrMask ( **/
MTRR_MEMORY_CACHE_TYPE
MtrrLibPrecedence (
- IN MTRR_MEMORY_CACHE_TYPE MtrrType1,
- IN MTRR_MEMORY_CACHE_TYPE MtrrType2
+ IN MTRR_MEMORY_CACHE_TYPE MtrrType1,
+ IN MTRR_MEMORY_CACHE_TYPE MtrrType2
)
{
if (MtrrType1 == MtrrType2) {
@@ -793,7 +796,7 @@ MtrrLibPrecedence ( ASSERT (
MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2) ||
MtrrLibTypeLeftPrecedeRight (MtrrType2, MtrrType1)
- );
+ );
if (MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2)) {
return MtrrType1;
@@ -817,20 +820,20 @@ MtrrLibPrecedence ( **/
MTRR_MEMORY_CACHE_TYPE
MtrrGetMemoryAttributeByAddressWorker (
- IN MTRR_SETTINGS *MtrrSetting,
- IN PHYSICAL_ADDRESS Address
+ IN MTRR_SETTINGS *MtrrSetting,
+ IN PHYSICAL_ADDRESS Address
)
{
- MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
- UINT64 FixedMtrr;
- UINTN Index;
- UINTN SubIndex;
- MTRR_MEMORY_CACHE_TYPE MtrrType;
- MTRR_MEMORY_RANGE VariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
- UINT64 MtrrValidBitsMask;
- UINT64 MtrrValidAddressMask;
- UINT32 VariableMtrrCount;
- MTRR_VARIABLE_SETTINGS VariableSettings;
+ MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;
+ UINT64 FixedMtrr;
+ UINTN Index;
+ UINTN SubIndex;
+ MTRR_MEMORY_CACHE_TYPE MtrrType;
+ MTRR_MEMORY_RANGE VariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
+ UINT64 MtrrValidBitsMask;
+ UINT64 MtrrValidAddressMask;
+ UINT32 VariableMtrrCount;
+ MTRR_VARIABLE_SETTINGS VariableSettings;
//
// Check if MTRR is enabled, if not, return UC as attribute
@@ -854,18 +857,20 @@ MtrrGetMemoryAttributeByAddressWorker ( // Go through the fixed MTRR
//
for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
- if (Address >= mMtrrLibFixedMtrrTable[Index].BaseAddress &&
- Address < mMtrrLibFixedMtrrTable[Index].BaseAddress +
- (mMtrrLibFixedMtrrTable[Index].Length * 8)) {
+ if ((Address >= mMtrrLibFixedMtrrTable[Index].BaseAddress) &&
+ (Address < mMtrrLibFixedMtrrTable[Index].BaseAddress +
+ (mMtrrLibFixedMtrrTable[Index].Length * 8)))
+ {
SubIndex =
- ((UINTN) Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) /
+ ((UINTN)Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) /
mMtrrLibFixedMtrrTable[Index].Length;
if (MtrrSetting == NULL) {
FixedMtrr = AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);
} else {
FixedMtrr = MtrrSetting->Fixed.Mtrr[Index];
}
- return (MTRR_MEMORY_CACHE_TYPE) (RShiftU64 (FixedMtrr, SubIndex * 8) & 0xFF);
+
+ return (MTRR_MEMORY_CACHE_TYPE)(RShiftU64 (FixedMtrr, SubIndex * 8) & 0xFF);
}
}
}
@@ -882,7 +887,7 @@ MtrrGetMemoryAttributeByAddressWorker ( MtrrValidBitsMask,
MtrrValidAddressMask,
VariableMtrr
- );
+ );
//
// Go through the variable MTRR
@@ -890,12 +895,13 @@ MtrrGetMemoryAttributeByAddressWorker ( MtrrType = CacheInvalid;
for (Index = 0; Index < VariableMtrrCount; Index++) {
if (VariableMtrr[Index].Length != 0) {
- if (Address >= VariableMtrr[Index].BaseAddress &&
- Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].Length) {
+ if ((Address >= VariableMtrr[Index].BaseAddress) &&
+ (Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].Length))
+ {
if (MtrrType == CacheInvalid) {
- MtrrType = (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type;
+ MtrrType = (MTRR_MEMORY_CACHE_TYPE)VariableMtrr[Index].Type;
} else {
- MtrrType = MtrrLibPrecedence (MtrrType, (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type);
+ MtrrType = MtrrLibPrecedence (MtrrType, (MTRR_MEMORY_CACHE_TYPE)VariableMtrr[Index].Type);
}
}
}
@@ -905,13 +911,12 @@ MtrrGetMemoryAttributeByAddressWorker ( // If there is no MTRR which covers the Address, use the default MTRR type.
//
if (MtrrType == CacheInvalid) {
- MtrrType = (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;
+ MtrrType = (MTRR_MEMORY_CACHE_TYPE)DefType.Bits.Type;
}
return MtrrType;
}
-
/**
This function will get the memory cache type of the specific address.
@@ -925,7 +930,7 @@ MtrrGetMemoryAttributeByAddressWorker ( MTRR_MEMORY_CACHE_TYPE
EFIAPI
MtrrGetMemoryAttribute (
- IN PHYSICAL_ADDRESS Address
+ IN PHYSICAL_ADDRESS Address
)
{
if (!IsMtrrSupported ()) {
@@ -955,46 +960,48 @@ MtrrGetMemoryAttribute ( **/
RETURN_STATUS
MtrrLibSetMemoryType (
- IN MTRR_MEMORY_RANGE *Ranges,
- IN UINTN Capacity,
- IN OUT UINTN *Count,
- IN UINT64 BaseAddress,
- IN UINT64 Length,
- IN MTRR_MEMORY_CACHE_TYPE Type
+ IN MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN Capacity,
+ IN OUT UINTN *Count,
+ IN UINT64 BaseAddress,
+ IN UINT64 Length,
+ IN MTRR_MEMORY_CACHE_TYPE Type
)
{
- UINTN Index;
- UINT64 Limit;
- UINT64 LengthLeft;
- UINT64 LengthRight;
- UINTN StartIndex;
- UINTN EndIndex;
- UINTN DeltaCount;
+ UINTN Index;
+ UINT64 Limit;
+ UINT64 LengthLeft;
+ UINT64 LengthRight;
+ UINTN StartIndex;
+ UINTN EndIndex;
+ UINTN DeltaCount;
LengthRight = 0;
LengthLeft = 0;
- Limit = BaseAddress + Length;
- StartIndex = *Count;
- EndIndex = *Count;
+ Limit = BaseAddress + Length;
+ StartIndex = *Count;
+ EndIndex = *Count;
for (Index = 0; Index < *Count; Index++) {
if ((StartIndex == *Count) &&
(Ranges[Index].BaseAddress <= BaseAddress) &&
- (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)) {
+ (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length))
+ {
StartIndex = Index;
LengthLeft = BaseAddress - Ranges[Index].BaseAddress;
}
if ((EndIndex == *Count) &&
(Ranges[Index].BaseAddress < Limit) &&
- (Limit <= Ranges[Index].BaseAddress + Ranges[Index].Length)) {
- EndIndex = Index;
+ (Limit <= Ranges[Index].BaseAddress + Ranges[Index].Length))
+ {
+ EndIndex = Index;
LengthRight = Ranges[Index].BaseAddress + Ranges[Index].Length - Limit;
break;
}
}
ASSERT (StartIndex != *Count && EndIndex != *Count);
- if (StartIndex == EndIndex && Ranges[StartIndex].Type == Type) {
+ if ((StartIndex == EndIndex) && (Ranges[StartIndex].Type == Type)) {
return RETURN_ALREADY_STARTED;
}
@@ -1004,14 +1011,15 @@ MtrrLibSetMemoryType ( // logic doesn't need to consider merging.
//
if (StartIndex != 0) {
- if (LengthLeft == 0 && Ranges[StartIndex - 1].Type == Type) {
+ if ((LengthLeft == 0) && (Ranges[StartIndex - 1].Type == Type)) {
StartIndex--;
- Length += Ranges[StartIndex].Length;
+ Length += Ranges[StartIndex].Length;
BaseAddress -= Ranges[StartIndex].Length;
}
}
+
if (EndIndex != (*Count) - 1) {
- if (LengthRight == 0 && Ranges[EndIndex + 1].Type == Type) {
+ if ((LengthRight == 0) && (Ranges[EndIndex + 1].Type == Type)) {
EndIndex++;
Length += Ranges[EndIndex].Length;
}
@@ -1029,9 +1037,11 @@ MtrrLibSetMemoryType ( if (LengthLeft == 0) {
DeltaCount++;
}
+
if (LengthRight == 0) {
DeltaCount++;
}
+
if (*Count - DeltaCount > Capacity) {
return RETURN_OUT_OF_RESOURCES;
}
@@ -1046,14 +1056,16 @@ MtrrLibSetMemoryType ( Ranges[StartIndex].Length = LengthLeft;
StartIndex++;
}
+
if (LengthRight != 0) {
Ranges[EndIndex - DeltaCount].BaseAddress = BaseAddress + Length;
- Ranges[EndIndex - DeltaCount].Length = LengthRight;
- Ranges[EndIndex - DeltaCount].Type = Ranges[EndIndex].Type;
+ Ranges[EndIndex - DeltaCount].Length = LengthRight;
+ Ranges[EndIndex - DeltaCount].Type = Ranges[EndIndex].Type;
}
+
Ranges[StartIndex].BaseAddress = BaseAddress;
- Ranges[StartIndex].Length = Length;
- Ranges[StartIndex].Type = Type;
+ Ranges[StartIndex].Length = Length;
+ Ranges[StartIndex].Type = Type;
return RETURN_SUCCESS;
}
@@ -1070,30 +1082,31 @@ MtrrLibSetMemoryType ( **/
UINT8
MtrrLibGetNumberOfTypes (
- IN CONST MTRR_MEMORY_RANGE *Ranges,
- IN UINTN RangeCount,
- IN UINT64 BaseAddress,
- IN UINT64 Length,
- IN OUT UINT8 *Types OPTIONAL
+ IN CONST MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCount,
+ IN UINT64 BaseAddress,
+ IN UINT64 Length,
+ IN OUT UINT8 *Types OPTIONAL
)
{
- UINTN Index;
- UINT8 TypeCount;
- UINT8 LocalTypes;
+ UINTN Index;
+ UINT8 TypeCount;
+ UINT8 LocalTypes;
- TypeCount = 0;
+ TypeCount = 0;
LocalTypes = 0;
for (Index = 0; Index < RangeCount; Index++) {
if ((Ranges[Index].BaseAddress <= BaseAddress) &&
(BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)
- ) {
+ )
+ {
if ((LocalTypes & (1 << Ranges[Index].Type)) == 0) {
LocalTypes |= (UINT8)(1 << Ranges[Index].Type);
TypeCount++;
}
if (BaseAddress + Length > Ranges[Index].BaseAddress + Ranges[Index].Length) {
- Length -= Ranges[Index].BaseAddress + Ranges[Index].Length - BaseAddress;
+ Length -= Ranges[Index].BaseAddress + Ranges[Index].Length - BaseAddress;
BaseAddress = Ranges[Index].BaseAddress + Ranges[Index].Length;
} else {
break;
@@ -1104,6 +1117,7 @@ MtrrLibGetNumberOfTypes ( if (Types != NULL) {
*Types = LocalTypes;
}
+
return TypeCount;
}
@@ -1121,32 +1135,32 @@ MtrrLibGetNumberOfTypes ( **/
VOID
MtrrLibCalculateLeastMtrrs (
- IN UINT16 VertexCount,
- IN MTRR_LIB_ADDRESS *Vertices,
- IN OUT CONST UINT8 *Weight,
- IN UINT16 Start,
- IN UINT16 Stop,
- IN BOOLEAN IncludeOptional
+ IN UINT16 VertexCount,
+ IN MTRR_LIB_ADDRESS *Vertices,
+ IN OUT CONST UINT8 *Weight,
+ IN UINT16 Start,
+ IN UINT16 Stop,
+ IN BOOLEAN IncludeOptional
)
{
- UINT16 Index;
- UINT8 MinWeight;
- UINT16 MinI;
- UINT8 Mandatory;
- UINT8 Optional;
+ UINT16 Index;
+ UINT8 MinWeight;
+ UINT16 MinI;
+ UINT8 Mandatory;
+ UINT8 Optional;
for (Index = Start; Index <= Stop; Index++) {
Vertices[Index].Visited = FALSE;
- Mandatory = Weight[M(Start,Index)];
- Vertices[Index].Weight = Mandatory;
+ Mandatory = Weight[M (Start, Index)];
+ Vertices[Index].Weight = Mandatory;
if (Mandatory != MAX_WEIGHT) {
- Optional = IncludeOptional ? Weight[O(Start, Index)] : 0;
+ Optional = IncludeOptional ? Weight[O (Start, Index)] : 0;
Vertices[Index].Weight += Optional;
ASSERT (Vertices[Index].Weight >= Optional);
}
}
- MinI = Start;
+ MinI = Start;
MinWeight = 0;
while (!Vertices[Stop].Visited) {
//
@@ -1154,9 +1168,9 @@ MtrrLibCalculateLeastMtrrs ( //
for (Index = Start + 1; Index <= Stop; Index++) {
if (!Vertices[Index].Visited) {
- Mandatory = Weight[M(MinI, Index)];
+ Mandatory = Weight[M (MinI, Index)];
if (Mandatory != MAX_WEIGHT) {
- Optional = IncludeOptional ? Weight[O(MinI, Index)] : 0;
+ Optional = IncludeOptional ? Weight[O (MinI, Index)] : 0;
if (MinWeight + Mandatory + Optional <= Vertices[Index].Weight) {
Vertices[Index].Weight = MinWeight + Mandatory + Optional;
Vertices[Index].Previous = MinI; // Previous is Start based.
@@ -1171,7 +1185,7 @@ MtrrLibCalculateLeastMtrrs ( MinI = VertexCount;
MinWeight = MAX_WEIGHT;
for (Index = Start + 1; Index <= Stop; Index++) {
- if (!Vertices[Index].Visited && MinWeight > Vertices[Index].Weight) {
+ if (!Vertices[Index].Visited && (MinWeight > Vertices[Index].Weight)) {
MinI = Index;
MinWeight = Vertices[Index].Weight;
}
@@ -1227,13 +1241,15 @@ MtrrLibAppendVariableMtrr ( **/
MTRR_MEMORY_CACHE_TYPE
MtrrLibLowestType (
- IN UINT8 TypeBits
-)
+ IN UINT8 TypeBits
+ )
{
- INT8 Type;
+ INT8 Type;
ASSERT (TypeBits != 0);
- for (Type = 7; (INT8)TypeBits > 0; Type--, TypeBits <<= 1);
+ for (Type = 7; (INT8)TypeBits > 0; Type--, TypeBits <<= 1) {
+ }
+
return (MTRR_MEMORY_CACHE_TYPE)Type;
}
@@ -1245,11 +1261,11 @@ MtrrLibLowestType ( **/
BOOLEAN
MtrrLibIsPowerOfTwo (
- IN UINT64 Operand
-)
+ IN UINT64 Operand
+ )
{
ASSERT (Operand != 0);
- return (BOOLEAN) ((Operand & (Operand - 1)) == 0);
+ return (BOOLEAN)((Operand & (Operand - 1)) == 0);
}
/**
@@ -1276,36 +1292,36 @@ MtrrLibIsPowerOfTwo ( **/
RETURN_STATUS
MtrrLibCalculateSubtractivePath (
- IN MTRR_MEMORY_CACHE_TYPE DefaultType,
- IN UINT64 A0,
- IN CONST MTRR_MEMORY_RANGE *Ranges,
- IN UINTN RangeCount,
- IN UINT16 VertexCount,
- IN MTRR_LIB_ADDRESS *Vertices,
- IN OUT UINT8 *Weight,
- IN UINT16 Start,
- IN UINT16 Stop,
- IN UINT8 Types,
- IN UINT8 TypeCount,
- IN OUT MTRR_MEMORY_RANGE *Mtrrs OPTIONAL,
- IN UINT32 MtrrCapacity OPTIONAL,
- IN OUT UINT32 *MtrrCount OPTIONAL
+ IN MTRR_MEMORY_CACHE_TYPE DefaultType,
+ IN UINT64 A0,
+ IN CONST MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCount,
+ IN UINT16 VertexCount,
+ IN MTRR_LIB_ADDRESS *Vertices,
+ IN OUT UINT8 *Weight,
+ IN UINT16 Start,
+ IN UINT16 Stop,
+ IN UINT8 Types,
+ IN UINT8 TypeCount,
+ IN OUT MTRR_MEMORY_RANGE *Mtrrs OPTIONAL,
+ IN UINT32 MtrrCapacity OPTIONAL,
+ IN OUT UINT32 *MtrrCount OPTIONAL
)
{
- RETURN_STATUS Status;
- UINT64 Base;
- UINT64 Length;
- UINT8 PrecedentTypes;
- UINTN Index;
- UINT64 HBase;
- UINT64 HLength;
- UINT64 SubLength;
- UINT16 SubStart;
- UINT16 SubStop;
- UINT16 Cur;
- UINT16 Pre;
- MTRR_MEMORY_CACHE_TYPE LowestType;
- MTRR_MEMORY_CACHE_TYPE LowestPrecedentType;
+ RETURN_STATUS Status;
+ UINT64 Base;
+ UINT64 Length;
+ UINT8 PrecedentTypes;
+ UINTN Index;
+ UINT64 HBase;
+ UINT64 HLength;
+ UINT64 SubLength;
+ UINT16 SubStart;
+ UINT16 SubStop;
+ UINT16 Cur;
+ UINT16 Pre;
+ MTRR_MEMORY_CACHE_TYPE LowestType;
+ MTRR_MEMORY_CACHE_TYPE LowestPrecedentType;
Base = Vertices[Start].Address;
Length = Vertices[Stop].Address - Base;
@@ -1315,21 +1331,22 @@ MtrrLibCalculateSubtractivePath ( //
// Clear the lowest type (highest bit) to get the precedent types
//
- PrecedentTypes = ~(1 << LowestType) & Types;
+ PrecedentTypes = ~(1 << LowestType) & Types;
LowestPrecedentType = MtrrLibLowestType (PrecedentTypes);
if (Mtrrs == NULL) {
- Weight[M(Start, Stop)] = ((LowestType == DefaultType) ? 0 : 1);
- Weight[O(Start, Stop)] = ((LowestType == DefaultType) ? 1 : 0);
+ Weight[M (Start, Stop)] = ((LowestType == DefaultType) ? 0 : 1);
+ Weight[O (Start, Stop)] = ((LowestType == DefaultType) ? 1 : 0);
}
// Add all high level ranges
- HBase = MAX_UINT64;
+ HBase = MAX_UINT64;
HLength = 0;
for (Index = 0; Index < RangeCount; Index++) {
if (Length == 0) {
break;
}
+
if ((Base < Ranges[Index].BaseAddress) || (Ranges[Index].BaseAddress + Ranges[Index].Length <= Base)) {
continue;
}
@@ -1342,6 +1359,7 @@ MtrrLibCalculateSubtractivePath ( } else {
SubLength = Length;
}
+
if (((1 << Ranges[Index].Type) & PrecedentTypes) != 0) {
//
// Meet a range whose types take precedence.
@@ -1351,17 +1369,19 @@ MtrrLibCalculateSubtractivePath ( if (HBase == MAX_UINT64) {
HBase = Base;
}
+
HLength += SubLength;
}
- Base += SubLength;
+ Base += SubLength;
Length -= SubLength;
if (HLength == 0) {
continue;
}
- if ((Ranges[Index].Type == LowestType) || (Length == 0)) { // meet low type or end
+ if ((Ranges[Index].Type == LowestType) || (Length == 0)) {
+ // meet low type or end
//
// Add the MTRRs for each high priority type range
@@ -1379,6 +1399,7 @@ MtrrLibCalculateSubtractivePath ( break;
}
}
+
ASSERT (Vertices[SubStart].Address == HBase);
ASSERT (Vertices[SubStop].Address == HBase + HLength);
@@ -1393,12 +1414,17 @@ MtrrLibCalculateSubtractivePath ( } else {
while (SubStart != SubStop) {
Status = MtrrLibAppendVariableMtrr (
- Mtrrs, MtrrCapacity, MtrrCount,
- Vertices[SubStart].Address, Vertices[SubStart].Length, Vertices[SubStart].Type
- );
+ Mtrrs,
+ MtrrCapacity,
+ MtrrCount,
+ Vertices[SubStart].Address,
+ Vertices[SubStart].Length,
+ Vertices[SubStart].Type
+ );
if (RETURN_ERROR (Status)) {
return Status;
}
+
SubStart++;
}
}
@@ -1411,43 +1437,57 @@ MtrrLibCalculateSubtractivePath ( } else {
// When we need to collect the optimal path from SubStart to SubStop
while (SubStop != SubStart) {
- Cur = SubStop;
- Pre = Vertices[Cur].Previous;
+ Cur = SubStop;
+ Pre = Vertices[Cur].Previous;
SubStop = Pre;
if (Weight[M (Pre, Cur)] + Weight[O (Pre, Cur)] != 0) {
Status = MtrrLibAppendVariableMtrr (
- Mtrrs, MtrrCapacity, MtrrCount,
- Vertices[Pre].Address, Vertices[Cur].Address - Vertices[Pre].Address,
- (Pre != Cur - 1) ? LowestPrecedentType : Vertices[Pre].Type
- );
+ Mtrrs,
+ MtrrCapacity,
+ MtrrCount,
+ Vertices[Pre].Address,
+ Vertices[Cur].Address - Vertices[Pre].Address,
+ (Pre != Cur - 1) ? LowestPrecedentType : Vertices[Pre].Type
+ );
if (RETURN_ERROR (Status)) {
return Status;
}
}
+
if (Pre != Cur - 1) {
Status = MtrrLibCalculateSubtractivePath (
- DefaultType, A0,
- Ranges, RangeCount,
- VertexCount, Vertices, Weight,
- Pre, Cur, PrecedentTypes, 2,
- Mtrrs, MtrrCapacity, MtrrCount
- );
+ DefaultType,
+ A0,
+ Ranges,
+ RangeCount,
+ VertexCount,
+ Vertices,
+ Weight,
+ Pre,
+ Cur,
+ PrecedentTypes,
+ 2,
+ Mtrrs,
+ MtrrCapacity,
+ MtrrCount
+ );
if (RETURN_ERROR (Status)) {
return Status;
}
}
}
}
-
}
+
//
// Reset HBase, HLength
//
- HBase = MAX_UINT64;
+ HBase = MAX_UINT64;
HLength = 0;
}
}
+
return RETURN_SUCCESS;
}
@@ -1474,34 +1514,34 @@ MtrrLibCalculateSubtractivePath ( **/
RETURN_STATUS
MtrrLibCalculateMtrrs (
- IN MTRR_MEMORY_CACHE_TYPE DefaultType,
- IN UINT64 A0,
- IN CONST MTRR_MEMORY_RANGE *Ranges,
- IN UINTN RangeCount,
- IN VOID *Scratch,
- IN OUT UINTN *ScratchSize,
- IN OUT MTRR_MEMORY_RANGE *Mtrrs,
- IN UINT32 MtrrCapacity,
- IN OUT UINT32 *MtrrCount
+ IN MTRR_MEMORY_CACHE_TYPE DefaultType,
+ IN UINT64 A0,
+ IN CONST MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCount,
+ IN VOID *Scratch,
+ IN OUT UINTN *ScratchSize,
+ IN OUT MTRR_MEMORY_RANGE *Mtrrs,
+ IN UINT32 MtrrCapacity,
+ IN OUT UINT32 *MtrrCount
)
{
- UINT64 Base0;
- UINT64 Base1;
- UINTN Index;
- UINT64 Base;
- UINT64 Length;
- UINT64 Alignment;
- UINT64 SubLength;
- MTRR_LIB_ADDRESS *Vertices;
- UINT8 *Weight;
- UINT32 VertexIndex;
- UINT32 VertexCount;
- UINTN RequiredScratchSize;
- UINT8 TypeCount;
- UINT16 Start;
- UINT16 Stop;
- UINT8 Type;
- RETURN_STATUS Status;
+ UINT64 Base0;
+ UINT64 Base1;
+ UINTN Index;
+ UINT64 Base;
+ UINT64 Length;
+ UINT64 Alignment;
+ UINT64 SubLength;
+ MTRR_LIB_ADDRESS *Vertices;
+ UINT8 *Weight;
+ UINT32 VertexIndex;
+ UINT32 VertexCount;
+ UINTN RequiredScratchSize;
+ UINT8 TypeCount;
+ UINT16 Start;
+ UINT16 Stop;
+ UINT8 Type;
+ RETURN_STATUS Status;
Base0 = Ranges[0].BaseAddress;
Base1 = Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length;
@@ -1510,9 +1550,9 @@ MtrrLibCalculateMtrrs ( //
// Count the number of vertices.
//
- Vertices = (MTRR_LIB_ADDRESS*)Scratch;
+ Vertices = (MTRR_LIB_ADDRESS *)Scratch;
for (VertexIndex = 0, Index = 0; Index < RangeCount; Index++) {
- Base = Ranges[Index].BaseAddress;
+ Base = Ranges[Index].BaseAddress;
Length = Ranges[Index].Length;
while (Length != 0) {
Alignment = MtrrLibBiggestAlignment (Base, A0);
@@ -1520,24 +1560,30 @@ MtrrLibCalculateMtrrs ( if (SubLength > Length) {
SubLength = GetPowerOfTwo64 (Length);
}
+
if (VertexIndex < *ScratchSize / sizeof (*Vertices)) {
Vertices[VertexIndex].Address = Base;
Vertices[VertexIndex].Alignment = Alignment;
Vertices[VertexIndex].Type = Ranges[Index].Type;
Vertices[VertexIndex].Length = SubLength;
}
+
Base += SubLength;
Length -= SubLength;
VertexIndex++;
}
}
+
//
// Vertices[VertexIndex] = Base1, so whole vertex count is (VertexIndex + 1).
//
VertexCount = VertexIndex + 1;
DEBUG ((
- DEBUG_CACHE, " Count of vertices (%016llx - %016llx) = %d\n",
- Ranges[0].BaseAddress, Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length, VertexCount
+ DEBUG_CACHE,
+ " Count of vertices (%016llx - %016llx) = %d\n",
+ Ranges[0].BaseAddress,
+ Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length,
+ VertexCount
));
ASSERT (VertexCount < MAX_UINT16);
@@ -1546,14 +1592,15 @@ MtrrLibCalculateMtrrs ( *ScratchSize = RequiredScratchSize;
return RETURN_BUFFER_TOO_SMALL;
}
+
Vertices[VertexCount - 1].Address = Base1;
- Weight = (UINT8 *) &Vertices[VertexCount];
+ Weight = (UINT8 *)&Vertices[VertexCount];
for (VertexIndex = 0; VertexIndex < VertexCount; VertexIndex++) {
//
// Set optional weight between vertices and self->self to 0
//
- SetMem (&Weight[M(VertexIndex, 0)], VertexIndex + 1, 0);
+ SetMem (&Weight[M (VertexIndex, 0)], VertexIndex + 1, 0);
//
// Set mandatory weight between vertices to MAX_WEIGHT
//
@@ -1590,19 +1637,34 @@ MtrrLibCalculateMtrrs ( //
break;
}
- if ((Weight[M(Start, Stop)] == MAX_WEIGHT) && MtrrLibIsPowerOfTwo (Length)) {
+
+ if ((Weight[M (Start, Stop)] == MAX_WEIGHT) && MtrrLibIsPowerOfTwo (Length)) {
if (MtrrLibGetNumberOfTypes (
- Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type
- ) == TypeCount) {
+ Ranges,
+ RangeCount,
+ Vertices[Start].Address,
+ Vertices[Stop].Address - Vertices[Start].Address,
+ &Type
+ ) == TypeCount)
+ {
//
// Update the Weight[Start, Stop] using subtractive path.
//
MtrrLibCalculateSubtractivePath (
- DefaultType, A0,
- Ranges, RangeCount,
- (UINT16)VertexCount, Vertices, Weight,
- Start, Stop, Type, TypeCount,
- NULL, 0, NULL
+ DefaultType,
+ A0,
+ Ranges,
+ RangeCount,
+ (UINT16)VertexCount,
+ Vertices,
+ Weight,
+ Start,
+ Stop,
+ Type,
+ TypeCount,
+ NULL,
+ 0,
+ NULL
);
} else if (TypeCount == 2) {
//
@@ -1617,19 +1679,22 @@ MtrrLibCalculateMtrrs ( }
Status = RETURN_SUCCESS;
- MtrrLibCalculateLeastMtrrs ((UINT16) VertexCount, Vertices, Weight, 0, (UINT16) VertexCount - 1, FALSE);
- Stop = (UINT16) VertexCount - 1;
+ MtrrLibCalculateLeastMtrrs ((UINT16)VertexCount, Vertices, Weight, 0, (UINT16)VertexCount - 1, FALSE);
+ Stop = (UINT16)VertexCount - 1;
while (Stop != 0) {
- Start = Vertices[Stop].Previous;
+ Start = Vertices[Stop].Previous;
TypeCount = MAX_UINT8;
- Type = 0;
- if (Weight[M(Start, Stop)] != 0) {
+ Type = 0;
+ if (Weight[M (Start, Stop)] != 0) {
TypeCount = MtrrLibGetNumberOfTypes (Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type);
- Status = MtrrLibAppendVariableMtrr (
- Mtrrs, MtrrCapacity, MtrrCount,
- Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address,
- MtrrLibLowestType (Type)
- );
+ Status = MtrrLibAppendVariableMtrr (
+ Mtrrs,
+ MtrrCapacity,
+ MtrrCount,
+ Vertices[Start].Address,
+ Vertices[Stop].Address - Vertices[Start].Address,
+ MtrrLibLowestType (Type)
+ );
if (RETURN_ERROR (Status)) {
break;
}
@@ -1641,26 +1706,41 @@ MtrrLibCalculateMtrrs ( //
if (TypeCount == MAX_UINT8) {
TypeCount = MtrrLibGetNumberOfTypes (
- Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type
+ Ranges,
+ RangeCount,
+ Vertices[Start].Address,
+ Vertices[Stop].Address - Vertices[Start].Address,
+ &Type
);
}
+
Status = MtrrLibCalculateSubtractivePath (
- DefaultType, A0,
- Ranges, RangeCount,
- (UINT16) VertexCount, Vertices, Weight, Start, Stop,
- Type, TypeCount,
- Mtrrs, MtrrCapacity, MtrrCount
+ DefaultType,
+ A0,
+ Ranges,
+ RangeCount,
+ (UINT16)VertexCount,
+ Vertices,
+ Weight,
+ Start,
+ Stop,
+ Type,
+ TypeCount,
+ Mtrrs,
+ MtrrCapacity,
+ MtrrCount
);
if (RETURN_ERROR (Status)) {
break;
}
}
+
Stop = Start;
}
+
return Status;
}
-
/**
Apply the fixed MTRR settings to memory range array.
@@ -1681,26 +1761,33 @@ MtrrLibApplyFixedMtrrs ( IN OUT UINTN *RangeCount
)
{
- RETURN_STATUS Status;
- UINTN MsrIndex;
- UINTN Index;
- MTRR_MEMORY_CACHE_TYPE MemoryType;
- UINT64 Base;
+ RETURN_STATUS Status;
+ UINTN MsrIndex;
+ UINTN Index;
+ MTRR_MEMORY_CACHE_TYPE MemoryType;
+ UINT64 Base;
Base = 0;
for (MsrIndex = 0; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {
ASSERT (Base == mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress);
for (Index = 0; Index < sizeof (UINT64); Index++) {
MemoryType = (MTRR_MEMORY_CACHE_TYPE)((UINT8 *)(&Fixed->Mtrr[MsrIndex]))[Index];
- Status = MtrrLibSetMemoryType (
- Ranges, RangeCapacity, RangeCount, Base, mMtrrLibFixedMtrrTable[MsrIndex].Length, MemoryType
- );
+ Status = MtrrLibSetMemoryType (
+ Ranges,
+ RangeCapacity,
+ RangeCount,
+ Base,
+ mMtrrLibFixedMtrrTable[MsrIndex].Length,
+ MemoryType
+ );
if (Status == RETURN_OUT_OF_RESOURCES) {
return Status;
}
+
Base += mMtrrLibFixedMtrrTable[MsrIndex].Length;
}
}
+
ASSERT (Base == BASE_1MB);
return RETURN_SUCCESS;
}
@@ -1719,15 +1806,15 @@ MtrrLibApplyFixedMtrrs ( **/
RETURN_STATUS
MtrrLibApplyVariableMtrrs (
- IN CONST MTRR_MEMORY_RANGE *VariableMtrr,
- IN UINT32 VariableMtrrCount,
- IN OUT MTRR_MEMORY_RANGE *Ranges,
- IN UINTN RangeCapacity,
- IN OUT UINTN *RangeCount
+ IN CONST MTRR_MEMORY_RANGE *VariableMtrr,
+ IN UINT32 VariableMtrrCount,
+ IN OUT MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCapacity,
+ IN OUT UINTN *RangeCount
)
{
- RETURN_STATUS Status;
- UINTN Index;
+ RETURN_STATUS Status;
+ UINTN Index;
//
// WT > WB
@@ -1741,9 +1828,13 @@ MtrrLibApplyVariableMtrrs ( for (Index = 0; Index < VariableMtrrCount; Index++) {
if ((VariableMtrr[Index].Length != 0) && (VariableMtrr[Index].Type == CacheWriteBack)) {
Status = MtrrLibSetMemoryType (
- Ranges, RangeCapacity, RangeCount,
- VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type
- );
+ Ranges,
+ RangeCapacity,
+ RangeCount,
+ VariableMtrr[Index].BaseAddress,
+ VariableMtrr[Index].Length,
+ VariableMtrr[Index].Type
+ );
if (Status == RETURN_OUT_OF_RESOURCES) {
return Status;
}
@@ -1755,10 +1846,15 @@ MtrrLibApplyVariableMtrrs ( //
for (Index = 0; Index < VariableMtrrCount; Index++) {
if ((VariableMtrr[Index].Length != 0) &&
- (VariableMtrr[Index].Type != CacheWriteBack) && (VariableMtrr[Index].Type != CacheUncacheable)) {
+ (VariableMtrr[Index].Type != CacheWriteBack) && (VariableMtrr[Index].Type != CacheUncacheable))
+ {
Status = MtrrLibSetMemoryType (
- Ranges, RangeCapacity, RangeCount,
- VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type
+ Ranges,
+ RangeCapacity,
+ RangeCount,
+ VariableMtrr[Index].BaseAddress,
+ VariableMtrr[Index].Length,
+ VariableMtrr[Index].Type
);
if (Status == RETURN_OUT_OF_RESOURCES) {
return Status;
@@ -1770,16 +1866,21 @@ MtrrLibApplyVariableMtrrs ( // 3. Set UC
//
for (Index = 0; Index < VariableMtrrCount; Index++) {
- if (VariableMtrr[Index].Length != 0 && VariableMtrr[Index].Type == CacheUncacheable) {
+ if ((VariableMtrr[Index].Length != 0) && (VariableMtrr[Index].Type == CacheUncacheable)) {
Status = MtrrLibSetMemoryType (
- Ranges, RangeCapacity, RangeCount,
- VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type
+ Ranges,
+ RangeCapacity,
+ RangeCount,
+ VariableMtrr[Index].BaseAddress,
+ VariableMtrr[Index].Length,
+ VariableMtrr[Index].Type
);
if (Status == RETURN_OUT_OF_RESOURCES) {
return Status;
}
}
}
+
return RETURN_SUCCESS;
}
@@ -1794,35 +1895,37 @@ MtrrLibApplyVariableMtrrs ( **/
UINT8
MtrrLibGetCompatibleTypes (
- IN CONST MTRR_MEMORY_RANGE *Ranges,
- IN UINTN RangeCount
+ IN CONST MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCount
)
{
ASSERT (RangeCount != 0);
switch (Ranges[0].Type) {
- case CacheWriteBack:
- case CacheWriteThrough:
- return (1 << CacheWriteBack) | (1 << CacheWriteThrough) | (1 << CacheUncacheable);
- break;
-
- case CacheWriteCombining:
- case CacheWriteProtected:
- return (1 << Ranges[0].Type) | (1 << CacheUncacheable);
- break;
-
- case CacheUncacheable:
- if (RangeCount == 1) {
- return (1 << CacheUncacheable);
- }
- return MtrrLibGetCompatibleTypes (&Ranges[1], RangeCount - 1);
- break;
+ case CacheWriteBack:
+ case CacheWriteThrough:
+ return (1 << CacheWriteBack) | (1 << CacheWriteThrough) | (1 << CacheUncacheable);
+ break;
+
+ case CacheWriteCombining:
+ case CacheWriteProtected:
+ return (1 << Ranges[0].Type) | (1 << CacheUncacheable);
+ break;
+
+ case CacheUncacheable:
+ if (RangeCount == 1) {
+ return (1 << CacheUncacheable);
+ }
- case CacheInvalid:
- default:
- ASSERT (FALSE);
- break;
+ return MtrrLibGetCompatibleTypes (&Ranges[1], RangeCount - 1);
+ break;
+
+ case CacheInvalid:
+ default:
+ ASSERT (FALSE);
+ break;
}
+
return 0;
}
@@ -1839,15 +1942,15 @@ MtrrLibGetCompatibleTypes ( **/
VOID
MtrrLibMergeVariableMtrr (
- MTRR_MEMORY_RANGE *DstMtrrs,
- UINT32 DstMtrrCount,
- MTRR_MEMORY_RANGE *SrcMtrrs,
- UINT32 SrcMtrrCount,
- BOOLEAN *Modified
+ MTRR_MEMORY_RANGE *DstMtrrs,
+ UINT32 DstMtrrCount,
+ MTRR_MEMORY_RANGE *SrcMtrrs,
+ UINT32 SrcMtrrCount,
+ BOOLEAN *Modified
)
{
- UINT32 DstIndex;
- UINT32 SrcIndex;
+ UINT32 DstIndex;
+ UINT32 SrcIndex;
ASSERT (SrcMtrrCount <= DstMtrrCount);
@@ -1857,10 +1960,12 @@ MtrrLibMergeVariableMtrr ( if (DstMtrrs[DstIndex].Length == 0) {
continue;
}
+
for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) {
- if (DstMtrrs[DstIndex].BaseAddress == SrcMtrrs[SrcIndex].BaseAddress &&
- DstMtrrs[DstIndex].Length == SrcMtrrs[SrcIndex].Length &&
- DstMtrrs[DstIndex].Type == SrcMtrrs[SrcIndex].Type) {
+ if ((DstMtrrs[DstIndex].BaseAddress == SrcMtrrs[SrcIndex].BaseAddress) &&
+ (DstMtrrs[DstIndex].Length == SrcMtrrs[SrcIndex].Length) &&
+ (DstMtrrs[DstIndex].Type == SrcMtrrs[SrcIndex].Type))
+ {
break;
}
}
@@ -1870,7 +1975,7 @@ MtrrLibMergeVariableMtrr ( // Remove the one from DstMtrrs which is not in SrcMtrrs
//
DstMtrrs[DstIndex].Length = 0;
- Modified[DstIndex] = TRUE;
+ Modified[DstIndex] = TRUE;
} else {
//
// Remove the one from SrcMtrrs which is also in DstMtrrs
@@ -1886,7 +1991,6 @@ MtrrLibMergeVariableMtrr ( DstIndex = 0;
for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) {
if (SrcMtrrs[SrcIndex].Length != 0) {
-
//
// Find the empty slot in DstMtrrs
//
@@ -1894,8 +1998,10 @@ MtrrLibMergeVariableMtrr ( if (DstMtrrs[DstIndex].Length == 0) {
break;
}
+
DstIndex++;
}
+
ASSERT (DstIndex < DstMtrrCount);
CopyMem (&DstMtrrs[DstIndex], &SrcMtrrs[SrcIndex], sizeof (SrcMtrrs[0]));
Modified[DstIndex] = TRUE;
@@ -1924,27 +2030,27 @@ MtrrLibMergeVariableMtrr ( **/
RETURN_STATUS
MtrrLibSetMemoryRanges (
- IN MTRR_MEMORY_CACHE_TYPE DefaultType,
- IN UINT64 A0,
- IN MTRR_MEMORY_RANGE *Ranges,
- IN UINTN RangeCount,
- IN VOID *Scratch,
- IN OUT UINTN *ScratchSize,
- OUT MTRR_MEMORY_RANGE *VariableMtrr,
- IN UINT32 VariableMtrrCapacity,
- OUT UINT32 *VariableMtrrCount
+ IN MTRR_MEMORY_CACHE_TYPE DefaultType,
+ IN UINT64 A0,
+ IN MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCount,
+ IN VOID *Scratch,
+ IN OUT UINTN *ScratchSize,
+ OUT MTRR_MEMORY_RANGE *VariableMtrr,
+ IN UINT32 VariableMtrrCapacity,
+ OUT UINT32 *VariableMtrrCount
)
{
- RETURN_STATUS Status;
- UINT32 Index;
- UINT64 Base0;
- UINT64 Base1;
- UINT64 Alignment;
- UINT8 CompatibleTypes;
- UINT64 Length;
- UINT32 End;
- UINTN ActualScratchSize;
- UINTN BiggestScratchSize;
+ RETURN_STATUS Status;
+ UINT32 Index;
+ UINT64 Base0;
+ UINT64 Base1;
+ UINT64 Alignment;
+ UINT8 CompatibleTypes;
+ UINT64 Length;
+ UINT32 End;
+ UINTN ActualScratchSize;
+ UINTN BiggestScratchSize;
*VariableMtrrCount = 0;
@@ -1969,21 +2075,26 @@ MtrrLibSetMemoryRanges ( while (Base0 + Alignment <= Ranges[Index].BaseAddress + Ranges[Index].Length) {
if ((BiggestScratchSize <= *ScratchSize) && (Ranges[Index].Type != DefaultType)) {
Status = MtrrLibAppendVariableMtrr (
- VariableMtrr, VariableMtrrCapacity, VariableMtrrCount,
- Base0, Alignment, Ranges[Index].Type
- );
+ VariableMtrr,
+ VariableMtrrCapacity,
+ VariableMtrrCount,
+ Base0,
+ Alignment,
+ Ranges[Index].Type
+ );
if (RETURN_ERROR (Status)) {
return Status;
}
}
- Base0 += Alignment;
+
+ Base0 += Alignment;
Alignment = MtrrLibBiggestAlignment (Base0, A0);
}
//
// Remove the above range from Ranges[Index]
//
- Ranges[Index].Length -= Base0 - Ranges[Index].BaseAddress;
+ Ranges[Index].Length -= Base0 - Ranges[Index].BaseAddress;
Ranges[Index].BaseAddress = Base0;
if (Ranges[Index].Length != 0) {
break;
@@ -2010,8 +2121,10 @@ MtrrLibSetMemoryRanges ( if (((1 << Ranges[End + 1].Type) & CompatibleTypes) == 0) {
break;
}
+
End++;
}
+
Alignment = MtrrLibBiggestAlignment (Base0, A0);
Length = GetPowerOfTwo64 (Ranges[End].BaseAddress + Ranges[End].Length - Base0);
Base1 = Base0 + MIN (Alignment, Length);
@@ -2024,18 +2137,24 @@ MtrrLibSetMemoryRanges ( if (Base1 <= Ranges[End + 1].BaseAddress) {
break;
}
+
End++;
}
- Length = Ranges[End].Length;
+ Length = Ranges[End].Length;
Ranges[End].Length = Base1 - Ranges[End].BaseAddress;
ActualScratchSize = *ScratchSize;
- Status = MtrrLibCalculateMtrrs (
- DefaultType, A0,
- &Ranges[Index], End + 1 - Index,
- Scratch, &ActualScratchSize,
- VariableMtrr, VariableMtrrCapacity, VariableMtrrCount
- );
+ Status = MtrrLibCalculateMtrrs (
+ DefaultType,
+ A0,
+ &Ranges[Index],
+ End + 1 - Index,
+ Scratch,
+ &ActualScratchSize,
+ VariableMtrr,
+ VariableMtrrCapacity,
+ VariableMtrrCount
+ );
if (Status == RETURN_BUFFER_TOO_SMALL) {
BiggestScratchSize = MAX (BiggestScratchSize, ActualScratchSize);
//
@@ -2044,14 +2163,15 @@ MtrrLibSetMemoryRanges ( //
Status = RETURN_SUCCESS;
}
+
if (RETURN_ERROR (Status)) {
return Status;
}
if (Length != Ranges[End].Length) {
Ranges[End].BaseAddress = Base1;
- Ranges[End].Length = Length - Ranges[End].Length;
- Index = End;
+ Ranges[End].Length = Length - Ranges[End].Length;
+ Index = End;
} else {
Index = End + 1;
}
@@ -2061,6 +2181,7 @@ MtrrLibSetMemoryRanges ( *ScratchSize = BiggestScratchSize;
return RETURN_BUFFER_TOO_SMALL;
}
+
return RETURN_SUCCESS;
}
@@ -2080,17 +2201,17 @@ MtrrLibSetMemoryRanges ( **/
RETURN_STATUS
MtrrLibSetBelow1MBMemoryAttribute (
- IN OUT UINT64 *ClearMasks,
- IN OUT UINT64 *OrMasks,
- IN PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN MTRR_MEMORY_CACHE_TYPE Type
+ IN OUT UINT64 *ClearMasks,
+ IN OUT UINT64 *OrMasks,
+ IN PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN MTRR_MEMORY_CACHE_TYPE Type
)
{
- RETURN_STATUS Status;
- UINT32 MsrIndex;
- UINT64 ClearMask;
- UINT64 OrMask;
+ RETURN_STATUS Status;
+ UINT32 MsrIndex;
+ UINT64 ClearMask;
+ UINT64 OrMask;
ASSERT (BaseAddress < BASE_1MB);
@@ -2100,9 +2221,11 @@ MtrrLibSetBelow1MBMemoryAttribute ( if (RETURN_ERROR (Status)) {
return Status;
}
+
ClearMasks[MsrIndex] = ClearMasks[MsrIndex] | ClearMask;
OrMasks[MsrIndex] = (OrMasks[MsrIndex] & ~ClearMask) | OrMask;
}
+
return RETURN_SUCCESS;
}
@@ -2135,39 +2258,39 @@ MtrrLibSetBelow1MBMemoryAttribute ( RETURN_STATUS
EFIAPI
MtrrSetMemoryAttributesInMtrrSettings (
- IN OUT MTRR_SETTINGS *MtrrSetting,
- IN VOID *Scratch,
- IN OUT UINTN *ScratchSize,
- IN CONST MTRR_MEMORY_RANGE *Ranges,
- IN UINTN RangeCount
+ IN OUT MTRR_SETTINGS *MtrrSetting,
+ IN VOID *Scratch,
+ IN OUT UINTN *ScratchSize,
+ IN CONST MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCount
)
{
- RETURN_STATUS Status;
- UINT32 Index;
- UINT64 BaseAddress;
- UINT64 Length;
- BOOLEAN Above1MbExist;
-
- UINT64 MtrrValidBitsMask;
- UINT64 MtrrValidAddressMask;
- MTRR_MEMORY_CACHE_TYPE DefaultType;
- MTRR_VARIABLE_SETTINGS VariableSettings;
- MTRR_MEMORY_RANGE WorkingRanges[2 * ARRAY_SIZE (MtrrSetting->Variables.Mtrr) + 2];
- UINTN WorkingRangeCount;
- BOOLEAN Modified;
- MTRR_VARIABLE_SETTING VariableSetting;
- UINT32 OriginalVariableMtrrCount;
- UINT32 FirmwareVariableMtrrCount;
- UINT32 WorkingVariableMtrrCount;
- MTRR_MEMORY_RANGE OriginalVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
- MTRR_MEMORY_RANGE WorkingVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
- BOOLEAN VariableSettingModified[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
-
- UINT64 ClearMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];
- UINT64 OrMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];
-
- MTRR_CONTEXT MtrrContext;
- BOOLEAN MtrrContextValid;
+ RETURN_STATUS Status;
+ UINT32 Index;
+ UINT64 BaseAddress;
+ UINT64 Length;
+ BOOLEAN Above1MbExist;
+
+ UINT64 MtrrValidBitsMask;
+ UINT64 MtrrValidAddressMask;
+ MTRR_MEMORY_CACHE_TYPE DefaultType;
+ MTRR_VARIABLE_SETTINGS VariableSettings;
+ MTRR_MEMORY_RANGE WorkingRanges[2 * ARRAY_SIZE (MtrrSetting->Variables.Mtrr) + 2];
+ UINTN WorkingRangeCount;
+ BOOLEAN Modified;
+ MTRR_VARIABLE_SETTING VariableSetting;
+ UINT32 OriginalVariableMtrrCount;
+ UINT32 FirmwareVariableMtrrCount;
+ UINT32 WorkingVariableMtrrCount;
+ MTRR_MEMORY_RANGE OriginalVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
+ MTRR_MEMORY_RANGE WorkingVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
+ BOOLEAN VariableSettingModified[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];
+
+ UINT64 ClearMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];
+ UINT64 OrMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];
+
+ MTRR_CONTEXT MtrrContext;
+ BOOLEAN MtrrContextValid;
Status = RETURN_SUCCESS;
MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);
@@ -2187,16 +2310,23 @@ MtrrSetMemoryAttributesInMtrrSettings ( // 0. Dump the requests.
//
DEBUG_CODE_BEGIN ();
- DEBUG ((DEBUG_CACHE, "Mtrr: Set Mem Attribute to %a, ScratchSize = %x%a",
- (MtrrSetting == NULL) ? "Hardware" : "Buffer", *ScratchSize,
- (RangeCount <= 1) ? "," : "\n"
- ));
- for (Index = 0; Index < RangeCount; Index++) {
- DEBUG ((DEBUG_CACHE, " %a: [%016lx, %016lx)\n",
- mMtrrMemoryCacheTypeShortName[MIN (Ranges[Index].Type, CacheInvalid)],
- Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length
- ));
- }
+ DEBUG ((
+ DEBUG_CACHE,
+ "Mtrr: Set Mem Attribute to %a, ScratchSize = %x%a",
+ (MtrrSetting == NULL) ? "Hardware" : "Buffer",
+ *ScratchSize,
+ (RangeCount <= 1) ? "," : "\n"
+ ));
+ for (Index = 0; Index < RangeCount; Index++) {
+ DEBUG ((
+ DEBUG_CACHE,
+ " %a: [%016lx, %016lx)\n",
+ mMtrrMemoryCacheTypeShortName[MIN (Ranges[Index].Type, CacheInvalid)],
+ Ranges[Index].BaseAddress,
+ Ranges[Index].BaseAddress + Ranges[Index].Length
+ ));
+ }
+
DEBUG_CODE_END ();
//
@@ -2212,10 +2342,12 @@ MtrrSetMemoryAttributesInMtrrSettings ( Status = RETURN_INVALID_PARAMETER;
goto Exit;
}
+
if (((Ranges[Index].BaseAddress & ~MtrrValidAddressMask) != 0) ||
((((Ranges[Index].BaseAddress + Ranges[Index].Length) & ~MtrrValidAddressMask) != 0) &&
- (Ranges[Index].BaseAddress + Ranges[Index].Length) != MtrrValidBitsMask + 1)
- ) {
+ ((Ranges[Index].BaseAddress + Ranges[Index].Length) != MtrrValidBitsMask + 1))
+ )
+ {
//
// Either the BaseAddress or the Limit doesn't follow the alignment requirement.
// Note: It's still valid if Limit doesn't follow the alignment requirement but equals to MAX Address.
@@ -2223,14 +2355,17 @@ MtrrSetMemoryAttributesInMtrrSettings ( Status = RETURN_UNSUPPORTED;
goto Exit;
}
+
if ((Ranges[Index].Type != CacheUncacheable) &&
(Ranges[Index].Type != CacheWriteCombining) &&
(Ranges[Index].Type != CacheWriteThrough) &&
(Ranges[Index].Type != CacheWriteProtected) &&
- (Ranges[Index].Type != CacheWriteBack)) {
+ (Ranges[Index].Type != CacheWriteBack))
+ {
Status = RETURN_INVALID_PARAMETER;
goto Exit;
}
+
if (Ranges[Index].BaseAddress + Ranges[Index].Length > BASE_1MB) {
Above1MbExist = TRUE;
}
@@ -2246,19 +2381,26 @@ MtrrSetMemoryAttributesInMtrrSettings ( OriginalVariableMtrrCount = GetVariableMtrrCountWorker ();
MtrrGetVariableMtrrWorker (MtrrSetting, OriginalVariableMtrrCount, &VariableSettings);
MtrrLibGetRawVariableRanges (
- &VariableSettings, OriginalVariableMtrrCount,
- MtrrValidBitsMask, MtrrValidAddressMask, OriginalVariableMtrr
+ &VariableSettings,
+ OriginalVariableMtrrCount,
+ MtrrValidBitsMask,
+ MtrrValidAddressMask,
+ OriginalVariableMtrr
);
- DefaultType = MtrrGetDefaultMemoryTypeWorker (MtrrSetting);
- WorkingRangeCount = 1;
+ DefaultType = MtrrGetDefaultMemoryTypeWorker (MtrrSetting);
+ WorkingRangeCount = 1;
WorkingRanges[0].BaseAddress = 0;
WorkingRanges[0].Length = MtrrValidBitsMask + 1;
WorkingRanges[0].Type = DefaultType;
Status = MtrrLibApplyVariableMtrrs (
- OriginalVariableMtrr, OriginalVariableMtrrCount,
- WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount);
+ OriginalVariableMtrr,
+ OriginalVariableMtrrCount,
+ WorkingRanges,
+ ARRAY_SIZE (WorkingRanges),
+ &WorkingRangeCount
+ );
ASSERT_RETURN_ERROR (Status);
ASSERT (OriginalVariableMtrrCount >= PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs));
@@ -2269,8 +2411,12 @@ MtrrSetMemoryAttributesInMtrrSettings ( // 2.2. Force [0, 1M) to UC, so that it doesn't impact subtraction algorithm.
//
Status = MtrrLibSetMemoryType (
- WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount,
- 0, SIZE_1MB, CacheUncacheable
+ WorkingRanges,
+ ARRAY_SIZE (WorkingRanges),
+ &WorkingRangeCount,
+ 0,
+ SIZE_1MB,
+ CacheUncacheable
);
ASSERT (Status != RETURN_OUT_OF_RESOURCES);
@@ -2280,17 +2426,23 @@ MtrrSetMemoryAttributesInMtrrSettings ( Modified = FALSE;
for (Index = 0; Index < RangeCount; Index++) {
BaseAddress = Ranges[Index].BaseAddress;
- Length = Ranges[Index].Length;
+ Length = Ranges[Index].Length;
if (BaseAddress < BASE_1MB) {
if (Length <= BASE_1MB - BaseAddress) {
continue;
}
- Length -= BASE_1MB - BaseAddress;
+
+ Length -= BASE_1MB - BaseAddress;
BaseAddress = BASE_1MB;
}
+
Status = MtrrLibSetMemoryType (
- WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount,
- BaseAddress, Length, Ranges[Index].Type
+ WorkingRanges,
+ ARRAY_SIZE (WorkingRanges),
+ &WorkingRangeCount,
+ BaseAddress,
+ Length,
+ Ranges[Index].Type
);
if (Status == RETURN_ALREADY_STARTED) {
Status = RETURN_SUCCESS;
@@ -2308,9 +2460,15 @@ MtrrSetMemoryAttributesInMtrrSettings ( // Buffer Too Small may be returned if the scratch buffer size is insufficient.
//
Status = MtrrLibSetMemoryRanges (
- DefaultType, LShiftU64 (1, (UINTN)HighBitSet64 (MtrrValidBitsMask)), WorkingRanges, WorkingRangeCount,
- Scratch, ScratchSize,
- WorkingVariableMtrr, FirmwareVariableMtrrCount + 1, &WorkingVariableMtrrCount
+ DefaultType,
+ LShiftU64 (1, (UINTN)HighBitSet64 (MtrrValidBitsMask)),
+ WorkingRanges,
+ WorkingRangeCount,
+ Scratch,
+ ScratchSize,
+ WorkingVariableMtrr,
+ FirmwareVariableMtrrCount + 1,
+ &WorkingVariableMtrrCount
);
if (RETURN_ERROR (Status)) {
goto Exit;
@@ -2320,11 +2478,12 @@ MtrrSetMemoryAttributesInMtrrSettings ( // 2.5. Remove the [0, 1MB) MTRR if it still exists (not merged with other range)
//
for (Index = 0; Index < WorkingVariableMtrrCount; Index++) {
- if (WorkingVariableMtrr[Index].BaseAddress == 0 && WorkingVariableMtrr[Index].Length == SIZE_1MB) {
+ if ((WorkingVariableMtrr[Index].BaseAddress == 0) && (WorkingVariableMtrr[Index].Length == SIZE_1MB)) {
ASSERT (WorkingVariableMtrr[Index].Type == CacheUncacheable);
WorkingVariableMtrrCount--;
CopyMem (
- &WorkingVariableMtrr[Index], &WorkingVariableMtrr[Index + 1],
+ &WorkingVariableMtrr[Index],
+ &WorkingVariableMtrr[Index + 1],
(WorkingVariableMtrrCount - Index) * sizeof (WorkingVariableMtrr[0])
);
break;
@@ -2341,10 +2500,12 @@ MtrrSetMemoryAttributesInMtrrSettings ( // Make sure least modification is made to OriginalVariableMtrr.
//
MtrrLibMergeVariableMtrr (
- OriginalVariableMtrr, OriginalVariableMtrrCount,
- WorkingVariableMtrr, WorkingVariableMtrrCount,
+ OriginalVariableMtrr,
+ OriginalVariableMtrrCount,
+ WorkingVariableMtrr,
+ WorkingVariableMtrrCount,
VariableSettingModified
- );
+ );
}
}
@@ -2361,8 +2522,11 @@ MtrrSetMemoryAttributesInMtrrSettings ( }
Status = MtrrLibSetBelow1MBMemoryAttribute (
- ClearMasks, OrMasks,
- Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type
+ ClearMasks,
+ OrMasks,
+ Ranges[Index].BaseAddress,
+ Ranges[Index].Length,
+ Ranges[Index].Type
);
if (RETURN_ERROR (Status)) {
goto Exit;
@@ -2382,6 +2546,7 @@ MtrrSetMemoryAttributesInMtrrSettings ( MtrrLibPreMtrrChange (&MtrrContext);
MtrrContextValid = TRUE;
}
+
AsmMsrAndThenOr64 (mMtrrLibFixedMtrrTable[Index].Msr, ~ClearMasks[Index], OrMasks[Index]);
}
}
@@ -2394,12 +2559,13 @@ MtrrSetMemoryAttributesInMtrrSettings ( if (VariableSettingModified[Index]) {
if (OriginalVariableMtrr[Index].Length != 0) {
VariableSetting.Base = (OriginalVariableMtrr[Index].BaseAddress & MtrrValidAddressMask)
- | (UINT8)OriginalVariableMtrr[Index].Type;
+ | (UINT8)OriginalVariableMtrr[Index].Type;
VariableSetting.Mask = ((~(OriginalVariableMtrr[Index].Length - 1)) & MtrrValidAddressMask) | BIT11;
} else {
VariableSetting.Base = 0;
VariableSetting.Mask = 0;
}
+
if (MtrrSetting != NULL) {
CopyMem (&MtrrSetting->Variables.Mtrr[Index], &VariableSetting, sizeof (VariableSetting));
} else {
@@ -2407,20 +2573,21 @@ MtrrSetMemoryAttributesInMtrrSettings ( MtrrLibPreMtrrChange (&MtrrContext);
MtrrContextValid = TRUE;
}
+
AsmWriteMsr64 (
MSR_IA32_MTRR_PHYSBASE0 + (Index << 1),
VariableSetting.Base
- );
+ );
AsmWriteMsr64 (
MSR_IA32_MTRR_PHYSMASK0 + (Index << 1),
VariableSetting.Mask
- );
+ );
}
}
}
if (MtrrSetting != NULL) {
- ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.E = 1;
+ ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.E = 1;
((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.FE = 1;
} else {
if (MtrrContextValid) {
@@ -2433,6 +2600,7 @@ Exit: if (!RETURN_ERROR (Status)) {
MtrrDebugPrintAllMtrrsWorker (MtrrSetting);
}
+
return Status;
}
@@ -2474,14 +2642,14 @@ MtrrSetMemoryAttributeInMtrrSettings ( IN MTRR_MEMORY_CACHE_TYPE Attribute
)
{
- UINT8 Scratch[SCRATCH_BUFFER_SIZE];
- UINTN ScratchSize;
- MTRR_MEMORY_RANGE Range;
+ UINT8 Scratch[SCRATCH_BUFFER_SIZE];
+ UINTN ScratchSize;
+ MTRR_MEMORY_RANGE Range;
Range.BaseAddress = BaseAddress;
Range.Length = Length;
Range.Type = Attribute;
- ScratchSize = sizeof (Scratch);
+ ScratchSize = sizeof (Scratch);
return MtrrSetMemoryAttributesInMtrrSettings (MtrrSetting, Scratch, &ScratchSize, &Range, 1);
}
@@ -2537,7 +2705,7 @@ MtrrSetMemoryAttribute ( **/
VOID
MtrrSetVariableMtrrWorker (
- IN MTRR_VARIABLE_SETTINGS *VariableSettings
+ IN MTRR_VARIABLE_SETTINGS *VariableSettings
)
{
UINT32 Index;
@@ -2566,20 +2734,19 @@ MtrrSetVariableMtrrWorker ( **/
VOID
MtrrSetFixedMtrrWorker (
- IN MTRR_FIXED_SETTINGS *FixedSettings
+ IN MTRR_FIXED_SETTINGS *FixedSettings
)
{
UINT32 Index;
for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {
- AsmWriteMsr64 (
- mMtrrLibFixedMtrrTable[Index].Msr,
- FixedSettings->Mtrr[Index]
- );
+ AsmWriteMsr64 (
+ mMtrrLibFixedMtrrTable[Index].Msr,
+ FixedSettings->Mtrr[Index]
+ );
}
}
-
/**
This function gets the content in all MTRRs (variable and fixed)
@@ -2591,7 +2758,7 @@ MtrrSetFixedMtrrWorker ( MTRR_SETTINGS *
EFIAPI
MtrrGetAllMtrrs (
- OUT MTRR_SETTINGS *MtrrSetting
+ OUT MTRR_SETTINGS *MtrrSetting
)
{
if (!IsMtrrSupported ()) {
@@ -2620,7 +2787,6 @@ MtrrGetAllMtrrs ( return MtrrSetting;
}
-
/**
This function sets all MTRRs (variable and fixed)
@@ -2632,7 +2798,7 @@ MtrrGetAllMtrrs ( MTRR_SETTINGS *
EFIAPI
MtrrSetAllMtrrs (
- IN MTRR_SETTINGS *MtrrSetting
+ IN MTRR_SETTINGS *MtrrSetting
)
{
MTRR_CONTEXT MtrrContext;
@@ -2663,7 +2829,6 @@ MtrrSetAllMtrrs ( return MtrrSetting;
}
-
/**
Checks if MTRR is supported.
@@ -2677,8 +2842,8 @@ IsMtrrSupported ( VOID
)
{
- CPUID_VERSION_INFO_EDX Edx;
- MSR_IA32_MTRRCAP_REGISTER MtrrCap;
+ CPUID_VERSION_INFO_EDX Edx;
+ MSR_IA32_MTRRCAP_REGISTER MtrrCap;
//
// Check CPUID(1).EDX[12] for MTRR capability
@@ -2697,10 +2862,10 @@ IsMtrrSupported ( if ((MtrrCap.Bits.VCNT == 0) || (MtrrCap.Bits.FIX == 0)) {
return FALSE;
}
+
return TRUE;
}
-
/**
Worker function prints all MTRRs for debugging.
@@ -2712,93 +2877,109 @@ IsMtrrSupported ( **/
VOID
MtrrDebugPrintAllMtrrsWorker (
- IN MTRR_SETTINGS *MtrrSetting
+ IN MTRR_SETTINGS *MtrrSetting
)
{
DEBUG_CODE_BEGIN ();
- MTRR_SETTINGS LocalMtrrs;
- MTRR_SETTINGS *Mtrrs;
- UINTN Index;
- UINTN RangeCount;
- UINT64 MtrrValidBitsMask;
- UINT64 MtrrValidAddressMask;
- UINT32 VariableMtrrCount;
- BOOLEAN ContainVariableMtrr;
- MTRR_MEMORY_RANGE Ranges[
- ARRAY_SIZE (mMtrrLibFixedMtrrTable) * sizeof (UINT64) + 2 * ARRAY_SIZE (Mtrrs->Variables.Mtrr) + 1
- ];
- MTRR_MEMORY_RANGE RawVariableRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];
-
- if (!IsMtrrSupported ()) {
- return;
- }
+ MTRR_SETTINGS LocalMtrrs;
+ MTRR_SETTINGS *Mtrrs;
+ UINTN Index;
+ UINTN RangeCount;
+ UINT64 MtrrValidBitsMask;
+ UINT64 MtrrValidAddressMask;
+ UINT32 VariableMtrrCount;
+ BOOLEAN ContainVariableMtrr;
+ MTRR_MEMORY_RANGE Ranges[
+ ARRAY_SIZE (mMtrrLibFixedMtrrTable) * sizeof (UINT64) + 2 * ARRAY_SIZE (Mtrrs->Variables.Mtrr) + 1
+ ];
+ MTRR_MEMORY_RANGE RawVariableRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];
- VariableMtrrCount = GetVariableMtrrCountWorker ();
+ if (!IsMtrrSupported ()) {
+ return;
+ }
- if (MtrrSetting != NULL) {
- Mtrrs = MtrrSetting;
- } else {
- MtrrGetAllMtrrs (&LocalMtrrs);
- Mtrrs = &LocalMtrrs;
- }
+ VariableMtrrCount = GetVariableMtrrCountWorker ();
- //
- // Dump RAW MTRR contents
- //
- DEBUG ((DEBUG_CACHE, "MTRR Settings:\n"));
- DEBUG ((DEBUG_CACHE, "=============\n"));
- DEBUG ((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType));
- for (Index = 0; Index < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Index++) {
- DEBUG ((DEBUG_CACHE, "Fixed MTRR[%02d] : %016lx\n", Index, Mtrrs->Fixed.Mtrr[Index]));
- }
- ContainVariableMtrr = FALSE;
- for (Index = 0; Index < VariableMtrrCount; Index++) {
- if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) {
- //
- // If mask is not valid, then do not display range
- //
- continue;
- }
- ContainVariableMtrr = TRUE;
- DEBUG ((DEBUG_CACHE, "Variable MTRR[%02d]: Base=%016lx Mask=%016lx\n",
- Index,
- Mtrrs->Variables.Mtrr[Index].Base,
- Mtrrs->Variables.Mtrr[Index].Mask
- ));
- }
- if (!ContainVariableMtrr) {
- DEBUG ((DEBUG_CACHE, "Variable MTRR : None.\n"));
+ if (MtrrSetting != NULL) {
+ Mtrrs = MtrrSetting;
+ } else {
+ MtrrGetAllMtrrs (&LocalMtrrs);
+ Mtrrs = &LocalMtrrs;
+ }
+
+ //
+ // Dump RAW MTRR contents
+ //
+ DEBUG ((DEBUG_CACHE, "MTRR Settings:\n"));
+ DEBUG ((DEBUG_CACHE, "=============\n"));
+ DEBUG ((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType));
+ for (Index = 0; Index < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Index++) {
+ DEBUG ((DEBUG_CACHE, "Fixed MTRR[%02d] : %016lx\n", Index, Mtrrs->Fixed.Mtrr[Index]));
+ }
+
+ ContainVariableMtrr = FALSE;
+ for (Index = 0; Index < VariableMtrrCount; Index++) {
+ if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) {
+ //
+ // If mask is not valid, then do not display range
+ //
+ continue;
}
- DEBUG((DEBUG_CACHE, "\n"));
- //
- // Dump MTRR setting in ranges
- //
- DEBUG((DEBUG_CACHE, "Memory Ranges:\n"));
- DEBUG((DEBUG_CACHE, "====================================\n"));
- MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);
- Ranges[0].BaseAddress = 0;
- Ranges[0].Length = MtrrValidBitsMask + 1;
- Ranges[0].Type = MtrrGetDefaultMemoryTypeWorker (Mtrrs);
- RangeCount = 1;
+ ContainVariableMtrr = TRUE;
+ DEBUG ((
+ DEBUG_CACHE,
+ "Variable MTRR[%02d]: Base=%016lx Mask=%016lx\n",
+ Index,
+ Mtrrs->Variables.Mtrr[Index].Base,
+ Mtrrs->Variables.Mtrr[Index].Mask
+ ));
+ }
- MtrrLibGetRawVariableRanges (
- &Mtrrs->Variables, VariableMtrrCount,
- MtrrValidBitsMask, MtrrValidAddressMask, RawVariableRanges
- );
- MtrrLibApplyVariableMtrrs (
- RawVariableRanges, VariableMtrrCount,
- Ranges, ARRAY_SIZE (Ranges), &RangeCount
- );
+ if (!ContainVariableMtrr) {
+ DEBUG ((DEBUG_CACHE, "Variable MTRR : None.\n"));
+ }
- MtrrLibApplyFixedMtrrs (&Mtrrs->Fixed, Ranges, ARRAY_SIZE (Ranges), &RangeCount);
+ DEBUG ((DEBUG_CACHE, "\n"));
+
+ //
+ // Dump MTRR setting in ranges
+ //
+ DEBUG ((DEBUG_CACHE, "Memory Ranges:\n"));
+ DEBUG ((DEBUG_CACHE, "====================================\n"));
+ MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);
+ Ranges[0].BaseAddress = 0;
+ Ranges[0].Length = MtrrValidBitsMask + 1;
+ Ranges[0].Type = MtrrGetDefaultMemoryTypeWorker (Mtrrs);
+ RangeCount = 1;
+
+ MtrrLibGetRawVariableRanges (
+ &Mtrrs->Variables,
+ VariableMtrrCount,
+ MtrrValidBitsMask,
+ MtrrValidAddressMask,
+ RawVariableRanges
+ );
+ MtrrLibApplyVariableMtrrs (
+ RawVariableRanges,
+ VariableMtrrCount,
+ Ranges,
+ ARRAY_SIZE (Ranges),
+ &RangeCount
+ );
+
+ MtrrLibApplyFixedMtrrs (&Mtrrs->Fixed, Ranges, ARRAY_SIZE (Ranges), &RangeCount);
+
+ for (Index = 0; Index < RangeCount; Index++) {
+ DEBUG ((
+ DEBUG_CACHE,
+ "%a:%016lx-%016lx\n",
+ mMtrrMemoryCacheTypeShortName[Ranges[Index].Type],
+ Ranges[Index].BaseAddress,
+ Ranges[Index].BaseAddress + Ranges[Index].Length - 1
+ ));
+ }
- for (Index = 0; Index < RangeCount; Index++) {
- DEBUG ((DEBUG_CACHE, "%a:%016lx-%016lx\n",
- mMtrrMemoryCacheTypeShortName[Ranges[Index].Type],
- Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length - 1
- ));
- }
DEBUG_CODE_END ();
}
diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c index e84b939060..b9a97dee09 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c @@ -8,11 +8,11 @@ #include "MtrrLibUnitTest.h"
-STATIC CONST MTRR_LIB_SYSTEM_PARAMETER mDefaultSystemParameter = {
+STATIC CONST MTRR_LIB_SYSTEM_PARAMETER mDefaultSystemParameter = {
42, TRUE, TRUE, CacheUncacheable, 12
};
-STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = {
+STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = {
{ 38, TRUE, TRUE, CacheUncacheable, 12 },
{ 38, TRUE, TRUE, CacheWriteBack, 12 },
{ 38, TRUE, TRUE, CacheWriteThrough, 12 },
@@ -32,7 +32,7 @@ STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = { { 48, TRUE, TRUE, CacheWriteCombining, 12 },
};
-UINT32 mFixedMtrrsIndex[] = {
+UINT32 mFixedMtrrsIndex[] = {
MSR_IA32_MTRR_FIX64K_00000,
MSR_IA32_MTRR_FIX16K_80000,
MSR_IA32_MTRR_FIX16K_A0000,
@@ -54,18 +54,18 @@ STATIC_ASSERT ( // Context structure to be used for most of the test cases.
//
typedef struct {
- CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
+ CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
} MTRR_LIB_TEST_CONTEXT;
//
// Context structure to be used for GetFirmwareVariableMtrrCount() test.
//
typedef struct {
- UINT32 NumberOfReservedVariableMtrrs;
- CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
+ UINT32 NumberOfReservedVariableMtrrs;
+ CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
} MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT;
-STATIC CHAR8 *mCacheDescription[] = { "UC", "WC", "N/A", "N/A", "WT", "WP", "WB" };
+STATIC CHAR8 *mCacheDescription[] = { "UC", "WC", "N/A", "N/A", "WT", "WP", "WB" };
/**
Compare the actual memory ranges against expected memory ranges and return PASS when they match.
@@ -87,6 +87,7 @@ VerifyMemoryRanges ( )
{
UINTN Index;
+
UT_ASSERT_EQUAL (ExpectedMemoryRangeCount, ActualRangeCount);
for (Index = 0; Index < ExpectedMemoryRangeCount; Index++) {
UT_ASSERT_EQUAL (ExpectedMemoryRanges[Index].BaseAddress, ActualRanges[Index].BaseAddress);
@@ -105,11 +106,12 @@ VerifyMemoryRanges ( **/
VOID
DumpMemoryRanges (
- MTRR_MEMORY_RANGE *Ranges,
- UINTN RangeCount
+ MTRR_MEMORY_RANGE *Ranges,
+ UINTN RangeCount
)
{
- UINTN Index;
+ UINTN Index;
+
for (Index = 0; Index < RangeCount; Index++) {
UT_LOG_INFO ("\t{ 0x%016llx, 0x%016llx, %a },\n", Ranges[Index].BaseAddress, Ranges[Index].Length, mCacheDescription[Ranges[Index].Type]);
}
@@ -130,17 +132,17 @@ DumpMemoryRanges ( **/
VOID
GenerateRandomMemoryTypeCombination (
- IN UINT32 TotalCount,
- OUT UINT32 *UcCount,
- OUT UINT32 *WtCount,
- OUT UINT32 *WbCount,
- OUT UINT32 *WpCount,
- OUT UINT32 *WcCount
+ IN UINT32 TotalCount,
+ OUT UINT32 *UcCount,
+ OUT UINT32 *WtCount,
+ OUT UINT32 *WbCount,
+ OUT UINT32 *WpCount,
+ OUT UINT32 *WcCount
)
{
- UINTN Index;
- UINT32 TotalMtrrCount;
- UINT32 *CountPerType[5];
+ UINTN Index;
+ UINT32 TotalMtrrCount;
+ UINT32 *CountPerType[5];
CountPerType[0] = UcCount;
CountPerType[1] = WtCount;
@@ -183,38 +185,47 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( IN UNIT_TEST_CONTEXT Context
)
{
- CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
- RETURN_STATUS Status;
- UINT32 UcCount;
- UINT32 WtCount;
- UINT32 WbCount;
- UINT32 WpCount;
- UINT32 WcCount;
-
- UINT32 MtrrIndex;
- UINT8 *Scratch;
- UINTN ScratchSize;
- MTRR_SETTINGS LocalMtrrs;
-
- MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR];
- MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
- UINT32 ExpectedVariableMtrrUsage;
- UINTN ExpectedMemoryRangesCount;
-
- MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
- UINT32 ActualVariableMtrrUsage;
- UINTN ActualMemoryRangesCount;
-
- MTRR_SETTINGS *Mtrrs[2];
-
- SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context;
+ CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
+ RETURN_STATUS Status;
+ UINT32 UcCount;
+ UINT32 WtCount;
+ UINT32 WbCount;
+ UINT32 WpCount;
+ UINT32 WcCount;
+
+ UINT32 MtrrIndex;
+ UINT8 *Scratch;
+ UINTN ScratchSize;
+ MTRR_SETTINGS LocalMtrrs;
+
+ MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR];
+ MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
+ UINT32 ExpectedVariableMtrrUsage;
+ UINTN ExpectedMemoryRangesCount;
+
+ MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
+ UINT32 ActualVariableMtrrUsage;
+ UINTN ActualMemoryRangesCount;
+
+ MTRR_SETTINGS *Mtrrs[2];
+
+ SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
GenerateRandomMemoryTypeCombination (
SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs),
- &UcCount, &WtCount, &WbCount, &WpCount, &WcCount
+ &UcCount,
+ &WtCount,
+ &WbCount,
+ &WpCount,
+ &WcCount
);
GenerateValidAndConfigurableMtrrPairs (
- SystemParameter->PhysicalAddressBits, RawMtrrRange,
- UcCount, WtCount, WbCount, WpCount, WcCount
+ SystemParameter->PhysicalAddressBits,
+ RawMtrrRange,
+ UcCount,
+ WtCount,
+ WbCount,
+ WpCount,
+ WcCount
);
ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount;
@@ -222,13 +233,20 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( GetEffectiveMemoryRanges (
SystemParameter->DefaultCacheType,
SystemParameter->PhysicalAddressBits,
- RawMtrrRange, ExpectedVariableMtrrUsage,
- ExpectedMemoryRanges, &ExpectedMemoryRangesCount
+ RawMtrrRange,
+ ExpectedVariableMtrrUsage,
+ ExpectedMemoryRanges,
+ &ExpectedMemoryRangesCount
);
UT_LOG_INFO (
"Total MTRR [%d]: UC=%d, WT=%d, WB=%d, WP=%d, WC=%d\n",
- ExpectedVariableMtrrUsage, UcCount, WtCount, WbCount, WpCount, WcCount
+ ExpectedVariableMtrrUsage,
+ UcCount,
+ WtCount,
+ WbCount,
+ WpCount,
+ WcCount
);
UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount);
DumpMemoryRanges (ExpectedMemoryRanges, ExpectedMemoryRangesCount);
@@ -244,21 +262,28 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( for (MtrrIndex = 0; MtrrIndex < ARRAY_SIZE (Mtrrs); MtrrIndex++) {
Scratch = calloc (ScratchSize, sizeof (UINT8));
- Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);
+ Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);
if (Status == RETURN_BUFFER_TOO_SMALL) {
Scratch = realloc (Scratch, ScratchSize);
- Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);
+ Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);
}
+
UT_ASSERT_STATUS_EQUAL (Status, RETURN_SUCCESS);
if (Mtrrs[MtrrIndex] == NULL) {
ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs));
MtrrGetAllMtrrs (&LocalMtrrs);
}
+
ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
CollectTestResult (
- SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount,
- &LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage
+ SystemParameter->DefaultCacheType,
+ SystemParameter->PhysicalAddressBits,
+ SystemParameter->VariableMtrrCount,
+ &LocalMtrrs,
+ ActualMemoryRanges,
+ &ActualMemoryRangesCount,
+ &ActualVariableMtrrUsage
);
UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount);
@@ -284,20 +309,20 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings ( UNIT_TEST_STATUS
EFIAPI
UnitTestInvalidMemoryLayouts (
- IN UNIT_TEST_CONTEXT Context
+ IN UNIT_TEST_CONTEXT Context
)
{
- CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
- MTRR_MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR * 2 + 1];
- UINTN RangeCount;
- UINT64 MaxAddress;
- UINT32 Index;
- UINT64 BaseAddress;
- UINT64 Length;
- RETURN_STATUS Status;
- UINTN ScratchSize;
-
- SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context;
+ CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
+ MTRR_MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR * 2 + 1];
+ UINTN RangeCount;
+ UINT64 MaxAddress;
+ UINT32 Index;
+ UINT64 BaseAddress;
+ UINT64 Length;
+ RETURN_STATUS Status;
+ UINTN ScratchSize;
+
+ SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
RangeCount = Random32 (1, ARRAY_SIZE (Ranges));
MaxAddress = 1ull << SystemParameter->PhysicalAddressBits;
@@ -313,13 +338,15 @@ UnitTestInvalidMemoryLayouts ( Ranges[Index].Type = GenerateRandomCacheType ();
Status = MtrrSetMemoryAttribute (
- Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type
- );
+ Ranges[Index].BaseAddress,
+ Ranges[Index].Length,
+ Ranges[Index].Type
+ );
UT_ASSERT_TRUE (RETURN_ERROR (Status));
}
ScratchSize = 0;
- Status = MtrrSetMemoryAttributesInMtrrSettings (NULL, NULL, &ScratchSize, Ranges, RangeCount);
+ Status = MtrrSetMemoryAttributesInMtrrSettings (NULL, NULL, &ScratchSize, Ranges, RangeCount);
UT_ASSERT_TRUE (RETURN_ERROR (Status));
return UNIT_TEST_PASSED;
@@ -344,7 +371,7 @@ UnitTestIsMtrrSupported ( MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_TEST_CONTEXT *LocalContext;
- LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;
+ LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
//
@@ -357,8 +384,8 @@ UnitTestIsMtrrSupported ( //
// MTRR capability on in CPUID leaf, but no variable or fixed MTRRs.
//
- SystemParameter.MtrrSupported = TRUE;
- SystemParameter.VariableMtrrCount = 0;
+ SystemParameter.MtrrSupported = TRUE;
+ SystemParameter.VariableMtrrCount = 0;
SystemParameter.FixedMtrrSupported = FALSE;
InitializeMtrrRegs (&SystemParameter);
UT_ASSERT_FALSE (IsMtrrSupported ());
@@ -366,8 +393,8 @@ UnitTestIsMtrrSupported ( //
// MTRR capability on in CPUID leaf, but no variable MTRRs.
//
- SystemParameter.MtrrSupported = TRUE;
- SystemParameter.VariableMtrrCount = 0;
+ SystemParameter.MtrrSupported = TRUE;
+ SystemParameter.VariableMtrrCount = 0;
SystemParameter.FixedMtrrSupported = TRUE;
InitializeMtrrRegs (&SystemParameter);
UT_ASSERT_FALSE (IsMtrrSupported ());
@@ -375,8 +402,8 @@ UnitTestIsMtrrSupported ( //
// MTRR capability on in CPUID leaf, but no fixed MTRRs.
//
- SystemParameter.MtrrSupported = TRUE;
- SystemParameter.VariableMtrrCount = 7;
+ SystemParameter.MtrrSupported = TRUE;
+ SystemParameter.VariableMtrrCount = 7;
SystemParameter.FixedMtrrSupported = FALSE;
InitializeMtrrRegs (&SystemParameter);
UT_ASSERT_FALSE (IsMtrrSupported ());
@@ -384,8 +411,8 @@ UnitTestIsMtrrSupported ( //
// MTRR capability on in CPUID leaf with both variable and fixed MTRRs.
//
- SystemParameter.MtrrSupported = TRUE;
- SystemParameter.VariableMtrrCount = 7;
+ SystemParameter.MtrrSupported = TRUE;
+ SystemParameter.VariableMtrrCount = 7;
SystemParameter.FixedMtrrSupported = TRUE;
InitializeMtrrRegs (&SystemParameter);
UT_ASSERT_TRUE (IsMtrrSupported ());
@@ -409,11 +436,11 @@ UnitTestGetVariableMtrrCount ( IN UNIT_TEST_CONTEXT Context
)
{
- UINT32 Result;
- MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
- MTRR_LIB_TEST_CONTEXT *LocalContext;
+ UINT32 Result;
+ MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
+ MTRR_LIB_TEST_CONTEXT *LocalContext;
- LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;
+ LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
//
@@ -445,7 +472,7 @@ UnitTestGetVariableMtrrCount ( InitializeMtrrRegs (&SystemParameter);
UT_EXPECT_ASSERT_FAILURE (GetVariableMtrrCount (), NULL);
- SystemParameter.MtrrSupported = TRUE;
+ SystemParameter.MtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = MAX_UINT8;
InitializeMtrrRegs (&SystemParameter);
UT_EXPECT_ASSERT_FAILURE (GetVariableMtrrCount (), NULL);
@@ -469,12 +496,12 @@ UnitTestGetFirmwareVariableMtrrCount ( IN UNIT_TEST_CONTEXT Context
)
{
- UINT32 Result;
- UINT32 ReservedMtrrs;
- MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
- MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext;
+ UINT32 Result;
+ UINT32 ReservedMtrrs;
+ MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
+ MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext;
- LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context;
+ LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
@@ -516,7 +543,7 @@ UnitTestGetFirmwareVariableMtrrCount ( //
// Negative test case when Fixed MTRRs are not supported
//
- SystemParameter.MtrrSupported = TRUE;
+ SystemParameter.MtrrSupported = TRUE;
SystemParameter.FixedMtrrSupported = FALSE;
InitializeMtrrRegs (&SystemParameter);
PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, 2);
@@ -527,7 +554,7 @@ UnitTestGetFirmwareVariableMtrrCount ( // Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR
//
SystemParameter.FixedMtrrSupported = TRUE;
- SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1;
+ SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1;
InitializeMtrrRegs (&SystemParameter);
UT_EXPECT_ASSERT_FAILURE (GetFirmwareVariableMtrrCount (), NULL);
@@ -569,17 +596,17 @@ UnitTestMtrrGetFixedMtrr ( IN UNIT_TEST_CONTEXT Context
)
{
- MTRR_FIXED_SETTINGS *Result;
- MTRR_FIXED_SETTINGS ExpectedFixedSettings;
- MTRR_FIXED_SETTINGS FixedSettings;
- UINTN Index;
- UINTN MsrIndex;
- UINTN ByteIndex;
- UINT64 MsrValue;
- MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
- MTRR_LIB_TEST_CONTEXT *LocalContext;
-
- LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;
+ MTRR_FIXED_SETTINGS *Result;
+ MTRR_FIXED_SETTINGS ExpectedFixedSettings;
+ MTRR_FIXED_SETTINGS FixedSettings;
+ UINTN Index;
+ UINTN MsrIndex;
+ UINTN ByteIndex;
+ UINT64 MsrValue;
+ MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
+ MTRR_LIB_TEST_CONTEXT *LocalContext;
+
+ LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
InitializeMtrrRegs (&SystemParameter);
@@ -594,6 +621,7 @@ UnitTestMtrrGetFixedMtrr ( for (ByteIndex = 0; ByteIndex < sizeof (UINT64); ByteIndex++) {
MsrValue = MsrValue | LShiftU64 (GenerateRandomCacheType (), ByteIndex * 8);
}
+
ExpectedFixedSettings.Mtrr[MsrIndex] = MsrValue;
AsmWriteMsr64 (mFixedMtrrsIndex[MsrIndex], MsrValue);
}
@@ -631,18 +659,18 @@ UnitTestMtrrGetFixedMtrr ( UNIT_TEST_STATUS
EFIAPI
UnitTestMtrrGetAllMtrrs (
- IN UNIT_TEST_CONTEXT Context
+ IN UNIT_TEST_CONTEXT Context
)
{
- MTRR_SETTINGS *Result;
- MTRR_SETTINGS Mtrrs;
- MTRR_SETTINGS ExpectedMtrrs;
- MTRR_VARIABLE_SETTING VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
- UINT32 Index;
- MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
- MTRR_LIB_TEST_CONTEXT *LocalContext;
+ MTRR_SETTINGS *Result;
+ MTRR_SETTINGS Mtrrs;
+ MTRR_SETTINGS ExpectedMtrrs;
+ MTRR_VARIABLE_SETTING VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
+ UINT32 Index;
+ MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
+ MTRR_LIB_TEST_CONTEXT *LocalContext;
- LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;
+ LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
InitializeMtrrRegs (&SystemParameter);
@@ -652,6 +680,7 @@ UnitTestMtrrGetAllMtrrs ( AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableMtrr[Index].Base);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableMtrr[Index].Mask);
}
+
Result = MtrrGetAllMtrrs (&Mtrrs);
UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs);
UT_ASSERT_MEM_EQUAL (Mtrrs.Variables.Mtrr, VariableMtrr, sizeof (MTRR_VARIABLE_SETTING) * SystemParameter.VariableMtrrCount);
@@ -671,7 +700,7 @@ UnitTestMtrrGetAllMtrrs ( //
// Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR
//
- SystemParameter.MtrrSupported = TRUE;
+ SystemParameter.MtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1;
InitializeMtrrRegs (&SystemParameter);
UT_EXPECT_ASSERT_FAILURE (MtrrGetAllMtrrs (&Mtrrs), NULL);
@@ -695,21 +724,21 @@ UnitTestMtrrSetAllMtrrs ( IN UNIT_TEST_CONTEXT Context
)
{
- MTRR_SETTINGS *Result;
- MTRR_SETTINGS Mtrrs;
- UINT32 Index;
- MSR_IA32_MTRR_DEF_TYPE_REGISTER Default;
- MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
- MTRR_LIB_TEST_CONTEXT *LocalContext;
+ MTRR_SETTINGS *Result;
+ MTRR_SETTINGS Mtrrs;
+ UINT32 Index;
+ MSR_IA32_MTRR_DEF_TYPE_REGISTER Default;
+ MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
+ MTRR_LIB_TEST_CONTEXT *LocalContext;
- LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;
+ LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
InitializeMtrrRegs (&SystemParameter);
- Default.Uint64 = 0;
- Default.Bits.E = 1;
- Default.Bits.FE = 1;
+ Default.Uint64 = 0;
+ Default.Bits.E = 1;
+ Default.Bits.FE = 1;
Default.Bits.Type = GenerateRandomCacheType ();
ZeroMem (&Mtrrs, sizeof (Mtrrs));
@@ -717,6 +746,7 @@ UnitTestMtrrSetAllMtrrs ( for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) {
GenerateRandomMtrrPair (SystemParameter.PhysicalAddressBits, GenerateRandomCacheType (), &Mtrrs.Variables.Mtrr[Index], NULL);
}
+
Result = MtrrSetAllMtrrs (&Mtrrs);
UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs);
@@ -745,18 +775,18 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr ( IN UNIT_TEST_CONTEXT Context
)
{
- MTRR_LIB_TEST_CONTEXT *LocalContext;
- MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
- UINT32 Result;
- MTRR_VARIABLE_SETTING VariableSetting[MTRR_NUMBER_OF_VARIABLE_MTRR];
- VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
- UINT64 ValidMtrrBitsMask;
- UINT64 ValidMtrrAddressMask;
- UINT32 Index;
- MSR_IA32_MTRR_PHYSBASE_REGISTER Base;
- MSR_IA32_MTRR_PHYSMASK_REGISTER Mask;
-
- LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;
+ MTRR_LIB_TEST_CONTEXT *LocalContext;
+ MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
+ UINT32 Result;
+ MTRR_VARIABLE_SETTING VariableSetting[MTRR_NUMBER_OF_VARIABLE_MTRR];
+ VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
+ UINT64 ValidMtrrBitsMask;
+ UINT64 ValidMtrrAddressMask;
+ UINT32 Index;
+ MSR_IA32_MTRR_PHYSBASE_REGISTER Base;
+ MSR_IA32_MTRR_PHYSMASK_REGISTER Mask;
+
+ LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
@@ -770,16 +800,17 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr ( AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSetting[Index].Base);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSetting[Index].Mask);
}
+
Result = MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr);
UT_ASSERT_EQUAL (Result, SystemParameter.VariableMtrrCount);
for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) {
Base.Uint64 = VariableMtrr[Index].BaseAddress;
- Base.Bits.Type = (UINT32) VariableMtrr[Index].Type;
+ Base.Bits.Type = (UINT32)VariableMtrr[Index].Type;
UT_ASSERT_EQUAL (Base.Uint64, VariableSetting[Index].Base);
- Mask.Uint64 = ~(VariableMtrr[Index].Length - 1) & ValidMtrrBitsMask;
- Mask.Bits.V = 1;
+ Mask.Uint64 = ~(VariableMtrr[Index].Length - 1) & ValidMtrrBitsMask;
+ Mask.Bits.V = 1;
UT_ASSERT_EQUAL (Mask.Uint64, VariableSetting[Index].Mask);
}
@@ -794,7 +825,7 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr ( //
// Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR
//
- SystemParameter.MtrrSupported = TRUE;
+ SystemParameter.MtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1;
InitializeMtrrRegs (&SystemParameter);
UT_EXPECT_ASSERT_FAILURE (MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr), NULL);
@@ -837,11 +868,11 @@ UnitTestMtrrGetDefaultMemoryType ( IN UNIT_TEST_CONTEXT Context
)
{
- MTRR_LIB_TEST_CONTEXT *LocalContext;
- UINTN Index;
- MTRR_MEMORY_CACHE_TYPE Result;
- MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
- MTRR_MEMORY_CACHE_TYPE CacheType[5];
+ MTRR_LIB_TEST_CONTEXT *LocalContext;
+ UINTN Index;
+ MTRR_MEMORY_CACHE_TYPE Result;
+ MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
+ MTRR_MEMORY_CACHE_TYPE CacheType[5];
CacheType[0] = CacheUncacheable;
CacheType[1] = CacheWriteCombining;
@@ -849,7 +880,7 @@ UnitTestMtrrGetDefaultMemoryType ( CacheType[3] = CacheWriteProtected;
CacheType[4] = CacheWriteBack;
- LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;
+ LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
//
@@ -871,15 +902,15 @@ UnitTestMtrrGetDefaultMemoryType ( Result = MtrrGetDefaultMemoryType ();
UT_ASSERT_EQUAL (Result, CacheUncacheable);
- SystemParameter.MtrrSupported = TRUE;
+ SystemParameter.MtrrSupported = TRUE;
SystemParameter.FixedMtrrSupported = FALSE;
InitializeMtrrRegs (&SystemParameter);
Result = MtrrGetDefaultMemoryType ();
UT_ASSERT_EQUAL (Result, CacheUncacheable);
- SystemParameter.MtrrSupported = TRUE;
+ SystemParameter.MtrrSupported = TRUE;
SystemParameter.FixedMtrrSupported = TRUE;
- SystemParameter.VariableMtrrCount = 0;
+ SystemParameter.VariableMtrrCount = 0;
InitializeMtrrRegs (&SystemParameter);
Result = MtrrGetDefaultMemoryType ();
UT_ASSERT_EQUAL (Result, CacheUncacheable);
@@ -903,37 +934,46 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( IN UNIT_TEST_CONTEXT Context
)
{
- CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
- RETURN_STATUS Status;
- UINT32 UcCount;
- UINT32 WtCount;
- UINT32 WbCount;
- UINT32 WpCount;
- UINT32 WcCount;
-
- UINTN MtrrIndex;
- UINTN Index;
- MTRR_SETTINGS LocalMtrrs;
-
- MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR];
- MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
- UINT32 ExpectedVariableMtrrUsage;
- UINTN ExpectedMemoryRangesCount;
-
- MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
- UINT32 ActualVariableMtrrUsage;
- UINTN ActualMemoryRangesCount;
-
- MTRR_SETTINGS *Mtrrs[2];
-
- SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context;
+ CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
+ RETURN_STATUS Status;
+ UINT32 UcCount;
+ UINT32 WtCount;
+ UINT32 WbCount;
+ UINT32 WpCount;
+ UINT32 WcCount;
+
+ UINTN MtrrIndex;
+ UINTN Index;
+ MTRR_SETTINGS LocalMtrrs;
+
+ MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR];
+ MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
+ UINT32 ExpectedVariableMtrrUsage;
+ UINTN ExpectedMemoryRangesCount;
+
+ MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
+ UINT32 ActualVariableMtrrUsage;
+ UINTN ActualMemoryRangesCount;
+
+ MTRR_SETTINGS *Mtrrs[2];
+
+ SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
GenerateRandomMemoryTypeCombination (
SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs),
- &UcCount, &WtCount, &WbCount, &WpCount, &WcCount
+ &UcCount,
+ &WtCount,
+ &WbCount,
+ &WpCount,
+ &WcCount
);
GenerateValidAndConfigurableMtrrPairs (
- SystemParameter->PhysicalAddressBits, RawMtrrRange,
- UcCount, WtCount, WbCount, WpCount, WcCount
+ SystemParameter->PhysicalAddressBits,
+ RawMtrrRange,
+ UcCount,
+ WtCount,
+ WbCount,
+ WpCount,
+ WcCount
);
ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount;
@@ -941,8 +981,10 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( GetEffectiveMemoryRanges (
SystemParameter->DefaultCacheType,
SystemParameter->PhysicalAddressBits,
- RawMtrrRange, ExpectedVariableMtrrUsage,
- ExpectedMemoryRanges, &ExpectedMemoryRangesCount
+ RawMtrrRange,
+ ExpectedVariableMtrrUsage,
+ ExpectedMemoryRanges,
+ &ExpectedMemoryRangesCount
);
UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount);
@@ -964,7 +1006,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( ExpectedMemoryRanges[Index].Type
);
UT_ASSERT_TRUE (Status == RETURN_SUCCESS || Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL);
- if (Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL) {
+ if ((Status == RETURN_OUT_OF_RESOURCES) || (Status == RETURN_BUFFER_TOO_SMALL)) {
return UNIT_TEST_SKIPPED;
}
}
@@ -973,10 +1015,16 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs));
MtrrGetAllMtrrs (&LocalMtrrs);
}
+
ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
CollectTestResult (
- SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount,
- &LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage
+ SystemParameter->DefaultCacheType,
+ SystemParameter->PhysicalAddressBits,
+ SystemParameter->VariableMtrrCount,
+ &LocalMtrrs,
+ ActualMemoryRanges,
+ &ActualMemoryRangesCount,
+ &ActualVariableMtrrUsage
);
UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount);
DumpMemoryRanges (ActualMemoryRanges, ActualMemoryRangesCount);
@@ -989,7 +1037,6 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings ( return UNIT_TEST_PASSED;
}
-
/**
Prep routine for UnitTestGetFirmwareVariableMtrrCount().
@@ -1003,7 +1050,7 @@ SavePcdValue ( {
MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext;
- LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context;
+ LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;
LocalContext->NumberOfReservedVariableMtrrs = PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);
return UNIT_TEST_PASSED;
}
@@ -1021,7 +1068,7 @@ RestorePcdValue ( {
MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext;
- LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context;
+ LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;
PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, LocalContext->NumberOfReservedVariableMtrrs);
}
@@ -1040,20 +1087,20 @@ STATIC EFI_STATUS
EFIAPI
UnitTestingEntry (
- UINTN Iteration
+ UINTN Iteration
)
{
- EFI_STATUS Status;
- UNIT_TEST_FRAMEWORK_HANDLE Framework;
- UNIT_TEST_SUITE_HANDLE MtrrApiTests;
- UINTN Index;
- UINTN SystemIndex;
- MTRR_LIB_TEST_CONTEXT Context;
- MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT GetFirmwareVariableMtrrCountContext;
+ EFI_STATUS Status;
+ UNIT_TEST_FRAMEWORK_HANDLE Framework;
+ UNIT_TEST_SUITE_HANDLE MtrrApiTests;
+ UINTN Index;
+ UINTN SystemIndex;
+ MTRR_LIB_TEST_CONTEXT Context;
+ MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT GetFirmwareVariableMtrrCountContext;
Context.SystemParameter = &mDefaultSystemParameter;
GetFirmwareVariableMtrrCountContext.SystemParameter = &mDefaultSystemParameter;
- Framework = NULL;
+ Framework = NULL;
//
// Setup the test framework for running the tests.
@@ -1077,24 +1124,26 @@ UnitTestingEntry ( Status = EFI_OUT_OF_RESOURCES;
goto EXIT;
}
- AddTestCase (MtrrApiTests, "Test IsMtrrSupported", "MtrrSupported", UnitTestIsMtrrSupported, NULL, NULL, &Context);
- AddTestCase (MtrrApiTests, "Test GetVariableMtrrCount", "GetVariableMtrrCount", UnitTestGetVariableMtrrCount, NULL, NULL, &Context);
- AddTestCase (MtrrApiTests, "Test GetFirmwareVariableMtrrCount", "GetFirmwareVariableMtrrCount", UnitTestGetFirmwareVariableMtrrCount, SavePcdValue, RestorePcdValue, &GetFirmwareVariableMtrrCountContext);
- AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttribute", "MtrrGetMemoryAttribute", UnitTestMtrrGetMemoryAttribute, NULL, NULL, &Context);
- AddTestCase (MtrrApiTests, "Test MtrrGetFixedMtrr", "MtrrGetFixedMtrr", UnitTestMtrrGetFixedMtrr, NULL, NULL, &Context);
- AddTestCase (MtrrApiTests, "Test MtrrGetAllMtrrs", "MtrrGetAllMtrrs", UnitTestMtrrGetAllMtrrs, NULL, NULL, &Context);
- AddTestCase (MtrrApiTests, "Test MtrrSetAllMtrrs", "MtrrSetAllMtrrs", UnitTestMtrrSetAllMtrrs, NULL, NULL, &Context);
+
+ AddTestCase (MtrrApiTests, "Test IsMtrrSupported", "MtrrSupported", UnitTestIsMtrrSupported, NULL, NULL, &Context);
+ AddTestCase (MtrrApiTests, "Test GetVariableMtrrCount", "GetVariableMtrrCount", UnitTestGetVariableMtrrCount, NULL, NULL, &Context);
+ AddTestCase (MtrrApiTests, "Test GetFirmwareVariableMtrrCount", "GetFirmwareVariableMtrrCount", UnitTestGetFirmwareVariableMtrrCount, SavePcdValue, RestorePcdValue, &GetFirmwareVariableMtrrCountContext);
+ AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttribute", "MtrrGetMemoryAttribute", UnitTestMtrrGetMemoryAttribute, NULL, NULL, &Context);
+ AddTestCase (MtrrApiTests, "Test MtrrGetFixedMtrr", "MtrrGetFixedMtrr", UnitTestMtrrGetFixedMtrr, NULL, NULL, &Context);
+ AddTestCase (MtrrApiTests, "Test MtrrGetAllMtrrs", "MtrrGetAllMtrrs", UnitTestMtrrGetAllMtrrs, NULL, NULL, &Context);
+ AddTestCase (MtrrApiTests, "Test MtrrSetAllMtrrs", "MtrrSetAllMtrrs", UnitTestMtrrSetAllMtrrs, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttributeInVariableMtrr", "MtrrGetMemoryAttributeInVariableMtrr", UnitTestMtrrGetMemoryAttributeInVariableMtrr, NULL, NULL, &Context);
- AddTestCase (MtrrApiTests, "Test MtrrDebugPrintAllMtrrs", "MtrrDebugPrintAllMtrrs", UnitTestMtrrDebugPrintAllMtrrs, NULL, NULL, &Context);
- AddTestCase (MtrrApiTests, "Test MtrrGetDefaultMemoryType", "MtrrGetDefaultMemoryType", UnitTestMtrrGetDefaultMemoryType, NULL, NULL, &Context);
+ AddTestCase (MtrrApiTests, "Test MtrrDebugPrintAllMtrrs", "MtrrDebugPrintAllMtrrs", UnitTestMtrrDebugPrintAllMtrrs, NULL, NULL, &Context);
+ AddTestCase (MtrrApiTests, "Test MtrrGetDefaultMemoryType", "MtrrGetDefaultMemoryType", UnitTestMtrrGetDefaultMemoryType, NULL, NULL, &Context);
for (SystemIndex = 0; SystemIndex < ARRAY_SIZE (mSystemParameters); SystemIndex++) {
for (Index = 0; Index < Iteration; Index++) {
- AddTestCase (MtrrApiTests, "Test InvalidMemoryLayouts", "InvalidMemoryLayouts", UnitTestInvalidMemoryLayouts, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);
- AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributeInMtrrSettings", "MtrrSetMemoryAttributeInMtrrSettings", UnitTestMtrrSetMemoryAttributeInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);
+ AddTestCase (MtrrApiTests, "Test InvalidMemoryLayouts", "InvalidMemoryLayouts", UnitTestInvalidMemoryLayouts, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);
+ AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributeInMtrrSettings", "MtrrSetMemoryAttributeInMtrrSettings", UnitTestMtrrSetMemoryAttributeInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);
AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributesInMtrrSettings", "MtrrSetMemoryAttributesInMtrrSettings", UnitTestMtrrSetMemoryAttributesInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);
}
}
+
//
// Execute the tests.
//
@@ -1118,14 +1167,14 @@ EXIT: **/
INT32
main (
- INT32 Argc,
- CHAR8 *Argv[]
+ INT32 Argc,
+ CHAR8 *Argv[]
)
{
- UINTN Count;
+ UINTN Count;
DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_APP_NAME, UNIT_TEST_APP_VERSION));
- srand ((unsigned int) time (NULL));
+ srand ((unsigned int)time (NULL));
//
// MtrrLibUnitTest generate-random-numbers <path to MtrrLib/UnitTest/RandomNumber.c> <random-number count>
diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h index 071c858a4c..57e656c555 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h @@ -29,21 +29,21 @@ #include <Register/Cpuid.h>
#include <Register/Msr.h>
-#define UNIT_TEST_APP_NAME "MtrrLib Unit Tests"
-#define UNIT_TEST_APP_VERSION "1.0"
+#define UNIT_TEST_APP_NAME "MtrrLib Unit Tests"
+#define UNIT_TEST_APP_VERSION "1.0"
-#define SCRATCH_BUFFER_SIZE SIZE_16KB
+#define SCRATCH_BUFFER_SIZE SIZE_16KB
typedef struct {
- UINT8 PhysicalAddressBits;
- BOOLEAN MtrrSupported;
- BOOLEAN FixedMtrrSupported;
- MTRR_MEMORY_CACHE_TYPE DefaultCacheType;
- UINT32 VariableMtrrCount;
+ UINT8 PhysicalAddressBits;
+ BOOLEAN MtrrSupported;
+ BOOLEAN FixedMtrrSupported;
+ MTRR_MEMORY_CACHE_TYPE DefaultCacheType;
+ UINT32 VariableMtrrCount;
} MTRR_LIB_SYSTEM_PARAMETER;
-extern UINT32 mFixedMtrrsIndex[];
-extern BOOLEAN mRandomInput;
+extern UINT32 mFixedMtrrsIndex[];
+extern BOOLEAN mRandomInput;
/**
Initialize the MTRR registers.
@@ -64,7 +64,7 @@ InitializeMtrrRegs ( UNIT_TEST_STATUS
EFIAPI
InitializeSystem (
- IN UNIT_TEST_CONTEXT Context
+ IN UNIT_TEST_CONTEXT Context
);
/**
@@ -88,13 +88,13 @@ GenerateRandomCacheType ( **/
VOID
GenerateValidAndConfigurableMtrrPairs (
- IN UINT32 PhysicalAddressBits,
- IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges,
- IN UINT32 UcCount,
- IN UINT32 WtCount,
- IN UINT32 WbCount,
- IN UINT32 WpCount,
- IN UINT32 WcCount
+ IN UINT32 PhysicalAddressBits,
+ IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges,
+ IN UINT32 UcCount,
+ IN UINT32 WtCount,
+ IN UINT32 WbCount,
+ IN UINT32 WpCount,
+ IN UINT32 WcCount
);
/**
@@ -109,12 +109,12 @@ GenerateValidAndConfigurableMtrrPairs ( **/
VOID
GetEffectiveMemoryRanges (
- IN MTRR_MEMORY_CACHE_TYPE DefaultType,
- IN UINT32 PhysicalAddressBits,
- IN MTRR_MEMORY_RANGE *RawMemoryRanges,
- IN UINT32 RawMemoryRangeCount,
- OUT MTRR_MEMORY_RANGE *MemoryRanges,
- OUT UINTN *MemoryRangeCount
+ IN MTRR_MEMORY_CACHE_TYPE DefaultType,
+ IN UINT32 PhysicalAddressBits,
+ IN MTRR_MEMORY_RANGE *RawMemoryRanges,
+ IN UINT32 RawMemoryRangeCount,
+ OUT MTRR_MEMORY_RANGE *MemoryRanges,
+ OUT UINTN *MemoryRangeCount
);
/**
@@ -127,10 +127,10 @@ GetEffectiveMemoryRanges ( **/
VOID
GenerateRandomMtrrPair (
- IN UINT32 PhysicalAddressBits,
- IN MTRR_MEMORY_CACHE_TYPE CacheType,
- OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL,
- OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL
+ IN UINT32 PhysicalAddressBits,
+ IN MTRR_MEMORY_CACHE_TYPE CacheType,
+ OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL,
+ OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL
);
/**
@@ -146,13 +146,13 @@ GenerateRandomMtrrPair ( **/
VOID
CollectTestResult (
- IN MTRR_MEMORY_CACHE_TYPE DefaultType,
- IN UINT32 PhysicalAddressBits,
- IN UINT32 VariableMtrrCount,
- IN MTRR_SETTINGS *Mtrrs,
- OUT MTRR_MEMORY_RANGE *Ranges,
- IN OUT UINTN *RangeCount,
- OUT UINT32 *MtrrCount
+ IN MTRR_MEMORY_CACHE_TYPE DefaultType,
+ IN UINT32 PhysicalAddressBits,
+ IN UINT32 VariableMtrrCount,
+ IN MTRR_SETTINGS *Mtrrs,
+ OUT MTRR_MEMORY_RANGE *Ranges,
+ IN OUT UINTN *RangeCount,
+ OUT UINT32 *MtrrCount
);
/**
@@ -189,7 +189,8 @@ Random32 ( **/
VOID
GenerateRandomNumbers (
- CHAR8 *FilePath,
- UINTN Count
+ CHAR8 *FilePath,
+ UINTN Count
);
+
#endif
diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c b/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c index 06104d8928..7190decc98 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c @@ -4,5006 +4,5006 @@ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-UINTN mNumberCount = 50000;
-UINTN mNumbers[] = {
- 7791, 9427, 6867, 23807, 10984, 16661, 1863, 16690, 14810, 14550,
- 11382, 15755, 19806, 32737, 209, 14661, 4112, 13680, 2425, 15502,
- 25268, 2882, 29953, 12346, 27936, 8942, 21365, 17849, 13910, 21879,
- 3995, 6982, 2032, 6432, 3448, 28770, 8385, 31106, 4630, 32385,
- 31417, 21979, 22661, 18947, 10249, 22953, 30752, 32613, 2952, 25464,
- 17, 12473, 28757, 19960, 27672, 1875, 17598, 20306, 22152, 15814,
- 31841, 25276, 2962, 30223, 23953, 28748, 25029, 16399, 15868, 9993,
- 31702, 25663, 29322, 15688, 22429, 18079, 30344, 2870, 20065, 30191,
- 3589, 13233, 27221, 15138, 26492, 20316, 13666, 15632, 180, 19954,
- 25895, 3179, 21221, 474, 2111, 11252, 2588, 2556, 6338, 26862,
- 19424, 3540, 6158, 6099, 20758, 32708, 6087, 2375, 22306, 22959,
- 21532, 19274, 11343, 1987, 17228, 2737, 23409, 30102, 15977, 10455,
+UINTN mNumberCount = 50000;
+UINTN mNumbers[] = {
+ 7791, 9427, 6867, 23807, 10984, 16661, 1863, 16690, 14810, 14550,
+ 11382, 15755, 19806, 32737, 209, 14661, 4112, 13680, 2425, 15502,
+ 25268, 2882, 29953, 12346, 27936, 8942, 21365, 17849, 13910, 21879,
+ 3995, 6982, 2032, 6432, 3448, 28770, 8385, 31106, 4630, 32385,
+ 31417, 21979, 22661, 18947, 10249, 22953, 30752, 32613, 2952, 25464,
+ 17, 12473, 28757, 19960, 27672, 1875, 17598, 20306, 22152, 15814,
+ 31841, 25276, 2962, 30223, 23953, 28748, 25029, 16399, 15868, 9993,
+ 31702, 25663, 29322, 15688, 22429, 18079, 30344, 2870, 20065, 30191,
+ 3589, 13233, 27221, 15138, 26492, 20316, 13666, 15632, 180, 19954,
+ 25895, 3179, 21221, 474, 2111, 11252, 2588, 2556, 6338, 26862,
+ 19424, 3540, 6158, 6099, 20758, 32708, 6087, 2375, 22306, 22959,
+ 21532, 19274, 11343, 1987, 17228, 2737, 23409, 30102, 15977, 10455,
15049, 29045, 10077, 22928, 25128, 23033, 12330, 23902, 19543, 18906,
- 10102, 11240, 10167, 13832, 28230, 8871, 6693, 12792, 31498, 3043,
- 31776, 20028, 3546, 4574, 20270, 17751, 31231, 29263, 29563, 27343,
- 10421, 1553, 24772, 4228, 14639, 28957, 26227, 22079, 25052, 3766,
- 14092, 6030, 30441, 28131, 17095, 27600, 14855, 29218, 9599, 27788,
+ 10102, 11240, 10167, 13832, 28230, 8871, 6693, 12792, 31498, 3043,
+ 31776, 20028, 3546, 4574, 20270, 17751, 31231, 29263, 29563, 27343,
+ 10421, 1553, 24772, 4228, 14639, 28957, 26227, 22079, 25052, 3766,
+ 14092, 6030, 30441, 28131, 17095, 27600, 14855, 29218, 9599, 27788,
22382, 27739, 11210, 13831, 13345, 16403, 13162, 22037, 29044, 26850,
- 27364, 7471, 18892, 29735, 13422, 1478, 10919, 17146, 12302, 9687,
- 12252, 10338, 12545, 24256, 25635, 14280, 8794, 16210, 27351, 22444,
- 7915, 19495, 30459, 27799, 16488, 8757, 13180, 12369, 27082, 10148,
- 181, 2387, 4338, 16093, 11064, 30335, 19343, 12260, 32716, 25359,
- 9025, 15335, 24754, 30412, 29951, 3863, 16429, 13952, 24502, 1206,
- 9281, 2221, 1586, 29041, 6074, 29311, 10306, 26609, 11376, 8448,
- 22295, 11181, 29386, 4747, 18670, 17922, 2689, 29827, 4079, 29061,
- 12454, 2372, 14420, 20376, 28391, 10842, 4557, 7227, 20494, 15090,
- 10275, 21541, 15818, 7821, 12060, 276, 27570, 2044, 26016, 8289,
- 29575, 13448, 13337, 22487, 1721, 26481, 2592, 27845, 22829, 14746,
- 16213, 12626, 10558, 4482, 31630, 23569, 2306, 22390, 27189, 32213,
- 19662, 14853, 15595, 2503, 17148, 5813, 16753, 9141, 6379, 23284,
- 3785, 10413, 4424, 29009, 3480, 9675, 28556, 3820, 24527, 12623,
- 15558, 29995, 27530, 23026, 18843, 31663, 3385, 8315, 4491, 30343,
+ 27364, 7471, 18892, 29735, 13422, 1478, 10919, 17146, 12302, 9687,
+ 12252, 10338, 12545, 24256, 25635, 14280, 8794, 16210, 27351, 22444,
+ 7915, 19495, 30459, 27799, 16488, 8757, 13180, 12369, 27082, 10148,
+ 181, 2387, 4338, 16093, 11064, 30335, 19343, 12260, 32716, 25359,
+ 9025, 15335, 24754, 30412, 29951, 3863, 16429, 13952, 24502, 1206,
+ 9281, 2221, 1586, 29041, 6074, 29311, 10306, 26609, 11376, 8448,
+ 22295, 11181, 29386, 4747, 18670, 17922, 2689, 29827, 4079, 29061,
+ 12454, 2372, 14420, 20376, 28391, 10842, 4557, 7227, 20494, 15090,
+ 10275, 21541, 15818, 7821, 12060, 276, 27570, 2044, 26016, 8289,
+ 29575, 13448, 13337, 22487, 1721, 26481, 2592, 27845, 22829, 14746,
+ 16213, 12626, 10558, 4482, 31630, 23569, 2306, 22390, 27189, 32213,
+ 19662, 14853, 15595, 2503, 17148, 5813, 16753, 9141, 6379, 23284,
+ 3785, 10413, 4424, 29009, 3480, 9675, 28556, 3820, 24527, 12623,
+ 15558, 29995, 27530, 23026, 18843, 31663, 3385, 8315, 4491, 30343,
13565, 12173, 25462, 19619, 29525, 17859, 29534, 21131, 14585, 1535,
- 14702, 15697, 19974, 8702, 16955, 16835, 17500, 4912, 21579, 13286,
- 26948, 21959, 3796, 15008, 31319, 23054, 26053, 27573, 8603, 8189,
- 7946, 25589, 31982, 12554, 13580, 12211, 13480, 27713, 17016, 6008,
- 25980, 22679, 23362, 9465, 24991, 29052, 30441, 29767, 3372, 8623,
- 20476, 9542, 22984, 24662, 23773, 352, 9602, 9294, 17861, 10618,
- 252, 8640, 31752, 24615, 8400, 1525, 22171, 17436, 32301, 9579,
- 22483, 3813, 27329, 20520, 111, 11222, 7132, 16462, 21465, 15171,
- 28882, 22256, 29097, 22004, 30881, 6948, 26731, 9427, 31443, 12121,
- 9634, 8424, 1958, 12523, 9997, 3975, 21355, 13813, 20776, 3784,
- 24876, 23911, 3830, 17976, 16529, 9560, 7934, 4046, 25348, 31645,
- 12691, 11553, 19476, 15514, 15449, 23767, 8471, 5208, 9989, 25697,
- 23572, 30168, 13668, 25062, 9696, 7335, 21151, 31356, 7046, 19635,
- 8637, 14494, 748, 17501, 30569, 11995, 12980, 5327, 8438, 13003,
- 12641, 21648, 7328, 17479, 20411, 24661, 10005, 29913, 17012, 7707,
- 16948, 25458, 32523, 30322, 6420, 8283, 24561, 30748, 25928, 3438,
- 21483, 22998, 14689, 3718, 7351, 20086, 21685, 7732, 24818, 24374,
- 25695, 6836, 5433, 16464, 21895, 24351, 143, 21451, 7396, 31969,
- 24574, 20116, 6014, 10606, 28033, 13264, 26809, 13361, 20002, 6769,
- 31119, 6341, 11104, 28935, 32029, 360, 31699, 13273, 7777, 19885,
+ 14702, 15697, 19974, 8702, 16955, 16835, 17500, 4912, 21579, 13286,
+ 26948, 21959, 3796, 15008, 31319, 23054, 26053, 27573, 8603, 8189,
+ 7946, 25589, 31982, 12554, 13580, 12211, 13480, 27713, 17016, 6008,
+ 25980, 22679, 23362, 9465, 24991, 29052, 30441, 29767, 3372, 8623,
+ 20476, 9542, 22984, 24662, 23773, 352, 9602, 9294, 17861, 10618,
+ 252, 8640, 31752, 24615, 8400, 1525, 22171, 17436, 32301, 9579,
+ 22483, 3813, 27329, 20520, 111, 11222, 7132, 16462, 21465, 15171,
+ 28882, 22256, 29097, 22004, 30881, 6948, 26731, 9427, 31443, 12121,
+ 9634, 8424, 1958, 12523, 9997, 3975, 21355, 13813, 20776, 3784,
+ 24876, 23911, 3830, 17976, 16529, 9560, 7934, 4046, 25348, 31645,
+ 12691, 11553, 19476, 15514, 15449, 23767, 8471, 5208, 9989, 25697,
+ 23572, 30168, 13668, 25062, 9696, 7335, 21151, 31356, 7046, 19635,
+ 8637, 14494, 748, 17501, 30569, 11995, 12980, 5327, 8438, 13003,
+ 12641, 21648, 7328, 17479, 20411, 24661, 10005, 29913, 17012, 7707,
+ 16948, 25458, 32523, 30322, 6420, 8283, 24561, 30748, 25928, 3438,
+ 21483, 22998, 14689, 3718, 7351, 20086, 21685, 7732, 24818, 24374,
+ 25695, 6836, 5433, 16464, 21895, 24351, 143, 21451, 7396, 31969,
+ 24574, 20116, 6014, 10606, 28033, 13264, 26809, 13361, 20002, 6769,
+ 31119, 6341, 11104, 28935, 32029, 360, 31699, 13273, 7777, 19885,
16147, 18741, 15170, 29041, 12501, 30724, 20688, 16399, 14167, 11425,
- 31950, 30680, 4351, 32748, 14446, 8637, 1343, 13466, 12379, 6479,
- 7355, 7887, 24060, 20714, 9390, 10734, 17912, 9772, 393, 28848,
- 32757, 23212, 5342, 7027, 27558, 1257, 14973, 30933, 14084, 3457,
- 8413, 1154, 6619, 3236, 189, 20554, 27273, 7111, 30730, 887,
- 28674, 28573, 3076, 25693, 5400, 20035, 5789, 8242, 24826, 13755,
- 8993, 17696, 22778, 18075, 32284, 8857, 12179, 18182, 31865, 1003,
- 25770, 20956, 15847, 30996, 15124, 1582, 28289, 8663, 10073, 19189,
- 19373, 12047, 7095, 31491, 28740, 3652, 21866, 3385, 11252, 29564,
- 3883, 3323, 27107, 13651, 15607, 30433, 27285, 12110, 13585, 19887,
- 21776, 7789, 27210, 31624, 25406, 11263, 7040, 21342, 11666, 6842,
- 7269, 18093, 23022, 18955, 7041, 9065, 12741, 939, 2427, 28213,
- 25469, 18291, 1428, 11477, 29463, 2417, 29556, 13542, 7697, 5691,
- 7721, 21196, 13963, 4483, 3181, 23789, 14762, 17132, 27175, 1821,
- 9530, 9500, 11061, 2648, 20631, 27411, 19305, 29879, 19661, 28603,
- 20433, 13725, 4094, 17344, 27964, 14897, 28676, 19873, 30713, 11794,
- 12376, 12296, 226, 13382, 10034, 27223, 17306, 11379, 15858, 26499,
+ 31950, 30680, 4351, 32748, 14446, 8637, 1343, 13466, 12379, 6479,
+ 7355, 7887, 24060, 20714, 9390, 10734, 17912, 9772, 393, 28848,
+ 32757, 23212, 5342, 7027, 27558, 1257, 14973, 30933, 14084, 3457,
+ 8413, 1154, 6619, 3236, 189, 20554, 27273, 7111, 30730, 887,
+ 28674, 28573, 3076, 25693, 5400, 20035, 5789, 8242, 24826, 13755,
+ 8993, 17696, 22778, 18075, 32284, 8857, 12179, 18182, 31865, 1003,
+ 25770, 20956, 15847, 30996, 15124, 1582, 28289, 8663, 10073, 19189,
+ 19373, 12047, 7095, 31491, 28740, 3652, 21866, 3385, 11252, 29564,
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+ 290, 31453, 31912, 28805, 5800, 5823, 6117, 17762, 19089, 28860,
+ 260, 7175, 10975, 21602, 13478, 8351, 3291, 29793, 17170, 26983,
+ 6305, 22519, 22487, 28607, 11742, 15531, 25779, 8065, 1497, 16446,
+ 29620, 28817, 14000, 26335, 25757, 16053, 31716, 20894, 6539, 21415,
+ 26648, 14627, 22232, 22377, 25622, 160, 23104, 6873, 7955, 29956,
};
diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c index d8511fefe8..748c403281 100644 --- a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c +++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c @@ -8,9 +8,9 @@ #include "MtrrLibUnitTest.h"
-MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] = {
+MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] = {
CacheUncacheable, CacheWriteCombining, CacheWriteThrough, CacheWriteProtected, CacheWriteBack
- };
+};
UINT64 mFixedMtrrsValue[MTRR_NUMBER_OF_FIXED_MTRR];
MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_NUMBER_OF_VARIABLE_MTRR];
@@ -20,10 +20,10 @@ MSR_IA32_MTRRCAP_REGISTER mMtrrCapMsr; CPUID_VERSION_INFO_EDX mCpuidVersionInfoEdx;
CPUID_VIR_PHY_ADDRESS_SIZE_EAX mCpuidVirPhyAddressSizeEax;
-BOOLEAN mRandomInput;
-UINTN mNumberIndex = 0;
-extern UINTN mNumbers[];
-extern UINTN mNumberCount;
+BOOLEAN mRandomInput;
+UINTN mNumberIndex = 0;
+extern UINTN mNumbers[];
+extern UINTN mNumberCount;
/**
Return a random number between 0 and RAND_MAX.
@@ -65,8 +65,8 @@ CHAR8 mContentTemplate[] = { **/
VOID
GenerateRandomNumbers (
- CHAR8 *FilePath,
- UINTN Count
+ CHAR8 *FilePath,
+ UINTN Count
)
{
FILE *File;
@@ -78,8 +78,10 @@ GenerateRandomNumbers ( if (Index % 10 == 0) {
fprintf (File, "\n ");
}
+
fprintf (File, " %d,", rand ());
}
+
fprintf (File, "\n};\n");
fclose (File);
}
@@ -112,38 +114,41 @@ GenerateRandomNumbers ( UINT32
EFIAPI
UnitTestMtrrLibAsmCpuid (
- IN UINT32 Index,
- OUT UINT32 *Eax OPTIONAL,
- OUT UINT32 *Ebx OPTIONAL,
- OUT UINT32 *Ecx OPTIONAL,
- OUT UINT32 *Edx OPTIONAL
+ IN UINT32 Index,
+ OUT UINT32 *Eax OPTIONAL,
+ OUT UINT32 *Ebx OPTIONAL,
+ OUT UINT32 *Ecx OPTIONAL,
+ OUT UINT32 *Edx OPTIONAL
)
{
switch (Index) {
- case CPUID_VERSION_INFO:
- if (Edx != NULL) {
- *Edx = mCpuidVersionInfoEdx.Uint32;
- }
- return Index;
- break;
- case CPUID_EXTENDED_FUNCTION:
- if (Eax != NULL) {
- *Eax = CPUID_VIR_PHY_ADDRESS_SIZE;
- }
- return Index;
- break;
- case CPUID_VIR_PHY_ADDRESS_SIZE:
- if (Eax != NULL) {
- *Eax = mCpuidVirPhyAddressSizeEax.Uint32;
- }
- return Index;
- break;
+ case CPUID_VERSION_INFO:
+ if (Edx != NULL) {
+ *Edx = mCpuidVersionInfoEdx.Uint32;
+ }
+
+ return Index;
+ break;
+ case CPUID_EXTENDED_FUNCTION:
+ if (Eax != NULL) {
+ *Eax = CPUID_VIR_PHY_ADDRESS_SIZE;
+ }
+
+ return Index;
+ break;
+ case CPUID_VIR_PHY_ADDRESS_SIZE:
+ if (Eax != NULL) {
+ *Eax = mCpuidVirPhyAddressSizeEax.Uint32;
+ }
+
+ return Index;
+ break;
}
//
// Should never fall through to here
//
- ASSERT(FALSE);
+ ASSERT (FALSE);
return Index;
}
@@ -163,11 +168,11 @@ UnitTestMtrrLibAsmCpuid ( **/
UINT64
EFIAPI
-UnitTestMtrrLibAsmReadMsr64(
+UnitTestMtrrLibAsmReadMsr64 (
IN UINT32 MsrIndex
)
{
- UINT32 Index;
+ UINT32 Index;
for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) {
if (MsrIndex == mFixedMtrrsIndex[Index]) {
@@ -176,7 +181,8 @@ UnitTestMtrrLibAsmReadMsr64( }
if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&
- (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) {
+ (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))
+ {
if (MsrIndex % 2 == 0) {
Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;
return mVariableMtrrsPhysBase[Index].Uint64;
@@ -197,7 +203,7 @@ UnitTestMtrrLibAsmReadMsr64( //
// Should never fall through to here
//
- ASSERT(FALSE);
+ ASSERT (FALSE);
return 0;
}
@@ -220,12 +226,12 @@ UnitTestMtrrLibAsmReadMsr64( **/
UINT64
EFIAPI
-UnitTestMtrrLibAsmWriteMsr64(
- IN UINT32 MsrIndex,
- IN UINT64 Value
+UnitTestMtrrLibAsmWriteMsr64 (
+ IN UINT32 MsrIndex,
+ IN UINT64 Value
)
{
- UINT32 Index;
+ UINT32 Index;
for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) {
if (MsrIndex == mFixedMtrrsIndex[Index]) {
@@ -235,13 +241,14 @@ UnitTestMtrrLibAsmWriteMsr64( }
if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&
- (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) {
+ (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))
+ {
if (MsrIndex % 2 == 0) {
- Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;
+ Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;
mVariableMtrrsPhysBase[Index].Uint64 = Value;
return Value;
} else {
- Index = (MsrIndex - MSR_IA32_MTRR_PHYSMASK0) >> 1;
+ Index = (MsrIndex - MSR_IA32_MTRR_PHYSMASK0) >> 1;
mVariableMtrrsPhysMask[Index].Uint64 = Value;
return Value;
}
@@ -260,7 +267,7 @@ UnitTestMtrrLibAsmWriteMsr64( //
// Should never fall through to here
//
- ASSERT(FALSE);
+ ASSERT (FALSE);
return 0;
}
@@ -275,7 +282,7 @@ InitializeMtrrRegs ( IN MTRR_LIB_SYSTEM_PARAMETER *SystemParameter
)
{
- UINT32 Index;
+ UINT32 Index;
SetMem (mFixedMtrrsValue, sizeof (mFixedMtrrsValue), SystemParameter->DefaultCacheType);
@@ -325,10 +332,10 @@ InitializeMtrrRegs ( UNIT_TEST_STATUS
EFIAPI
InitializeSystem (
- IN UNIT_TEST_CONTEXT Context
+ IN UNIT_TEST_CONTEXT Context
)
{
- return InitializeMtrrRegs ((MTRR_LIB_SYSTEM_PARAMETER *) Context);
+ return InitializeMtrrRegs ((MTRR_LIB_SYSTEM_PARAMETER *)Context);
}
/**
@@ -344,34 +351,34 @@ InitializeSystem ( **/
VOID
CollectTestResult (
- IN MTRR_MEMORY_CACHE_TYPE DefaultType,
- IN UINT32 PhysicalAddressBits,
- IN UINT32 VariableMtrrCount,
- IN MTRR_SETTINGS *Mtrrs,
- OUT MTRR_MEMORY_RANGE *Ranges,
- IN OUT UINTN *RangeCount,
- OUT UINT32 *MtrrCount
+ IN MTRR_MEMORY_CACHE_TYPE DefaultType,
+ IN UINT32 PhysicalAddressBits,
+ IN UINT32 VariableMtrrCount,
+ IN MTRR_SETTINGS *Mtrrs,
+ OUT MTRR_MEMORY_RANGE *Ranges,
+ IN OUT UINTN *RangeCount,
+ OUT UINT32 *MtrrCount
)
{
- UINTN Index;
- UINT64 MtrrValidBitsMask;
- UINT64 MtrrValidAddressMask;
- MTRR_MEMORY_RANGE RawMemoryRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];
+ UINTN Index;
+ UINT64 MtrrValidBitsMask;
+ UINT64 MtrrValidAddressMask;
+ MTRR_MEMORY_RANGE RawMemoryRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];
ASSERT (Mtrrs != NULL);
ASSERT (VariableMtrrCount <= ARRAY_SIZE (Mtrrs->Variables.Mtrr));
- MtrrValidBitsMask = (1ull << PhysicalAddressBits) - 1;
+ MtrrValidBitsMask = (1ull << PhysicalAddressBits) - 1;
MtrrValidAddressMask = MtrrValidBitsMask & ~0xFFFull;
*MtrrCount = 0;
for (Index = 0; Index < VariableMtrrCount; Index++) {
- if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 1) {
+ if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 1) {
RawMemoryRanges[*MtrrCount].BaseAddress = Mtrrs->Variables.Mtrr[Index].Base & MtrrValidAddressMask;
RawMemoryRanges[*MtrrCount].Type =
- ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &Mtrrs->Variables.Mtrr[Index].Base)->Bits.Type;
- RawMemoryRanges[*MtrrCount].Length =
- ((~(Mtrrs->Variables.Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;
+ ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Base)->Bits.Type;
+ RawMemoryRanges[*MtrrCount].Length =
+ ((~(Mtrrs->Variables.Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;
(*MtrrCount)++;
}
}
@@ -392,7 +399,7 @@ Random32 ( UINT32 Limit
)
{
- return (UINT32) (((double) Rand () / RAND_MAX) * (Limit - Start)) + Start;
+ return (UINT32)(((double)Rand () / RAND_MAX) * (Limit - Start)) + Start;
}
/**
@@ -408,7 +415,7 @@ Random64 ( UINT64 Limit
)
{
- return (UINT64) (((double) Rand () / RAND_MAX) * (Limit - Start)) + Start;
+ return (UINT64)(((double)Rand () / RAND_MAX) * (Limit - Start)) + Start;
}
/**
@@ -421,30 +428,30 @@ Random64 ( **/
VOID
GenerateRandomMtrrPair (
- IN UINT32 PhysicalAddressBits,
- IN MTRR_MEMORY_CACHE_TYPE CacheType,
- OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL,
- OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL
+ IN UINT32 PhysicalAddressBits,
+ IN MTRR_MEMORY_CACHE_TYPE CacheType,
+ OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL,
+ OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL
)
{
- MSR_IA32_MTRR_PHYSBASE_REGISTER PhysBase;
- MSR_IA32_MTRR_PHYSMASK_REGISTER PhysMask;
- UINT32 SizeShift;
- UINT32 BaseShift;
- UINT64 RandomBoundary;
- UINT64 MaxPhysicalAddress;
- UINT64 RangeSize;
- UINT64 RangeBase;
- UINT64 PhysBasePhyMaskValidBitsMask;
+ MSR_IA32_MTRR_PHYSBASE_REGISTER PhysBase;
+ MSR_IA32_MTRR_PHYSMASK_REGISTER PhysMask;
+ UINT32 SizeShift;
+ UINT32 BaseShift;
+ UINT64 RandomBoundary;
+ UINT64 MaxPhysicalAddress;
+ UINT64 RangeSize;
+ UINT64 RangeBase;
+ UINT64 PhysBasePhyMaskValidBitsMask;
MaxPhysicalAddress = 1ull << PhysicalAddressBits;
do {
SizeShift = Random32 (12, PhysicalAddressBits - 1);
RangeSize = 1ull << SizeShift;
- BaseShift = Random32 (SizeShift, PhysicalAddressBits - 1);
+ BaseShift = Random32 (SizeShift, PhysicalAddressBits - 1);
RandomBoundary = Random64 (0, 1ull << (PhysicalAddressBits - BaseShift));
- RangeBase = RandomBoundary << BaseShift;
+ RangeBase = RandomBoundary << BaseShift;
} while (RangeBase < SIZE_1MB || RangeBase > MaxPhysicalAddress - 1);
PhysBasePhyMaskValidBitsMask = (MaxPhysicalAddress - 1) & 0xfffffffffffff000ULL;
@@ -468,7 +475,6 @@ GenerateRandomMtrrPair ( }
}
-
/**
Check whether the Range overlaps with any one in Ranges.
@@ -480,9 +486,9 @@ GenerateRandomMtrrPair ( **/
BOOLEAN
RangesOverlap (
- IN MTRR_MEMORY_RANGE *Range,
- IN MTRR_MEMORY_RANGE *Ranges,
- IN UINTN Count
+ IN MTRR_MEMORY_RANGE *Range,
+ IN MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN Count
)
{
while (Count-- != 0) {
@@ -491,11 +497,13 @@ RangesOverlap ( // 1. range#2.base is in the middle of range#1
// 2. range#1.base is in the middle of range#2
//
- if ((Range->BaseAddress <= Ranges[Count].BaseAddress && Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length)
- || (Ranges[Count].BaseAddress <= Range->BaseAddress && Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length)) {
+ if ( ((Range->BaseAddress <= Ranges[Count].BaseAddress) && (Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length))
+ || ((Ranges[Count].BaseAddress <= Range->BaseAddress) && (Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length)))
+ {
return TRUE;
}
}
+
return FALSE;
}
@@ -512,16 +520,16 @@ RangesOverlap ( **/
VOID
GenerateValidAndConfigurableMtrrPairs (
- IN UINT32 PhysicalAddressBits,
- IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges,
- IN UINT32 UcCount,
- IN UINT32 WtCount,
- IN UINT32 WbCount,
- IN UINT32 WpCount,
- IN UINT32 WcCount
+ IN UINT32 PhysicalAddressBits,
+ IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges,
+ IN UINT32 UcCount,
+ IN UINT32 WtCount,
+ IN UINT32 WbCount,
+ IN UINT32 WpCount,
+ IN UINT32 WcCount
)
{
- UINT32 Index;
+ UINT32 Index;
//
// 1. Generate UC, WT, WB in order.
@@ -567,7 +575,7 @@ GenerateRandomCacheType ( VOID
)
{
- return mMemoryCacheTypes[Random32 (0, ARRAY_SIZE (mMemoryCacheTypes) - 1)];
+ return mMemoryCacheTypes[Random32 (0, ARRAY_SIZE (mMemoryCacheTypes) - 1)];
}
/**
@@ -586,19 +594,20 @@ GenerateRandomCacheType ( **/
INT32
CompareFuncUint64 (
- CONST VOID * Left,
- CONST VOID * Right
+ CONST VOID *Left,
+ CONST VOID *Right
)
{
- INT64 Delta;
- Delta = (*(UINT64*)Left - *(UINT64*)Right);
- if (Delta > 0) {
- return 1;
- } else if (Delta == 0) {
- return 0;
- } else {
- return -1;
- }
+ INT64 Delta;
+
+ Delta = (*(UINT64 *)Left - *(UINT64 *)Right);
+ if (Delta > 0) {
+ return 1;
+ } else if (Delta == 0) {
+ return 0;
+ } else {
+ return -1;
+ }
}
/**
@@ -611,13 +620,14 @@ CompareFuncUint64 ( **/
VOID
DetermineMemoryCacheType (
- IN MTRR_MEMORY_CACHE_TYPE DefaultType,
- IN OUT MTRR_MEMORY_RANGE *Range,
- IN MTRR_MEMORY_RANGE *Ranges,
- IN UINT32 RangeCount
+ IN MTRR_MEMORY_CACHE_TYPE DefaultType,
+ IN OUT MTRR_MEMORY_RANGE *Range,
+ IN MTRR_MEMORY_RANGE *Ranges,
+ IN UINT32 RangeCount
)
{
- UINT32 Index;
+ UINT32 Index;
+
Range->Type = CacheInvalid;
for (Index = 0; Index < RangeCount; Index++) {
if (RangesOverlap (Range, &Ranges[Index], 1)) {
@@ -643,16 +653,18 @@ DetermineMemoryCacheType ( **/
UINT32
GetNextDifferentElementInSortedArray (
- IN UINT32 Index,
- IN UINT64 *Array,
- IN UINT32 Count
+ IN UINT32 Index,
+ IN UINT64 *Array,
+ IN UINT32 Count
)
{
- UINT64 CurrentElement;
+ UINT64 CurrentElement;
+
CurrentElement = Array[Index];
while (CurrentElement == Array[Index] && Index < Count) {
Index++;
}
+
return Index;
}
@@ -664,12 +676,12 @@ GetNextDifferentElementInSortedArray ( **/
VOID
RemoveDuplicatesInSortedArray (
- IN OUT UINT64 *Array,
- IN OUT UINT32 *Count
+ IN OUT UINT64 *Array,
+ IN OUT UINT32 *Count
)
{
- UINT32 Index;
- UINT32 NewCount;
+ UINT32 Index;
+ UINT32 NewCount;
Index = 0;
NewCount = 0;
@@ -678,6 +690,7 @@ RemoveDuplicatesInSortedArray ( NewCount++;
Index = GetNextDifferentElementInSortedArray (Index, Array, *Count);
}
+
*Count = NewCount;
}
@@ -690,11 +703,11 @@ RemoveDuplicatesInSortedArray ( **/
BOOLEAN
AddressInRange (
- IN UINT64 Address,
- IN MTRR_MEMORY_RANGE Range
+ IN UINT64 Address,
+ IN MTRR_MEMORY_RANGE Range
)
{
- return (Address >= Range.BaseAddress) && (Address <= Range.BaseAddress + Range.Length - 1);
+ return (Address >= Range.BaseAddress) && (Address <= Range.BaseAddress + Range.Length - 1);
}
/**
@@ -706,13 +719,14 @@ AddressInRange ( **/
UINT64
GetOverlapBitFlag (
- IN MTRR_MEMORY_RANGE *RawMemoryRanges,
- IN UINT32 RawMemoryRangeCount,
- IN UINT64 Address
+ IN MTRR_MEMORY_RANGE *RawMemoryRanges,
+ IN UINT32 RawMemoryRangeCount,
+ IN UINT64 Address
)
{
- UINT64 OverlapBitFlag;
- UINT32 Index;
+ UINT64 OverlapBitFlag;
+ UINT32 Index;
+
OverlapBitFlag = 0;
for (Index = 0; Index < RawMemoryRangeCount; Index++) {
if (AddressInRange (Address, RawMemoryRanges[Index])) {
@@ -736,14 +750,23 @@ GetOverlapBitFlag ( **/
UINT32
CheckOverlapBitFlagsRelation (
- IN UINT64 Flag1,
- IN UINT64 Flag2
+ IN UINT64 Flag1,
+ IN UINT64 Flag2
)
{
- if (Flag1 == Flag2) return 0;
- if ((Flag1 | Flag2) == Flag2) return 1;
- if ((Flag1 | Flag2) == Flag1) return 2;
- return 3;
+ if (Flag1 == Flag2) {
+ return 0;
+ }
+
+ if ((Flag1 | Flag2) == Flag2) {
+ return 1;
+ }
+
+ if ((Flag1 | Flag2) == Flag1) {
+ return 2;
+ }
+
+ return 3;
}
/**
@@ -758,20 +781,21 @@ CheckOverlapBitFlagsRelation ( **/
BOOLEAN
IsEndpointInRanges (
- IN UINT64 Endpoint,
- IN MTRR_MEMORY_RANGE *Ranges,
- IN UINTN RangeCount
+ IN UINT64 Endpoint,
+ IN MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCount
)
{
- UINT32 Index;
- for (Index = 0; Index < RangeCount; Index++) {
- if (AddressInRange (Endpoint, Ranges[Index])) {
- return TRUE;
- }
+ UINT32 Index;
+
+ for (Index = 0; Index < RangeCount; Index++) {
+ if (AddressInRange (Endpoint, Ranges[Index])) {
+ return TRUE;
}
- return FALSE;
-}
+ }
+ return FALSE;
+}
/**
Compact adjacent ranges of the same type.
@@ -783,26 +807,26 @@ IsEndpointInRanges ( **/
VOID
CompactAndExtendEffectiveMtrrMemoryRanges (
- IN MTRR_MEMORY_CACHE_TYPE DefaultType,
- IN UINT32 PhysicalAddressBits,
- IN OUT MTRR_MEMORY_RANGE **EffectiveMtrrMemoryRanges,
- IN OUT UINTN *EffectiveMtrrMemoryRangesCount
+ IN MTRR_MEMORY_CACHE_TYPE DefaultType,
+ IN UINT32 PhysicalAddressBits,
+ IN OUT MTRR_MEMORY_RANGE **EffectiveMtrrMemoryRanges,
+ IN OUT UINTN *EffectiveMtrrMemoryRangesCount
)
{
- UINT64 MaxAddress;
- UINTN NewRangesCountAtMost;
- MTRR_MEMORY_RANGE *NewRanges;
- UINTN NewRangesCountActual;
- MTRR_MEMORY_RANGE *CurrentRangeInNewRanges;
- MTRR_MEMORY_CACHE_TYPE CurrentRangeTypeInOldRanges;
+ UINT64 MaxAddress;
+ UINTN NewRangesCountAtMost;
+ MTRR_MEMORY_RANGE *NewRanges;
+ UINTN NewRangesCountActual;
+ MTRR_MEMORY_RANGE *CurrentRangeInNewRanges;
+ MTRR_MEMORY_CACHE_TYPE CurrentRangeTypeInOldRanges;
- MTRR_MEMORY_RANGE *OldRanges;
- MTRR_MEMORY_RANGE OldLastRange;
- UINTN OldRangesIndex;
+ MTRR_MEMORY_RANGE *OldRanges;
+ MTRR_MEMORY_RANGE OldLastRange;
+ UINTN OldRangesIndex;
NewRangesCountActual = 0;
NewRangesCountAtMost = *EffectiveMtrrMemoryRangesCount + 2; // At most with 2 more range entries.
- NewRanges = (MTRR_MEMORY_RANGE *) calloc (NewRangesCountAtMost, sizeof (MTRR_MEMORY_RANGE));
+ NewRanges = (MTRR_MEMORY_RANGE *)calloc (NewRangesCountAtMost, sizeof (MTRR_MEMORY_RANGE));
OldRanges = *EffectiveMtrrMemoryRanges;
if (OldRanges[0].BaseAddress > 0) {
NewRanges[NewRangesCountActual].BaseAddress = 0;
@@ -814,44 +838,45 @@ CompactAndExtendEffectiveMtrrMemoryRanges ( OldRangesIndex = 0;
while (OldRangesIndex < *EffectiveMtrrMemoryRangesCount) {
CurrentRangeTypeInOldRanges = OldRanges[OldRangesIndex].Type;
- CurrentRangeInNewRanges = NULL;
- if (NewRangesCountActual > 0) // We need to check CurrentNewRange first before generate a new NewRange.
- {
+ CurrentRangeInNewRanges = NULL;
+ if (NewRangesCountActual > 0) {
+ // We need to check CurrentNewRange first before generate a new NewRange.
CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1];
}
- if (CurrentRangeInNewRanges != NULL && CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges) {
+
+ if ((CurrentRangeInNewRanges != NULL) && (CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges)) {
CurrentRangeInNewRanges->Length += OldRanges[OldRangesIndex].Length;
} else {
NewRanges[NewRangesCountActual].BaseAddress = OldRanges[OldRangesIndex].BaseAddress;
NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length;
NewRanges[NewRangesCountActual].Type = CurrentRangeTypeInOldRanges;
- while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges)
- {
+ while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges) {
OldRangesIndex++;
NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length;
}
+
NewRangesCountActual++;
}
OldRangesIndex++;
}
- MaxAddress = (1ull << PhysicalAddressBits) - 1;
- OldLastRange = OldRanges[(*EffectiveMtrrMemoryRangesCount) - 1];
+ MaxAddress = (1ull << PhysicalAddressBits) - 1;
+ OldLastRange = OldRanges[(*EffectiveMtrrMemoryRangesCount) - 1];
CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1];
if (OldLastRange.BaseAddress + OldLastRange.Length - 1 < MaxAddress) {
if (CurrentRangeInNewRanges->Type == DefaultType) {
CurrentRangeInNewRanges->Length = MaxAddress - CurrentRangeInNewRanges->BaseAddress + 1;
} else {
NewRanges[NewRangesCountActual].BaseAddress = OldLastRange.BaseAddress + OldLastRange.Length;
- NewRanges[NewRangesCountActual].Length = MaxAddress - NewRanges[NewRangesCountActual].BaseAddress + 1;
- NewRanges[NewRangesCountActual].Type = DefaultType;
+ NewRanges[NewRangesCountActual].Length = MaxAddress - NewRanges[NewRangesCountActual].BaseAddress + 1;
+ NewRanges[NewRangesCountActual].Type = DefaultType;
NewRangesCountActual++;
}
}
free (*EffectiveMtrrMemoryRanges);
- *EffectiveMtrrMemoryRanges = NewRanges;
+ *EffectiveMtrrMemoryRanges = NewRanges;
*EffectiveMtrrMemoryRangesCount = NewRangesCountActual;
}
@@ -865,20 +890,20 @@ CompactAndExtendEffectiveMtrrMemoryRanges ( **/
VOID
CollectEndpoints (
- IN OUT UINT64 *Endpoints,
- IN OUT UINT32 *EndPointCount,
- IN MTRR_MEMORY_RANGE *RawMemoryRanges,
- IN UINT32 RawMemoryRangeCount
+ IN OUT UINT64 *Endpoints,
+ IN OUT UINT32 *EndPointCount,
+ IN MTRR_MEMORY_RANGE *RawMemoryRanges,
+ IN UINT32 RawMemoryRangeCount
)
{
- UINT32 Index;
- UINT32 RawRangeIndex;
+ UINT32 Index;
+ UINT32 RawRangeIndex;
ASSERT ((RawMemoryRangeCount << 1) == *EndPointCount);
for (Index = 0; Index < *EndPointCount; Index += 2) {
- RawRangeIndex = Index >> 1;
- Endpoints[Index] = RawMemoryRanges[RawRangeIndex].BaseAddress;
+ RawRangeIndex = Index >> 1;
+ Endpoints[Index] = RawMemoryRanges[RawRangeIndex].BaseAddress;
Endpoints[Index + 1] = RawMemoryRanges[RawRangeIndex].BaseAddress + RawMemoryRanges[RawRangeIndex].Length - 1;
}
@@ -898,41 +923,41 @@ CollectEndpoints ( **/
VOID
GetEffectiveMemoryRanges (
- IN MTRR_MEMORY_CACHE_TYPE DefaultType,
- IN UINT32 PhysicalAddressBits,
- IN MTRR_MEMORY_RANGE *RawMemoryRanges,
- IN UINT32 RawMemoryRangeCount,
- OUT MTRR_MEMORY_RANGE *MemoryRanges,
- OUT UINTN *MemoryRangeCount
+ IN MTRR_MEMORY_CACHE_TYPE DefaultType,
+ IN UINT32 PhysicalAddressBits,
+ IN MTRR_MEMORY_RANGE *RawMemoryRanges,
+ IN UINT32 RawMemoryRangeCount,
+ OUT MTRR_MEMORY_RANGE *MemoryRanges,
+ OUT UINTN *MemoryRangeCount
)
{
- UINTN Index;
- UINT32 AllEndPointsCount;
- UINT64 *AllEndPointsInclusive;
- UINT32 AllRangePiecesCountMax;
- MTRR_MEMORY_RANGE *AllRangePieces;
- UINTN AllRangePiecesCountActual;
- UINT64 OverlapBitFlag1;
- UINT64 OverlapBitFlag2;
- INT32 OverlapFlagRelation;
+ UINTN Index;
+ UINT32 AllEndPointsCount;
+ UINT64 *AllEndPointsInclusive;
+ UINT32 AllRangePiecesCountMax;
+ MTRR_MEMORY_RANGE *AllRangePieces;
+ UINTN AllRangePiecesCountActual;
+ UINT64 OverlapBitFlag1;
+ UINT64 OverlapBitFlag2;
+ INT32 OverlapFlagRelation;
if (RawMemoryRangeCount == 0) {
MemoryRanges[0].BaseAddress = 0;
MemoryRanges[0].Length = (1ull << PhysicalAddressBits);
MemoryRanges[0].Type = DefaultType;
- *MemoryRangeCount = 1;
+ *MemoryRangeCount = 1;
return;
}
- AllEndPointsCount = RawMemoryRangeCount << 1;
- AllEndPointsInclusive = calloc (AllEndPointsCount, sizeof (UINT64));
- AllRangePiecesCountMax = RawMemoryRangeCount * 3 + 1;
- AllRangePieces = calloc (AllRangePiecesCountMax, sizeof (MTRR_MEMORY_RANGE));
+ AllEndPointsCount = RawMemoryRangeCount << 1;
+ AllEndPointsInclusive = calloc (AllEndPointsCount, sizeof (UINT64));
+ AllRangePiecesCountMax = RawMemoryRangeCount * 3 + 1;
+ AllRangePieces = calloc (AllRangePiecesCountMax, sizeof (MTRR_MEMORY_RANGE));
CollectEndpoints (AllEndPointsInclusive, &AllEndPointsCount, RawMemoryRanges, RawMemoryRangeCount);
for (Index = 0, AllRangePiecesCountActual = 0; Index < AllEndPointsCount - 1; Index++) {
- OverlapBitFlag1 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index]);
- OverlapBitFlag2 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index + 1]);
+ OverlapBitFlag1 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index]);
+ OverlapBitFlag2 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index + 1]);
OverlapFlagRelation = CheckOverlapBitFlagsRelation (OverlapBitFlag1, OverlapBitFlag2);
switch (OverlapFlagRelation) {
case 0: // [1, 2]
@@ -955,18 +980,23 @@ GetEffectiveMemoryRanges ( AllRangePieces[AllRangePiecesCountActual].Length = 1;
AllRangePiecesCountActual++;
}
+
break;
case 3: // (1, 2)
AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index] + 1;
AllRangePieces[AllRangePiecesCountActual].Length = (AllEndPointsInclusive[Index + 1] - 1) - (AllEndPointsInclusive[Index] + 1) + 1;
- if (AllRangePieces[AllRangePiecesCountActual].Length == 0) // Only in case 3 can exists Length=0, we should skip such "segment".
+ if (AllRangePieces[AllRangePiecesCountActual].Length == 0) {
+ // Only in case 3 can exists Length=0, we should skip such "segment".
break;
+ }
+
AllRangePiecesCountActual++;
if (!IsEndpointInRanges (AllEndPointsInclusive[Index], AllRangePieces, AllRangePiecesCountActual)) {
AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index];
AllRangePieces[AllRangePiecesCountActual].Length = 1;
AllRangePiecesCountActual++;
}
+
break;
default:
ASSERT (FALSE);
diff --git a/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c b/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c index cebaa81399..9f71c2611c 100644 --- a/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c +++ b/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c @@ -30,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent EFI_PEI_PPI_DESCRIPTOR *
EFIAPI
SecPlatformMain (
- IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
)
{
return NULL;
@@ -50,9 +50,9 @@ SecPlatformMain ( EFI_STATUS
EFIAPI
SecPlatformInformation (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN OUT UINT64 *StructureSize,
- OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
)
{
return EFI_SUCCESS;
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index 2f77ab3aeb..a8e4f920fc 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -8,7 +8,7 @@ #include "RegisterCpuFeatures.h"
-CHAR16 *mDependTypeStr[] = {L"None", L"Thread", L"Core", L"Package", L"Invalid" };
+CHAR16 *mDependTypeStr[] = { L"None", L"Thread", L"Core", L"Package", L"Invalid" };
/**
Worker function to save PcdCpuFeaturesCapability.
@@ -19,11 +19,11 @@ CHAR16 *mDependTypeStr[] = {L"None", L"Thread", L"Core", L"Package", L"Invalid **/
VOID
SetCapabilityPcd (
- IN UINT8 *SupportedFeatureMask,
- IN UINTN BitMaskSize
+ IN UINT8 *SupportedFeatureMask,
+ IN UINTN BitMaskSize
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = PcdSetPtrS (PcdCpuFeaturesCapability, &BitMaskSize, SupportedFeatureMask);
ASSERT_EFI_ERROR (Status);
@@ -37,11 +37,11 @@ SetCapabilityPcd ( **/
VOID
SetSettingPcd (
- IN UINT8 *SupportedFeatureMask,
- IN UINTN BitMaskSize
+ IN UINT8 *SupportedFeatureMask,
+ IN UINTN BitMaskSize
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = PcdSetPtrS (PcdCpuFeaturesSetting, &BitMaskSize, SupportedFeatureMask);
ASSERT_EFI_ERROR (Status);
@@ -54,14 +54,14 @@ SetSettingPcd ( **/
VOID
FillProcessorInfo (
- IN OUT REGISTER_CPU_FEATURE_INFORMATION *CpuInfo
+ IN OUT REGISTER_CPU_FEATURE_INFORMATION *CpuInfo
)
{
- CPUID_VERSION_INFO_EAX Eax;
- CPUID_VERSION_INFO_ECX Ecx;
- CPUID_VERSION_INFO_EDX Edx;
- UINT32 DisplayedFamily;
- UINT32 DisplayedModel;
+ CPUID_VERSION_INFO_EAX Eax;
+ CPUID_VERSION_INFO_ECX Ecx;
+ CPUID_VERSION_INFO_EDX Edx;
+ UINT32 DisplayedFamily;
+ UINT32 DisplayedModel;
AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, &Ecx.Uint32, &Edx.Uint32);
@@ -71,14 +71,14 @@ FillProcessorInfo ( }
DisplayedModel = Eax.Bits.Model;
- if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) {
+ if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {
DisplayedModel |= (Eax.Bits.ExtendedModelId << 4);
}
- CpuInfo->DisplayFamily = DisplayedFamily;
- CpuInfo->DisplayModel = DisplayedModel;
- CpuInfo->SteppingId = Eax.Bits.SteppingId;
- CpuInfo->ProcessorType = Eax.Bits.ProcessorType;
+ CpuInfo->DisplayFamily = DisplayedFamily;
+ CpuInfo->DisplayModel = DisplayedModel;
+ CpuInfo->SteppingId = Eax.Bits.SteppingId;
+ CpuInfo->ProcessorType = Eax.Bits.ProcessorType;
CpuInfo->CpuIdVersionInfoEcx.Uint32 = Ecx.Uint32;
CpuInfo->CpuIdVersionInfoEdx.Uint32 = Edx.Uint32;
}
@@ -92,29 +92,29 @@ CpuInitDataInitialize ( VOID
)
{
- EFI_STATUS Status;
- UINTN ProcessorNumber;
- EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer;
- CPU_FEATURES_ENTRY *CpuFeature;
- CPU_FEATURES_INIT_ORDER *InitOrder;
- CPU_FEATURES_DATA *CpuFeaturesData;
- LIST_ENTRY *Entry;
- UINT32 Core;
- UINT32 Package;
- UINT32 Thread;
- EFI_CPU_PHYSICAL_LOCATION *Location;
- UINT32 PackageIndex;
- UINT32 CoreIndex;
- UINTN Pages;
- UINT32 FirstPackage;
- UINT32 *FirstCore;
- UINT32 *FirstThread;
- ACPI_CPU_DATA *AcpiCpuData;
- CPU_STATUS_INFORMATION *CpuStatus;
- UINT32 *ThreadCountPerPackage;
- UINT8 *ThreadCountPerCore;
- UINTN NumberOfCpus;
- UINTN NumberOfEnabledProcessors;
+ EFI_STATUS Status;
+ UINTN ProcessorNumber;
+ EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer;
+ CPU_FEATURES_ENTRY *CpuFeature;
+ CPU_FEATURES_INIT_ORDER *InitOrder;
+ CPU_FEATURES_DATA *CpuFeaturesData;
+ LIST_ENTRY *Entry;
+ UINT32 Core;
+ UINT32 Package;
+ UINT32 Thread;
+ EFI_CPU_PHYSICAL_LOCATION *Location;
+ UINT32 PackageIndex;
+ UINT32 CoreIndex;
+ UINTN Pages;
+ UINT32 FirstPackage;
+ UINT32 *FirstCore;
+ UINT32 *FirstThread;
+ ACPI_CPU_DATA *AcpiCpuData;
+ CPU_STATUS_INFORMATION *CpuStatus;
+ UINT32 *ThreadCountPerPackage;
+ UINT8 *ThreadCountPerCore;
+ UINTN NumberOfCpus;
+ UINTN NumberOfEnabledProcessors;
Core = 0;
Package = 0;
@@ -143,23 +143,24 @@ CpuInitDataInitialize ( if (CpuFeature->GetConfigDataFunc != NULL) {
CpuFeature->ConfigData = CpuFeature->GetConfigDataFunc (NumberOfCpus);
}
+
Entry = Entry->ForwardLink;
}
- CpuFeaturesData->NumberOfCpus = (UINT32) NumberOfCpus;
+ CpuFeaturesData->NumberOfCpus = (UINT32)NumberOfCpus;
AcpiCpuData = GetAcpiCpuData ();
ASSERT (AcpiCpuData != NULL);
- CpuFeaturesData->AcpiCpuData= AcpiCpuData;
+ CpuFeaturesData->AcpiCpuData = AcpiCpuData;
CpuStatus = &AcpiCpuData->CpuFeatureInitData.CpuStatus;
- Location = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EFI_CPU_PHYSICAL_LOCATION) * NumberOfCpus));
+ Location = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EFI_CPU_PHYSICAL_LOCATION) * NumberOfCpus));
ASSERT (Location != NULL);
ZeroMem (Location, sizeof (EFI_CPU_PHYSICAL_LOCATION) * NumberOfCpus);
AcpiCpuData->CpuFeatureInitData.ApLocation = (EFI_PHYSICAL_ADDRESS)(UINTN)Location;
for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++) {
- InitOrder = &CpuFeaturesData->InitOrder[ProcessorNumber];
+ InitOrder = &CpuFeaturesData->InitOrder[ProcessorNumber];
InitOrder->FeaturesSupportedMask = AllocateZeroPool (CpuFeaturesData->BitMaskSize);
ASSERT (InitOrder->FeaturesSupportedMask != NULL);
InitializeListHead (&InitOrder->OrderList);
@@ -182,12 +183,14 @@ CpuInitDataInitialize ( if (Package < ProcessorInfoBuffer.Location.Package) {
Package = ProcessorInfoBuffer.Location.Package;
}
+
//
// Collect CPU max core count info.
//
if (Core < ProcessorInfoBuffer.Location.Core) {
Core = ProcessorInfoBuffer.Location.Core;
}
+
//
// Collect CPU max thread count info.
//
@@ -195,13 +198,17 @@ CpuInitDataInitialize ( Thread = ProcessorInfoBuffer.Location.Thread;
}
}
- CpuStatus->PackageCount = Package + 1;
- CpuStatus->MaxCoreCount = Core + 1;
- CpuStatus->MaxThreadCount = Thread + 1;
- DEBUG ((DEBUG_INFO, "Processor Info: Package: %d, MaxCore : %d, MaxThread: %d\n",
- CpuStatus->PackageCount,
- CpuStatus->MaxCoreCount,
- CpuStatus->MaxThreadCount));
+
+ CpuStatus->PackageCount = Package + 1;
+ CpuStatus->MaxCoreCount = Core + 1;
+ CpuStatus->MaxThreadCount = Thread + 1;
+ DEBUG ((
+ DEBUG_INFO,
+ "Processor Info: Package: %d, MaxCore : %d, MaxThread: %d\n",
+ CpuStatus->PackageCount,
+ CpuStatus->MaxCoreCount,
+ CpuStatus->MaxThreadCount
+ ));
//
// Collect valid core count in each package because not all cores are valid.
@@ -228,7 +235,10 @@ CpuInitDataInitialize ( for (CoreIndex = 0; CoreIndex < CpuStatus->MaxCoreCount; CoreIndex++) {
if (ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex] != 0) {
DEBUG ((
- DEBUG_INFO, " P%02d C%04d, Thread Count = %d\n", PackageIndex, CoreIndex,
+ DEBUG_INFO,
+ " P%02d C%04d, Thread Count = %d\n",
+ PackageIndex,
+ CoreIndex,
ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex]
));
}
@@ -248,13 +258,13 @@ CpuInitDataInitialize ( Pages = EFI_SIZE_TO_PAGES (CpuStatus->PackageCount * sizeof (UINT32) + CpuStatus->PackageCount * CpuStatus->MaxCoreCount * sizeof (UINT32));
FirstCore = AllocatePages (Pages);
ASSERT (FirstCore != NULL);
- FirstThread = FirstCore + CpuStatus->PackageCount;
+ FirstThread = FirstCore + CpuStatus->PackageCount;
//
// Set FirstPackage, FirstCore[], FirstThread[] to maximum package ID, core ID, thread ID.
//
FirstPackage = MAX_UINT32;
- SetMem32 (FirstCore, CpuStatus->PackageCount * sizeof (UINT32), MAX_UINT32);
+ SetMem32 (FirstCore, CpuStatus->PackageCount * sizeof (UINT32), MAX_UINT32);
SetMem32 (FirstThread, CpuStatus->PackageCount * CpuStatus->MaxCoreCount * sizeof (UINT32), MAX_UINT32);
for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++) {
@@ -263,7 +273,7 @@ CpuInitDataInitialize ( //
// Save the minimum package ID in the platform.
//
- FirstPackage = MIN (Location->Package, FirstPackage);
+ FirstPackage = MIN (Location->Package, FirstPackage);
//
// Save the minimum core ID per package.
@@ -274,9 +284,9 @@ CpuInitDataInitialize ( // Save the minimum thread ID per core.
//
FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core] = MIN (
- Location->Thread,
- FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core]
- );
+ Location->Thread,
+ FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core]
+ );
}
//
@@ -293,13 +303,14 @@ CpuInitDataInitialize ( // Set First.Die/Tile/Module for each thread assuming:
// single Die under each package, single Tile under each Die, single Module under each Tile
//
- CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Die = 1;
- CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Tile = 1;
+ CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Die = 1;
+ CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Tile = 1;
CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Module = 1;
if (Location->Core == FirstCore[Location->Package]) {
CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Core = 1;
}
+
if (Location->Thread == FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core]) {
CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Thread = 1;
}
@@ -318,14 +329,14 @@ CpuInitDataInitialize ( **/
VOID
SupportedMaskOr (
- IN UINT8 *SupportedFeatureMask,
- IN UINT8 *OrFeatureBitMask,
- IN UINT32 BitMaskSize
+ IN UINT8 *SupportedFeatureMask,
+ IN UINT8 *OrFeatureBitMask,
+ IN UINT32 BitMaskSize
)
{
- UINTN Index;
- UINT8 *Data1;
- UINT8 *Data2;
+ UINTN Index;
+ UINT8 *Data1;
+ UINT8 *Data2;
Data1 = SupportedFeatureMask;
Data2 = OrFeatureBitMask;
@@ -344,14 +355,14 @@ SupportedMaskOr ( **/
VOID
SupportedMaskAnd (
- IN UINT8 *SupportedFeatureMask,
- IN CONST UINT8 *AndFeatureBitMask,
- IN UINT32 BitMaskSize
+ IN UINT8 *SupportedFeatureMask,
+ IN CONST UINT8 *AndFeatureBitMask,
+ IN UINT32 BitMaskSize
)
{
- UINTN Index;
- UINT8 *Data1;
- CONST UINT8 *Data2;
+ UINTN Index;
+ UINT8 *Data1;
+ CONST UINT8 *Data2;
Data1 = SupportedFeatureMask;
Data2 = AndFeatureBitMask;
@@ -369,14 +380,14 @@ SupportedMaskAnd ( **/
VOID
SupportedMaskCleanBit (
- IN UINT8 *SupportedFeatureMask,
- IN UINT8 *AndFeatureBitMask,
- IN UINT32 BitMaskSize
+ IN UINT8 *SupportedFeatureMask,
+ IN UINT8 *AndFeatureBitMask,
+ IN UINT32 BitMaskSize
)
{
- UINTN Index;
- UINT8 *Data1;
- UINT8 *Data2;
+ UINTN Index;
+ UINT8 *Data1;
+ UINT8 *Data2;
Data1 = SupportedFeatureMask;
Data2 = AndFeatureBitMask;
@@ -400,14 +411,14 @@ SupportedMaskCleanBit ( **/
BOOLEAN
IsBitMaskMatch (
- IN UINT8 *SupportedFeatureMask,
- IN UINT8 *ComparedFeatureBitMask,
- IN UINT32 BitMaskSize
+ IN UINT8 *SupportedFeatureMask,
+ IN UINT8 *ComparedFeatureBitMask,
+ IN UINT32 BitMaskSize
)
{
- UINTN Index;
- UINT8 *Data1;
- UINT8 *Data2;
+ UINTN Index;
+ UINT8 *Data1;
+ UINT8 *Data2;
Data1 = SupportedFeatureMask;
Data2 = ComparedFeatureBitMask;
@@ -416,6 +427,7 @@ IsBitMaskMatch ( return TRUE;
}
}
+
return FALSE;
}
@@ -427,18 +439,18 @@ IsBitMaskMatch ( VOID
EFIAPI
CollectProcessorData (
- IN OUT VOID *Buffer
+ IN OUT VOID *Buffer
)
{
- UINTN ProcessorNumber;
- CPU_FEATURES_ENTRY *CpuFeature;
- REGISTER_CPU_FEATURE_INFORMATION *CpuInfo;
- LIST_ENTRY *Entry;
- CPU_FEATURES_DATA *CpuFeaturesData;
+ UINTN ProcessorNumber;
+ CPU_FEATURES_ENTRY *CpuFeature;
+ REGISTER_CPU_FEATURE_INFORMATION *CpuInfo;
+ LIST_ENTRY *Entry;
+ CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = (CPU_FEATURES_DATA *)Buffer;
ProcessorNumber = GetProcessorIndex (CpuFeaturesData);
- CpuInfo = &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo;
+ CpuInfo = &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo;
//
// collect processor information
//
@@ -462,6 +474,7 @@ CollectProcessorData ( CpuFeaturesData->BitMaskSize
);
}
+
Entry = Entry->ForwardLink;
}
}
@@ -475,15 +488,15 @@ CollectProcessorData ( **/
VOID
DumpRegisterTableOnProcessor (
- IN UINTN ProcessorNumber
+ IN UINTN ProcessorNumber
)
{
- CPU_FEATURES_DATA *CpuFeaturesData;
- UINTN FeatureIndex;
- CPU_REGISTER_TABLE *RegisterTable;
- CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
- CPU_REGISTER_TABLE_ENTRY *RegisterTableEntryHead;
- UINT32 DebugPrintErrorLevel;
+ CPU_FEATURES_DATA *CpuFeaturesData;
+ UINTN FeatureIndex;
+ CPU_REGISTER_TABLE *RegisterTable;
+ CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
+ CPU_REGISTER_TABLE_ENTRY *RegisterTableEntryHead;
+ UINT32 DebugPrintErrorLevel;
DebugPrintErrorLevel = (ProcessorNumber == 0) ? DEBUG_INFO : DEBUG_VERBOSE;
CpuFeaturesData = GetCpuFeaturesData ();
@@ -493,71 +506,71 @@ DumpRegisterTableOnProcessor ( RegisterTable = &CpuFeaturesData->RegisterTable[ProcessorNumber];
DEBUG ((DebugPrintErrorLevel, "RegisterTable->TableLength = %d\n", RegisterTable->TableLength));
- RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;
+ RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;
for (FeatureIndex = 0; FeatureIndex < RegisterTable->TableLength; FeatureIndex++) {
RegisterTableEntry = &RegisterTableEntryHead[FeatureIndex];
switch (RegisterTableEntry->RegisterType) {
- case Msr:
- DEBUG ((
- DebugPrintErrorLevel,
- "Processor: %04d: Index %04d, MSR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
- (UINT32) ProcessorNumber,
- (UINT32) FeatureIndex,
- RegisterTableEntry->Index,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitLength,
- RegisterTableEntry->Value
- ));
- break;
- case ControlRegister:
- DEBUG ((
- DebugPrintErrorLevel,
- "Processor: %04d: Index %04d, CR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
- (UINT32) ProcessorNumber,
- (UINT32) FeatureIndex,
- RegisterTableEntry->Index,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitLength,
- RegisterTableEntry->Value
- ));
- break;
- case MemoryMapped:
- DEBUG ((
- DebugPrintErrorLevel,
- "Processor: %04d: Index %04d, MMIO : %016lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
- (UINT32) ProcessorNumber,
- (UINT32) FeatureIndex,
- RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32),
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitLength,
- RegisterTableEntry->Value
- ));
- break;
- case CacheControl:
- DEBUG ((
- DebugPrintErrorLevel,
- "Processor: %04d: Index %04d, CACHE: %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
- (UINT32) ProcessorNumber,
- (UINT32) FeatureIndex,
- RegisterTableEntry->Index,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitLength,
- RegisterTableEntry->Value
- ));
- break;
- case Semaphore:
- DEBUG ((
- DebugPrintErrorLevel,
- "Processor: %04d: Index %04d, SEMAP: %s\r\n",
- (UINT32) ProcessorNumber,
- (UINT32) FeatureIndex,
- mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)]
- ));
- break;
+ case Msr:
+ DEBUG ((
+ DebugPrintErrorLevel,
+ "Processor: %04d: Index %04d, MSR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
+ (UINT32)ProcessorNumber,
+ (UINT32)FeatureIndex,
+ RegisterTableEntry->Index,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitLength,
+ RegisterTableEntry->Value
+ ));
+ break;
+ case ControlRegister:
+ DEBUG ((
+ DebugPrintErrorLevel,
+ "Processor: %04d: Index %04d, CR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
+ (UINT32)ProcessorNumber,
+ (UINT32)FeatureIndex,
+ RegisterTableEntry->Index,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitLength,
+ RegisterTableEntry->Value
+ ));
+ break;
+ case MemoryMapped:
+ DEBUG ((
+ DebugPrintErrorLevel,
+ "Processor: %04d: Index %04d, MMIO : %016lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
+ (UINT32)ProcessorNumber,
+ (UINT32)FeatureIndex,
+ RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32),
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitLength,
+ RegisterTableEntry->Value
+ ));
+ break;
+ case CacheControl:
+ DEBUG ((
+ DebugPrintErrorLevel,
+ "Processor: %04d: Index %04d, CACHE: %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
+ (UINT32)ProcessorNumber,
+ (UINT32)FeatureIndex,
+ RegisterTableEntry->Index,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitLength,
+ RegisterTableEntry->Value
+ ));
+ break;
+ case Semaphore:
+ DEBUG ((
+ DebugPrintErrorLevel,
+ "Processor: %04d: Index %04d, SEMAP: %s\r\n",
+ (UINT32)ProcessorNumber,
+ (UINT32)FeatureIndex,
+ mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)]
+ ));
+ break;
- default:
- break;
+ default:
+ break;
}
}
}
@@ -581,11 +594,11 @@ BiggestDep ( IN CPU_FEATURE_DEPENDENCE_TYPE NoneNeibAfterDep
)
{
- CPU_FEATURE_DEPENDENCE_TYPE Bigger;
+ CPU_FEATURE_DEPENDENCE_TYPE Bigger;
Bigger = MAX (BeforeDep, AfterDep);
Bigger = MAX (Bigger, NoneNeibBeforeDep);
- return MAX(Bigger, NoneNeibAfterDep);
+ return MAX (Bigger, NoneNeibAfterDep);
}
/**
@@ -596,26 +609,26 @@ BiggestDep ( **/
VOID
AnalysisProcessorFeatures (
- IN UINTN NumberOfCpus
+ IN UINTN NumberOfCpus
)
{
- EFI_STATUS Status;
- UINTN ProcessorNumber;
- CPU_FEATURES_ENTRY *CpuFeature;
- CPU_FEATURES_ENTRY *CpuFeatureInOrder;
- CPU_FEATURES_INIT_ORDER *CpuInitOrder;
- REGISTER_CPU_FEATURE_INFORMATION *CpuInfo;
- LIST_ENTRY *Entry;
- CPU_FEATURES_DATA *CpuFeaturesData;
- LIST_ENTRY *NextEntry;
- CPU_FEATURES_ENTRY *NextCpuFeatureInOrder;
- BOOLEAN Success;
- CPU_FEATURE_DEPENDENCE_TYPE BeforeDep;
- CPU_FEATURE_DEPENDENCE_TYPE AfterDep;
- CPU_FEATURE_DEPENDENCE_TYPE NoneNeibBeforeDep;
- CPU_FEATURE_DEPENDENCE_TYPE NoneNeibAfterDep;
-
- CpuFeaturesData = GetCpuFeaturesData ();
+ EFI_STATUS Status;
+ UINTN ProcessorNumber;
+ CPU_FEATURES_ENTRY *CpuFeature;
+ CPU_FEATURES_ENTRY *CpuFeatureInOrder;
+ CPU_FEATURES_INIT_ORDER *CpuInitOrder;
+ REGISTER_CPU_FEATURE_INFORMATION *CpuInfo;
+ LIST_ENTRY *Entry;
+ CPU_FEATURES_DATA *CpuFeaturesData;
+ LIST_ENTRY *NextEntry;
+ CPU_FEATURES_ENTRY *NextCpuFeatureInOrder;
+ BOOLEAN Success;
+ CPU_FEATURE_DEPENDENCE_TYPE BeforeDep;
+ CPU_FEATURE_DEPENDENCE_TYPE AfterDep;
+ CPU_FEATURE_DEPENDENCE_TYPE NoneNeibBeforeDep;
+ CPU_FEATURE_DEPENDENCE_TYPE NoneNeibAfterDep;
+
+ CpuFeaturesData = GetCpuFeaturesData ();
CpuFeaturesData->CapabilityPcd = AllocatePool (CpuFeaturesData->BitMaskSize);
ASSERT (CpuFeaturesData->CapabilityPcd != NULL);
SetMem (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize, 0xFF);
@@ -626,6 +639,7 @@ AnalysisProcessorFeatures ( //
SupportedMaskAnd (CpuFeaturesData->CapabilityPcd, CpuInitOrder->FeaturesSupportedMask, CpuFeaturesData->BitMaskSize);
}
+
//
// Calculate the last setting
//
@@ -637,28 +651,30 @@ AnalysisProcessorFeatures ( // Dump the last CPU feature list
//
DEBUG_CODE_BEGIN ();
- DEBUG ((DEBUG_INFO, "Last CPU features list...\n"));
- Entry = GetFirstNode (&CpuFeaturesData->FeatureList);
- while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) {
- CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (Entry);
- if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize)) {
- if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize)) {
- DEBUG ((DEBUG_INFO, "[Enable ] "));
- } else {
- DEBUG ((DEBUG_INFO, "[Disable ] "));
- }
+ DEBUG ((DEBUG_INFO, "Last CPU features list...\n"));
+ Entry = GetFirstNode (&CpuFeaturesData->FeatureList);
+ while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) {
+ CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (Entry);
+ if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize)) {
+ if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize)) {
+ DEBUG ((DEBUG_INFO, "[Enable ] "));
} else {
- DEBUG ((DEBUG_INFO, "[Unsupport] "));
+ DEBUG ((DEBUG_INFO, "[Disable ] "));
}
- DumpCpuFeature (CpuFeature, CpuFeaturesData->BitMaskSize);
- Entry = Entry->ForwardLink;
+ } else {
+ DEBUG ((DEBUG_INFO, "[Unsupport] "));
}
- DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n"));
- DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize);
- DEBUG ((DEBUG_INFO, "Origin PcdCpuFeaturesSetting:\n"));
- DumpCpuFeatureMask (PcdGetPtr (PcdCpuFeaturesSetting), CpuFeaturesData->BitMaskSize);
- DEBUG ((DEBUG_INFO, "Final PcdCpuFeaturesSetting:\n"));
- DumpCpuFeatureMask (CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize);
+
+ DumpCpuFeature (CpuFeature, CpuFeaturesData->BitMaskSize);
+ Entry = Entry->ForwardLink;
+ }
+
+ DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n"));
+ DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize);
+ DEBUG ((DEBUG_INFO, "Origin PcdCpuFeaturesSetting:\n"));
+ DumpCpuFeatureMask (PcdGetPtr (PcdCpuFeaturesSetting), CpuFeaturesData->BitMaskSize);
+ DEBUG ((DEBUG_INFO, "Final PcdCpuFeaturesSetting:\n"));
+ DumpCpuFeatureMask (CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize);
DEBUG_CODE_END ();
//
@@ -669,7 +685,7 @@ AnalysisProcessorFeatures ( for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++) {
CpuInitOrder = &CpuFeaturesData->InitOrder[ProcessorNumber];
- Entry = GetFirstNode (&CpuFeaturesData->FeatureList);
+ Entry = GetFirstNode (&CpuFeaturesData->FeatureList);
while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) {
//
// Insert each feature into processor's order list
@@ -680,13 +696,15 @@ AnalysisProcessorFeatures ( ASSERT (CpuFeatureInOrder != NULL);
InsertTailList (&CpuInitOrder->OrderList, &CpuFeatureInOrder->Link);
}
+
Entry = Entry->ForwardLink;
}
+
//
// Go through ordered feature list to initialize CPU features
//
CpuInfo = &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo;
- Entry = GetFirstNode (&CpuInitOrder->OrderList);
+ Entry = GetFirstNode (&CpuInitOrder->OrderList);
while (!IsNull (&CpuInitOrder->OrderList, Entry)) {
CpuFeatureInOrder = CPU_FEATURE_ENTRY_FROM_LINK (Entry);
@@ -736,23 +754,24 @@ AnalysisProcessorFeatures ( // Check whether next feature has After type dependence with not neighborhood CPU
// Features in former CPU features.
//
- NoneNeibAfterDep = DetectNoneNeighborhoodFeatureScope(NextCpuFeatureInOrder, FALSE, &CpuInitOrder->OrderList);
+ NoneNeibAfterDep = DetectNoneNeighborhoodFeatureScope (NextCpuFeatureInOrder, FALSE, &CpuInitOrder->OrderList);
} else {
BeforeDep = NoneDepType;
AfterDep = NoneDepType;
NoneNeibAfterDep = NoneDepType;
}
+
//
// Check whether current feature has Before type dependence with none neighborhood
// CPU features in after Cpu features.
//
- NoneNeibBeforeDep = DetectNoneNeighborhoodFeatureScope(CpuFeatureInOrder, TRUE, &CpuInitOrder->OrderList);
+ NoneNeibBeforeDep = DetectNoneNeighborhoodFeatureScope (CpuFeatureInOrder, TRUE, &CpuInitOrder->OrderList);
//
// Get the biggest dependence and add semaphore for it.
// PackageDepType > CoreDepType > ThreadDepType > NoneDepType.
//
- BeforeDep = BiggestDep(BeforeDep, AfterDep, NoneNeibBeforeDep, NoneNeibAfterDep);
+ BeforeDep = BiggestDep (BeforeDep, AfterDep, NoneNeibBeforeDep, NoneNeibAfterDep);
if (BeforeDep > ThreadDepType) {
CPU_REGISTER_TABLE_WRITE32 (ProcessorNumber, Semaphore, 0, BeforeDep);
}
@@ -783,7 +802,7 @@ AnalysisProcessorFeatures ( **/
VOID
LibReleaseSemaphore (
- IN OUT volatile UINT32 *Sem
+ IN OUT volatile UINT32 *Sem
)
{
InterlockedIncrement (Sem);
@@ -801,7 +820,7 @@ LibReleaseSemaphore ( **/
VOID
LibWaitForSemaphore (
- IN OUT volatile UINT32 *Sem
+ IN OUT volatile UINT32 *Sem
)
{
UINT32 Value;
@@ -827,42 +846,46 @@ LibWaitForSemaphore ( **/
UINTN
ReadWriteCr (
- IN UINT32 CrIndex,
- IN BOOLEAN Read,
- IN OUT UINTN *CrValue
+ IN UINT32 CrIndex,
+ IN BOOLEAN Read,
+ IN OUT UINTN *CrValue
)
{
switch (CrIndex) {
- case 0:
- if (Read) {
- *CrValue = AsmReadCr0 ();
- } else {
- AsmWriteCr0 (*CrValue);
- }
- break;
- case 2:
- if (Read) {
- *CrValue = AsmReadCr2 ();
- } else {
- AsmWriteCr2 (*CrValue);
- }
- break;
- case 3:
- if (Read) {
- *CrValue = AsmReadCr3 ();
- } else {
- AsmWriteCr3 (*CrValue);
- }
- break;
- case 4:
- if (Read) {
- *CrValue = AsmReadCr4 ();
- } else {
- AsmWriteCr4 (*CrValue);
- }
- break;
- default:
- return EFI_UNSUPPORTED;;
+ case 0:
+ if (Read) {
+ *CrValue = AsmReadCr0 ();
+ } else {
+ AsmWriteCr0 (*CrValue);
+ }
+
+ break;
+ case 2:
+ if (Read) {
+ *CrValue = AsmReadCr2 ();
+ } else {
+ AsmWriteCr2 (*CrValue);
+ }
+
+ break;
+ case 3:
+ if (Read) {
+ *CrValue = AsmReadCr3 ();
+ } else {
+ AsmWriteCr3 (*CrValue);
+ }
+
+ break;
+ case 4:
+ if (Read) {
+ *CrValue = AsmReadCr4 ();
+ } else {
+ AsmWriteCr4 (*CrValue);
+ }
+
+ break;
+ default:
+ return EFI_UNSUPPORTED;
}
return EFI_SUCCESS;
@@ -880,10 +903,10 @@ ReadWriteCr ( **/
VOID
ProgramProcessorRegister (
- IN CPU_REGISTER_TABLE *RegisterTable,
- IN EFI_CPU_PHYSICAL_LOCATION *ApLocation,
- IN CPU_STATUS_INFORMATION *CpuStatus,
- IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags
+ IN CPU_REGISTER_TABLE *RegisterTable,
+ IN EFI_CPU_PHYSICAL_LOCATION *ApLocation,
+ IN CPU_STATUS_INFORMATION *CpuStatus,
+ IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags
)
{
CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
@@ -903,54 +926,25 @@ ProgramProcessorRegister ( //
// Traverse Register Table of this logical processor
//
- RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;
+ RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;
for (Index = 0; Index < RegisterTable->TableLength; Index++) {
-
RegisterTableEntry = &RegisterTableEntryHead[Index];
//
// Check the type of specified register
//
switch (RegisterTableEntry->RegisterType) {
- //
- // The specified register is Control Register
- //
- case ControlRegister:
- Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);
- if (EFI_ERROR (Status)) {
- break;
- }
- if (RegisterTableEntry->TestThenWrite) {
- CurrentValue = BitFieldRead64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1
- );
- if (CurrentValue == RegisterTableEntry->Value) {
+ //
+ // The specified register is Control Register
+ //
+ case ControlRegister:
+ Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);
+ if (EFI_ERROR (Status)) {
break;
}
- }
- Value = (UINTN) BitFieldWrite64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- RegisterTableEntry->Value
- );
- ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);
- break;
- //
- // The specified register is Model Specific Register
- //
- case Msr:
- if (RegisterTableEntry->TestThenWrite) {
- Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index);
- if (RegisterTableEntry->ValidBitLength >= 64) {
- if (Value == RegisterTableEntry->Value) {
- break;
- }
- } else {
+ if (RegisterTableEntry->TestThenWrite) {
CurrentValue = BitFieldRead64 (
Value,
RegisterTableEntry->ValidBitStart,
@@ -960,153 +954,190 @@ ProgramProcessorRegister ( break;
}
}
- }
- if (RegisterTableEntry->ValidBitLength >= 64) {
- //
- // If length is not less than 64 bits, then directly write without reading
- //
- AsmWriteMsr64 (
- RegisterTableEntry->Index,
- RegisterTableEntry->Value
- );
- } else {
- //
- // Set the bit section according to bit start and length
- //
- AsmMsrBitFieldWrite64 (
- RegisterTableEntry->Index,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- RegisterTableEntry->Value
- );
- }
- break;
- //
- // MemoryMapped operations
- //
- case MemoryMapped:
- AcquireSpinLock (&CpuFlags->MemoryMappedLock);
- MmioBitFieldWrite32 (
- (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- (UINT32)RegisterTableEntry->Value
- );
- ReleaseSpinLock (&CpuFlags->MemoryMappedLock);
- break;
- //
- // Enable or disable cache
- //
- case CacheControl:
- //
- // If value of the entry is 0, then disable cache. Otherwise, enable cache.
- //
- if (RegisterTableEntry->Value == 0) {
- AsmDisableCache ();
- } else {
- AsmEnableCache ();
- }
- break;
+ Value = (UINTN)BitFieldWrite64 (
+ Value,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
+ RegisterTableEntry->Value
+ );
+ ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);
+ break;
- case Semaphore:
- // Semaphore works logic like below:
//
- // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);
- // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);
+ // The specified register is Model Specific Register
//
- // All threads (T0...Tn) waits in P() line and continues running
- // together.
+ case Msr:
+ if (RegisterTableEntry->TestThenWrite) {
+ Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index);
+ if (RegisterTableEntry->ValidBitLength >= 64) {
+ if (Value == RegisterTableEntry->Value) {
+ break;
+ }
+ } else {
+ CurrentValue = BitFieldRead64 (
+ Value,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1
+ );
+ if (CurrentValue == RegisterTableEntry->Value) {
+ break;
+ }
+ }
+ }
+
+ if (RegisterTableEntry->ValidBitLength >= 64) {
+ //
+ // If length is not less than 64 bits, then directly write without reading
+ //
+ AsmWriteMsr64 (
+ RegisterTableEntry->Index,
+ RegisterTableEntry->Value
+ );
+ } else {
+ //
+ // Set the bit section according to bit start and length
+ //
+ AsmMsrBitFieldWrite64 (
+ RegisterTableEntry->Index,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
+ RegisterTableEntry->Value
+ );
+ }
+
+ break;
//
+ // MemoryMapped operations
//
- // T0 T1 ... Tn
+ case MemoryMapped:
+ AcquireSpinLock (&CpuFlags->MemoryMappedLock);
+ MmioBitFieldWrite32 (
+ (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
+ (UINT32)RegisterTableEntry->Value
+ );
+ ReleaseSpinLock (&CpuFlags->MemoryMappedLock);
+ break;
//
- // V(0...n) V(0...n) ... V(0...n)
- // n * P(0) n * P(1) ... n * P(n)
+ // Enable or disable cache
//
- switch (RegisterTableEntry->Value) {
- case CoreDepType:
- SemaphorePtr = CpuFlags->CoreSemaphoreCount;
- ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore;
-
- CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core;
+ case CacheControl:
//
- // Get Offset info for the first thread in the core which current thread belongs to.
+ // If value of the entry is 0, then disable cache. Otherwise, enable cache.
//
- FirstThread = CurrentCore * CpuStatus->MaxThreadCount;
- CurrentThread = FirstThread + ApLocation->Thread;
-
- //
- // Different cores may have different valid threads in them. If driver maintail clearly
- // thread index in different cores, the logic will be much complicated.
- // Here driver just simply records the max thread number in all cores and use it as expect
- // thread number for all cores.
- // In below two steps logic, first current thread will Release semaphore for each thread
- // in current core. Maybe some threads are not valid in this core, but driver don't
- // care. Second, driver will let current thread wait semaphore for all valid threads in
- // current core. Because only the valid threads will do release semaphore for this
- // thread, driver here only need to wait the valid thread count.
- //
-
- //
- // First Notify ALL THREADs in current Core that this thread is ready.
- //
- for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) {
- LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
- }
- //
- // Second, check whether all VALID THREADs (not all threads) in current core are ready.
- //
- for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex ++) {
- LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);
+ if (RegisterTableEntry->Value == 0) {
+ AsmDisableCache ();
+ } else {
+ AsmEnableCache ();
}
+
break;
- case PackageDepType:
- SemaphorePtr = CpuFlags->PackageSemaphoreCount;
- ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage;
+ case Semaphore:
+ // Semaphore works logic like below:
//
- // Get Offset info for the first thread in the package which current thread belongs to.
+ // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);
+ // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);
//
- FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;
+ // All threads (T0...Tn) waits in P() line and continues running
+ // together.
//
- // Get the possible threads count for current package.
//
- CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;
-
+ // T0 T1 ... Tn
//
- // Different packages may have different valid threads in them. If driver maintail clearly
- // thread index in different packages, the logic will be much complicated.
- // Here driver just simply records the max thread number in all packages and use it as expect
- // thread number for all packages.
- // In below two steps logic, first current thread will Release semaphore for each thread
- // in current package. Maybe some threads are not valid in this package, but driver don't
- // care. Second, driver will let current thread wait semaphore for all valid threads in
- // current package. Because only the valid threads will do release semaphore for this
- // thread, driver here only need to wait the valid thread count.
+ // V(0...n) V(0...n) ... V(0...n)
+ // n * P(0) n * P(1) ... n * P(n)
//
+ switch (RegisterTableEntry->Value) {
+ case CoreDepType:
+ SemaphorePtr = CpuFlags->CoreSemaphoreCount;
+ ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore;
+
+ CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core;
+ //
+ // Get Offset info for the first thread in the core which current thread belongs to.
+ //
+ FirstThread = CurrentCore * CpuStatus->MaxThreadCount;
+ CurrentThread = FirstThread + ApLocation->Thread;
+
+ //
+ // Different cores may have different valid threads in them. If driver maintail clearly
+ // thread index in different cores, the logic will be much complicated.
+ // Here driver just simply records the max thread number in all cores and use it as expect
+ // thread number for all cores.
+ // In below two steps logic, first current thread will Release semaphore for each thread
+ // in current core. Maybe some threads are not valid in this core, but driver don't
+ // care. Second, driver will let current thread wait semaphore for all valid threads in
+ // current core. Because only the valid threads will do release semaphore for this
+ // thread, driver here only need to wait the valid thread count.
+ //
+
+ //
+ // First Notify ALL THREADs in current Core that this thread is ready.
+ //
+ for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex++) {
+ LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
+ }
+
+ //
+ // Second, check whether all VALID THREADs (not all threads) in current core are ready.
+ //
+ for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex++) {
+ LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);
+ }
- //
- // First Notify ALL THREADS in current package that this thread is ready.
- //
- for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex ++) {
- LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
- }
- //
- // Second, check whether VALID THREADS (not all threads) in current package are ready.
- //
- for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex ++) {
- LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);
+ break;
+
+ case PackageDepType:
+ SemaphorePtr = CpuFlags->PackageSemaphoreCount;
+ ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage;
+ //
+ // Get Offset info for the first thread in the package which current thread belongs to.
+ //
+ FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;
+ //
+ // Get the possible threads count for current package.
+ //
+ CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;
+
+ //
+ // Different packages may have different valid threads in them. If driver maintail clearly
+ // thread index in different packages, the logic will be much complicated.
+ // Here driver just simply records the max thread number in all packages and use it as expect
+ // thread number for all packages.
+ // In below two steps logic, first current thread will Release semaphore for each thread
+ // in current package. Maybe some threads are not valid in this package, but driver don't
+ // care. Second, driver will let current thread wait semaphore for all valid threads in
+ // current package. Because only the valid threads will do release semaphore for this
+ // thread, driver here only need to wait the valid thread count.
+ //
+
+ //
+ // First Notify ALL THREADS in current package that this thread is ready.
+ //
+ for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex++) {
+ LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
+ }
+
+ //
+ // Second, check whether VALID THREADS (not all threads) in current package are ready.
+ //
+ for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex++) {
+ LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);
+ }
+
+ break;
+
+ default:
+ break;
}
+
break;
default:
break;
- }
- break;
-
- default:
- break;
}
}
}
@@ -1120,32 +1151,33 @@ ProgramProcessorRegister ( VOID
EFIAPI
SetProcessorRegister (
- IN OUT VOID *Buffer
+ IN OUT VOID *Buffer
)
{
- CPU_FEATURES_DATA *CpuFeaturesData;
- CPU_REGISTER_TABLE *RegisterTable;
- CPU_REGISTER_TABLE *RegisterTables;
- UINT32 InitApicId;
- UINTN ProcIndex;
- UINTN Index;
- ACPI_CPU_DATA *AcpiCpuData;
+ CPU_FEATURES_DATA *CpuFeaturesData;
+ CPU_REGISTER_TABLE *RegisterTable;
+ CPU_REGISTER_TABLE *RegisterTables;
+ UINT32 InitApicId;
+ UINTN ProcIndex;
+ UINTN Index;
+ ACPI_CPU_DATA *AcpiCpuData;
- CpuFeaturesData = (CPU_FEATURES_DATA *) Buffer;
- AcpiCpuData = CpuFeaturesData->AcpiCpuData;
+ CpuFeaturesData = (CPU_FEATURES_DATA *)Buffer;
+ AcpiCpuData = CpuFeaturesData->AcpiCpuData;
RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.RegisterTable;
- InitApicId = GetInitialApicId ();
+ InitApicId = GetInitialApicId ();
RegisterTable = NULL;
- ProcIndex = (UINTN)-1;
+ ProcIndex = (UINTN)-1;
for (Index = 0; Index < AcpiCpuData->NumberOfCpus; Index++) {
if (RegisterTables[Index].InitialApicId == InitApicId) {
RegisterTable = &RegisterTables[Index];
- ProcIndex = Index;
+ ProcIndex = Index;
break;
}
}
+
ASSERT (RegisterTable != NULL);
ProgramProcessorRegister (
@@ -1170,9 +1202,9 @@ CpuFeaturesDetect ( VOID
)
{
- CPU_FEATURES_DATA *CpuFeaturesData;
+ CPU_FEATURES_DATA *CpuFeaturesData;
- CpuFeaturesData = GetCpuFeaturesData();
+ CpuFeaturesData = GetCpuFeaturesData ();
CpuInitDataInitialize ();
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c index e2e06e88e0..e635cade5d 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c @@ -13,7 +13,7 @@ #include "RegisterCpuFeatures.h"
-CPU_FEATURES_DATA mCpuFeaturesData = {0};
+CPU_FEATURES_DATA mCpuFeaturesData = { 0 };
/**
Worker function to get CPU_FEATURES_DATA pointer.
@@ -38,17 +38,17 @@ GetMpService ( VOID
)
{
- EFI_STATUS Status;
- MP_SERVICES MpService;
+ EFI_STATUS Status;
+ MP_SERVICES MpService;
//
// Get MP Services Protocol
//
Status = gBS->LocateProtocol (
- &gEfiMpServiceProtocolGuid,
- NULL,
- (VOID **)&MpService.Protocol
- );
+ &gEfiMpServiceProtocolGuid,
+ NULL,
+ (VOID **)&MpService.Protocol
+ );
ASSERT_EFI_ERROR (Status);
return MpService;
@@ -63,15 +63,15 @@ GetMpService ( **/
UINTN
GetProcessorIndex (
- IN CPU_FEATURES_DATA *CpuFeaturesData
+ IN CPU_FEATURES_DATA *CpuFeaturesData
)
{
- EFI_STATUS Status;
- UINTN ProcessorIndex;
- EFI_MP_SERVICES_PROTOCOL *MpServices;
+ EFI_STATUS Status;
+ UINTN ProcessorIndex;
+ EFI_MP_SERVICES_PROTOCOL *MpServices;
MpServices = CpuFeaturesData->MpService.Protocol;
- Status = MpServices->WhoAmI(MpServices, &ProcessorIndex);
+ Status = MpServices->WhoAmI (MpServices, &ProcessorIndex);
ASSERT_EFI_ERROR (Status);
return ProcessorIndex;
}
@@ -88,22 +88,22 @@ GetProcessorIndex ( **/
EFI_STATUS
GetProcessorInformation (
- IN UINTN ProcessorNumber,
- OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
+ IN UINTN ProcessorNumber,
+ OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
)
{
- EFI_STATUS Status;
- EFI_MP_SERVICES_PROTOCOL *MpServices;
- CPU_FEATURES_DATA *CpuFeaturesData;
+ EFI_STATUS Status;
+ EFI_MP_SERVICES_PROTOCOL *MpServices;
+ CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- MpServices = CpuFeaturesData->MpService.Protocol;
+ MpServices = CpuFeaturesData->MpService.Protocol;
Status = MpServices->GetProcessorInfo (
- MpServices,
- ProcessorNumber,
- ProcessorInfoBuffer
- );
+ MpServices,
+ ProcessorNumber,
+ ProcessorInfoBuffer
+ );
return Status;
}
@@ -117,29 +117,29 @@ GetProcessorInformation ( **/
VOID
StartupAllAPsWorker (
- IN EFI_AP_PROCEDURE Procedure,
- IN EFI_EVENT MpEvent
+ IN EFI_AP_PROCEDURE Procedure,
+ IN EFI_EVENT MpEvent
)
{
- EFI_STATUS Status;
- EFI_MP_SERVICES_PROTOCOL *MpServices;
- CPU_FEATURES_DATA *CpuFeaturesData;
+ EFI_STATUS Status;
+ EFI_MP_SERVICES_PROTOCOL *MpServices;
+ CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- MpServices = CpuFeaturesData->MpService.Protocol;
+ MpServices = CpuFeaturesData->MpService.Protocol;
//
// Wakeup all APs
//
Status = MpServices->StartupAllAPs (
- MpServices,
- Procedure,
- FALSE,
- MpEvent,
- 0,
- CpuFeaturesData,
- NULL
- );
+ MpServices,
+ Procedure,
+ FALSE,
+ MpEvent,
+ 0,
+ CpuFeaturesData,
+ NULL
+ );
ASSERT_EFI_ERROR (Status);
}
@@ -150,24 +150,24 @@ StartupAllAPsWorker ( **/
VOID
SwitchNewBsp (
- IN UINTN ProcessorNumber
+ IN UINTN ProcessorNumber
)
{
- EFI_STATUS Status;
- EFI_MP_SERVICES_PROTOCOL *MpServices;
- CPU_FEATURES_DATA *CpuFeaturesData;
+ EFI_STATUS Status;
+ EFI_MP_SERVICES_PROTOCOL *MpServices;
+ CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- MpServices = CpuFeaturesData->MpService.Protocol;
+ MpServices = CpuFeaturesData->MpService.Protocol;
//
// Wakeup all APs
//
Status = MpServices->SwitchBSP (
- MpServices,
- ProcessorNumber,
- TRUE
- );
+ MpServices,
+ ProcessorNumber,
+ TRUE
+ );
ASSERT_EFI_ERROR (Status);
}
@@ -183,16 +183,16 @@ SwitchNewBsp ( **/
VOID
GetNumberOfProcessor (
- OUT UINTN *NumberOfCpus,
- OUT UINTN *NumberOfEnabledProcessors
+ OUT UINTN *NumberOfCpus,
+ OUT UINTN *NumberOfEnabledProcessors
)
{
- EFI_STATUS Status;
- EFI_MP_SERVICES_PROTOCOL *MpServices;
- CPU_FEATURES_DATA *CpuFeaturesData;
+ EFI_STATUS Status;
+ EFI_MP_SERVICES_PROTOCOL *MpServices;
+ CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- MpServices = CpuFeaturesData->MpService.Protocol;
+ MpServices = CpuFeaturesData->MpService.Protocol;
//
// Get the number of CPUs
@@ -219,14 +219,14 @@ CpuFeaturesInitialize ( VOID
)
{
- CPU_FEATURES_DATA *CpuFeaturesData;
- UINTN OldBspNumber;
- EFI_EVENT MpEvent;
- EFI_STATUS Status;
+ CPU_FEATURES_DATA *CpuFeaturesData;
+ UINTN OldBspNumber;
+ EFI_EVENT MpEvent;
+ EFI_STATUS Status;
CpuFeaturesData = GetCpuFeaturesData ();
- OldBspNumber = GetProcessorIndex (CpuFeaturesData);
+ OldBspNumber = GetProcessorIndex (CpuFeaturesData);
CpuFeaturesData->BspNumber = OldBspNumber;
//
@@ -263,6 +263,7 @@ CpuFeaturesInitialize ( do {
Status = gBS->CheckEvent (MpEvent);
} while (Status == EFI_NOT_READY);
+
ASSERT_EFI_ERROR (Status);
}
@@ -273,4 +274,3 @@ CpuFeaturesInitialize ( SwitchNewBsp (CpuFeaturesData->BspNumber);
}
}
-
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c index 4e558e9fee..d4c528b3e9 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c @@ -20,7 +20,7 @@ 0xa694c467, 0x697a, 0x446b, { 0xb9, 0x29, 0x5b, 0x14, 0xa0, 0xcf, 0x39, 0xf } \
}
-EFI_GUID mRegisterCpuFeaturesHobGuid = REGISTER_CPU_FEATURES_GUID;
+EFI_GUID mRegisterCpuFeaturesHobGuid = REGISTER_CPU_FEATURES_GUID;
/**
Worker function to get CPU_FEATURES_DATA pointer.
@@ -32,16 +32,16 @@ GetCpuFeaturesData ( VOID
)
{
- CPU_FEATURES_DATA *CpuInitData;
- EFI_HOB_GUID_TYPE *GuidHob;
- VOID *DataInHob;
- UINT64 Data64;
+ CPU_FEATURES_DATA *CpuInitData;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ VOID *DataInHob;
+ UINT64 Data64;
CpuInitData = NULL;
- GuidHob = GetFirstGuidHob (&mRegisterCpuFeaturesHobGuid);
+ GuidHob = GetFirstGuidHob (&mRegisterCpuFeaturesHobGuid);
if (GuidHob != NULL) {
- DataInHob = GET_GUID_HOB_DATA (GuidHob);
- CpuInitData = (CPU_FEATURES_DATA *) (*(UINTN *) DataInHob);
+ DataInHob = GET_GUID_HOB_DATA (GuidHob);
+ CpuInitData = (CPU_FEATURES_DATA *)(*(UINTN *)DataInHob);
ASSERT (CpuInitData != NULL);
} else {
CpuInitData = AllocateZeroPool (sizeof (CPU_FEATURES_DATA));
@@ -49,10 +49,10 @@ GetCpuFeaturesData ( //
// Build location of CPU MP DATA buffer in HOB
//
- Data64 = (UINT64) (UINTN) CpuInitData;
+ Data64 = (UINT64)(UINTN)CpuInitData;
BuildGuidDataHob (
&mRegisterCpuFeaturesHobGuid,
- (VOID *) &Data64,
+ (VOID *)&Data64,
sizeof (UINT64)
);
}
@@ -70,8 +70,8 @@ GetMpService ( VOID
)
{
- EFI_STATUS Status;
- MP_SERVICES MpService;
+ EFI_STATUS Status;
+ MP_SERVICES MpService;
//
// Get MP Services2 Ppi
@@ -95,12 +95,12 @@ GetMpService ( **/
UINTN
GetProcessorIndex (
- IN CPU_FEATURES_DATA *CpuFeaturesData
+ IN CPU_FEATURES_DATA *CpuFeaturesData
)
{
- EFI_STATUS Status;
- EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
- UINTN ProcessorIndex;
+ EFI_STATUS Status;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
+ UINTN ProcessorIndex;
CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
@@ -126,22 +126,22 @@ GetProcessorIndex ( **/
EFI_STATUS
GetProcessorInformation (
- IN UINTN ProcessorNumber,
- OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
+ IN UINTN ProcessorNumber,
+ OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
)
{
- EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
- EFI_STATUS Status;
- CPU_FEATURES_DATA *CpuFeaturesData;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
+ EFI_STATUS Status;
+ CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
Status = CpuMp2Ppi->GetProcessorInfo (
- CpuMp2Ppi,
- ProcessorNumber,
- ProcessorInfoBuffer
- );
+ CpuMp2Ppi,
+ ProcessorNumber,
+ ProcessorInfoBuffer
+ );
return Status;
}
@@ -155,27 +155,27 @@ GetProcessorInformation ( **/
VOID
StartupAllAPsWorker (
- IN EFI_AP_PROCEDURE Procedure,
- IN EFI_EVENT MpEvent
+ IN EFI_AP_PROCEDURE Procedure,
+ IN EFI_EVENT MpEvent
)
{
- EFI_STATUS Status;
- EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
- CPU_FEATURES_DATA *CpuFeaturesData;
+ EFI_STATUS Status;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
+ CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
//
// Wakeup all APs for data collection.
//
Status = CpuMp2Ppi->StartupAllAPs (
- CpuMp2Ppi,
- Procedure,
- FALSE,
- 0,
- CpuFeaturesData
- );
+ CpuMp2Ppi,
+ Procedure,
+ FALSE,
+ 0,
+ CpuFeaturesData
+ );
ASSERT_EFI_ERROR (Status);
}
@@ -188,12 +188,12 @@ StartupAllAPsWorker ( **/
VOID
StartupAllCPUsWorker (
- IN EFI_AP_PROCEDURE Procedure
+ IN EFI_AP_PROCEDURE Procedure
)
{
- EFI_STATUS Status;
- EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
- CPU_FEATURES_DATA *CpuFeaturesData;
+ EFI_STATUS Status;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
+ CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
@@ -201,12 +201,12 @@ StartupAllCPUsWorker ( // Get MP Services2 Ppi
//
CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
- Status = CpuMp2Ppi->StartupAllCPUs (
- CpuMp2Ppi,
- Procedure,
- 0,
- CpuFeaturesData
- );
+ Status = CpuMp2Ppi->StartupAllCPUs (
+ CpuMp2Ppi,
+ Procedure,
+ 0,
+ CpuFeaturesData
+ );
ASSERT_EFI_ERROR (Status);
}
@@ -217,24 +217,24 @@ StartupAllCPUsWorker ( **/
VOID
SwitchNewBsp (
- IN UINTN ProcessorNumber
+ IN UINTN ProcessorNumber
)
{
- EFI_STATUS Status;
- EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
- CPU_FEATURES_DATA *CpuFeaturesData;
+ EFI_STATUS Status;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
+ CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
//
// Wakeup all APs for data collection.
//
Status = CpuMp2Ppi->SwitchBSP (
- CpuMp2Ppi,
- ProcessorNumber,
- TRUE
- );
+ CpuMp2Ppi,
+ ProcessorNumber,
+ TRUE
+ );
ASSERT_EFI_ERROR (Status);
}
@@ -250,25 +250,25 @@ SwitchNewBsp ( **/
VOID
GetNumberOfProcessor (
- OUT UINTN *NumberOfCpus,
- OUT UINTN *NumberOfEnabledProcessors
+ OUT UINTN *NumberOfCpus,
+ OUT UINTN *NumberOfEnabledProcessors
)
{
- EFI_STATUS Status;
- EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
- CPU_FEATURES_DATA *CpuFeaturesData;
+ EFI_STATUS Status;
+ EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
+ CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData ();
- CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
+ CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
//
// Get the number of CPUs
//
Status = CpuMp2Ppi->GetNumberOfProcessors (
- CpuMp2Ppi,
- NumberOfCpus,
- NumberOfEnabledProcessors
- );
+ CpuMp2Ppi,
+ NumberOfCpus,
+ NumberOfEnabledProcessors
+ );
ASSERT_EFI_ERROR (Status);
}
@@ -286,12 +286,12 @@ CpuFeaturesInitialize ( VOID
)
{
- CPU_FEATURES_DATA *CpuFeaturesData;
- UINTN OldBspNumber;
+ CPU_FEATURES_DATA *CpuFeaturesData;
+ UINTN OldBspNumber;
CpuFeaturesData = GetCpuFeaturesData ();
- OldBspNumber = GetProcessorIndex (CpuFeaturesData);
+ OldBspNumber = GetProcessorIndex (CpuFeaturesData);
CpuFeaturesData->BspNumber = OldBspNumber;
//
@@ -306,4 +306,3 @@ CpuFeaturesInitialize ( SwitchNewBsp (CpuFeaturesData->BspNumber);
}
}
-
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h index e8a4aa644d..4a84954cac 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h @@ -27,66 +27,66 @@ #define CPU_FEATURE_ENTRY_SIGNATURE SIGNATURE_32 ('C', 'F', 'E', 'S')
-#define CPU_FEATURE_NAME_SIZE 128
+#define CPU_FEATURE_NAME_SIZE 128
typedef struct {
- REGISTER_CPU_FEATURE_INFORMATION CpuInfo;
- UINT8 *FeaturesSupportedMask;
- LIST_ENTRY OrderList;
+ REGISTER_CPU_FEATURE_INFORMATION CpuInfo;
+ UINT8 *FeaturesSupportedMask;
+ LIST_ENTRY OrderList;
} CPU_FEATURES_INIT_ORDER;
typedef struct {
- UINT32 Signature;
- LIST_ENTRY Link;
- UINT8 *FeatureMask;
- CHAR8 *FeatureName;
- CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc;
- CPU_FEATURE_SUPPORT SupportFunc;
- CPU_FEATURE_INITIALIZE InitializeFunc;
- UINT8 *ThreadBeforeFeatureBitMask;
- UINT8 *ThreadAfterFeatureBitMask;
- UINT8 *CoreBeforeFeatureBitMask;
- UINT8 *CoreAfterFeatureBitMask;
- UINT8 *PackageBeforeFeatureBitMask;
- UINT8 *PackageAfterFeatureBitMask;
- VOID *ConfigData;
- BOOLEAN BeforeAll;
- BOOLEAN AfterAll;
+ UINT32 Signature;
+ LIST_ENTRY Link;
+ UINT8 *FeatureMask;
+ CHAR8 *FeatureName;
+ CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc;
+ CPU_FEATURE_SUPPORT SupportFunc;
+ CPU_FEATURE_INITIALIZE InitializeFunc;
+ UINT8 *ThreadBeforeFeatureBitMask;
+ UINT8 *ThreadAfterFeatureBitMask;
+ UINT8 *CoreBeforeFeatureBitMask;
+ UINT8 *CoreAfterFeatureBitMask;
+ UINT8 *PackageBeforeFeatureBitMask;
+ UINT8 *PackageAfterFeatureBitMask;
+ VOID *ConfigData;
+ BOOLEAN BeforeAll;
+ BOOLEAN AfterAll;
} CPU_FEATURES_ENTRY;
//
// Flags used when program the register.
//
typedef struct {
- volatile UINTN MemoryMappedLock; // Spinlock used to program mmio
- volatile UINT32 *CoreSemaphoreCount; // Semaphore containers used to program Core semaphore.
- volatile UINT32 *PackageSemaphoreCount; // Semaphore containers used to program Package semaphore.
+ volatile UINTN MemoryMappedLock; // Spinlock used to program mmio
+ volatile UINT32 *CoreSemaphoreCount; // Semaphore containers used to program Core semaphore.
+ volatile UINT32 *PackageSemaphoreCount; // Semaphore containers used to program Package semaphore.
} PROGRAM_CPU_REGISTER_FLAGS;
typedef union {
- EFI_MP_SERVICES_PROTOCOL *Protocol;
- EDKII_PEI_MP_SERVICES2_PPI *Ppi;
+ EFI_MP_SERVICES_PROTOCOL *Protocol;
+ EDKII_PEI_MP_SERVICES2_PPI *Ppi;
} MP_SERVICES;
typedef struct {
- UINTN FeaturesCount;
- UINT32 BitMaskSize;
- LIST_ENTRY FeatureList;
+ UINTN FeaturesCount;
+ UINT32 BitMaskSize;
+ LIST_ENTRY FeatureList;
- CPU_FEATURES_INIT_ORDER *InitOrder;
- UINT8 *CapabilityPcd;
- UINT8 *SettingPcd;
+ CPU_FEATURES_INIT_ORDER *InitOrder;
+ UINT8 *CapabilityPcd;
+ UINT8 *SettingPcd;
- UINT32 NumberOfCpus;
- ACPI_CPU_DATA *AcpiCpuData;
+ UINT32 NumberOfCpus;
+ ACPI_CPU_DATA *AcpiCpuData;
- CPU_REGISTER_TABLE *RegisterTable;
- CPU_REGISTER_TABLE *PreSmmRegisterTable;
- UINTN BspNumber;
+ CPU_REGISTER_TABLE *RegisterTable;
+ CPU_REGISTER_TABLE *PreSmmRegisterTable;
+ UINTN BspNumber;
- PROGRAM_CPU_REGISTER_FLAGS CpuFlags;
+ PROGRAM_CPU_REGISTER_FLAGS CpuFlags;
- MP_SERVICES MpService;
+ MP_SERVICES MpService;
} CPU_FEATURES_DATA;
#define CPU_FEATURE_ENTRY_FROM_LINK(a) \
@@ -116,7 +116,7 @@ GetCpuFeaturesData ( **/
UINTN
GetProcessorIndex (
- IN CPU_FEATURES_DATA *CpuFeaturesData
+ IN CPU_FEATURES_DATA *CpuFeaturesData
);
/**
@@ -131,8 +131,8 @@ GetProcessorIndex ( **/
EFI_STATUS
GetProcessorInformation (
- IN UINTN ProcessorNumber,
- OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
+ IN UINTN ProcessorNumber,
+ OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
);
/**
@@ -145,8 +145,8 @@ GetProcessorInformation ( **/
VOID
StartupAllAPsWorker (
- IN EFI_AP_PROCEDURE Procedure,
- IN EFI_EVENT MpEvent
+ IN EFI_AP_PROCEDURE Procedure,
+ IN EFI_EVENT MpEvent
);
/**
@@ -161,8 +161,8 @@ StartupAllAPsWorker ( **/
VOID
GetNumberOfProcessor (
- OUT UINTN *NumberOfCpus,
- OUT UINTN *NumberOfEnabledProcessors
+ OUT UINTN *NumberOfCpus,
+ OUT UINTN *NumberOfEnabledProcessors
);
/**
@@ -172,7 +172,7 @@ GetNumberOfProcessor ( **/
VOID
SwitchNewBsp (
- IN UINTN ProcessorNumber
+ IN UINTN ProcessorNumber
);
/**
@@ -184,8 +184,8 @@ SwitchNewBsp ( **/
VOID
DumpCpuFeatureMask (
- IN UINT8 *FeatureMask,
- IN UINT32 BitMaskSize
+ IN UINT8 *FeatureMask,
+ IN UINT32 BitMaskSize
);
/**
@@ -212,9 +212,9 @@ DumpCpuFeature ( **/
CPU_FEATURE_DEPENDENCE_TYPE
DetectFeatureScope (
- IN CPU_FEATURES_ENTRY *CpuFeature,
- IN BOOLEAN Before,
- IN UINT8 *NextCpuFeatureMask
+ IN CPU_FEATURES_ENTRY *CpuFeature,
+ IN BOOLEAN Before,
+ IN UINT8 *NextCpuFeatureMask
);
/**
@@ -228,9 +228,9 @@ DetectFeatureScope ( **/
CPU_FEATURE_DEPENDENCE_TYPE
DetectNoneNeighborhoodFeatureScope (
- IN CPU_FEATURES_ENTRY *CpuFeature,
- IN BOOLEAN Before,
- IN LIST_ENTRY *FeatureList
+ IN CPU_FEATURES_ENTRY *CpuFeature,
+ IN BOOLEAN Before,
+ IN LIST_ENTRY *FeatureList
);
/**
@@ -242,7 +242,7 @@ DetectNoneNeighborhoodFeatureScope ( VOID
EFIAPI
SetProcessorRegister (
- IN OUT VOID *Buffer
+ IN OUT VOID *Buffer
);
/**
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c index ffe34ffb48..0285aaf5c9 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c @@ -17,17 +17,18 @@ **/
VOID
DumpCpuFeatureMask (
- IN UINT8 *FeatureMask,
- IN UINT32 BitMaskSize
+ IN UINT8 *FeatureMask,
+ IN UINT32 BitMaskSize
)
{
- UINTN Index;
- UINT8 *Data8;
+ UINTN Index;
+ UINT8 *Data8;
- Data8 = (UINT8 *) FeatureMask;
+ Data8 = (UINT8 *)FeatureMask;
for (Index = 0; Index < BitMaskSize; Index++) {
DEBUG ((DEBUG_INFO, " %02x ", *Data8++));
}
+
DEBUG ((DEBUG_INFO, "\n"));
}
@@ -44,7 +45,6 @@ DumpCpuFeature ( IN UINT32 BitMaskSize
)
{
-
if (CpuFeature->FeatureName != NULL) {
DEBUG ((DEBUG_INFO, "FeatureName: %a\n", CpuFeature->FeatureName));
} else {
@@ -64,8 +64,8 @@ DumpCpuFeature ( **/
BOOLEAN
IsBitMaskMatchCheck (
- IN UINT8 *FeatureMask,
- IN UINT8 *DependentBitMask
+ IN UINT8 *FeatureMask,
+ IN UINT8 *DependentBitMask
)
{
UINTN Index;
@@ -82,6 +82,7 @@ IsBitMaskMatchCheck ( return TRUE;
}
}
+
return FALSE;
}
@@ -98,14 +99,14 @@ IsBitMaskMatchCheck ( **/
BOOLEAN
FindSpecifyFeature (
- IN LIST_ENTRY *FeatureList,
- IN LIST_ENTRY *CurrentEntry,
- IN BOOLEAN SearchFormer,
- IN UINT8 *FeatureMask
+ IN LIST_ENTRY *FeatureList,
+ IN LIST_ENTRY *CurrentEntry,
+ IN BOOLEAN SearchFormer,
+ IN UINT8 *FeatureMask
)
{
- CPU_FEATURES_ENTRY *CpuFeature;
- LIST_ENTRY *NextEntry;
+ CPU_FEATURES_ENTRY *CpuFeature;
+ LIST_ENTRY *NextEntry;
//
// Check whether exist the not neighborhood entry first.
@@ -165,9 +166,9 @@ FindSpecifyFeature ( **/
CPU_FEATURE_DEPENDENCE_TYPE
DetectFeatureScope (
- IN CPU_FEATURES_ENTRY *CpuFeature,
- IN BOOLEAN Before,
- IN UINT8 *NextCpuFeatureMask
+ IN CPU_FEATURES_ENTRY *CpuFeature,
+ IN BOOLEAN Before,
+ IN UINT8 *NextCpuFeatureMask
)
{
//
@@ -185,17 +186,20 @@ DetectFeatureScope ( if (Before) {
if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) &&
- IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageBeforeFeatureBitMask)) {
+ IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageBeforeFeatureBitMask))
+ {
return PackageDepType;
}
if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) &&
- IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreBeforeFeatureBitMask)) {
+ IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreBeforeFeatureBitMask))
+ {
return CoreDepType;
}
if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) &&
- IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadBeforeFeatureBitMask)) {
+ IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadBeforeFeatureBitMask))
+ {
return ThreadDepType;
}
@@ -203,17 +207,20 @@ DetectFeatureScope ( }
if ((CpuFeature->PackageAfterFeatureBitMask != NULL) &&
- IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageAfterFeatureBitMask)) {
+ IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageAfterFeatureBitMask))
+ {
return PackageDepType;
}
if ((CpuFeature->CoreAfterFeatureBitMask != NULL) &&
- IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreAfterFeatureBitMask)) {
+ IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreAfterFeatureBitMask))
+ {
return CoreDepType;
}
if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) &&
- IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadAfterFeatureBitMask)) {
+ IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadAfterFeatureBitMask))
+ {
return ThreadDepType;
}
@@ -231,24 +238,27 @@ DetectFeatureScope ( **/
CPU_FEATURE_DEPENDENCE_TYPE
DetectNoneNeighborhoodFeatureScope (
- IN CPU_FEATURES_ENTRY *CpuFeature,
- IN BOOLEAN Before,
- IN LIST_ENTRY *FeatureList
+ IN CPU_FEATURES_ENTRY *CpuFeature,
+ IN BOOLEAN Before,
+ IN LIST_ENTRY *FeatureList
)
{
if (Before) {
if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) &&
- FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->PackageBeforeFeatureBitMask)) {
+ FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->PackageBeforeFeatureBitMask))
+ {
return PackageDepType;
}
if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) &&
- FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->CoreBeforeFeatureBitMask)) {
+ FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->CoreBeforeFeatureBitMask))
+ {
return CoreDepType;
}
if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) &&
- FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->ThreadBeforeFeatureBitMask)) {
+ FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->ThreadBeforeFeatureBitMask))
+ {
return ThreadDepType;
}
@@ -256,17 +266,20 @@ DetectNoneNeighborhoodFeatureScope ( }
if ((CpuFeature->PackageAfterFeatureBitMask != NULL) &&
- FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->PackageAfterFeatureBitMask)) {
+ FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->PackageAfterFeatureBitMask))
+ {
return PackageDepType;
}
if ((CpuFeature->CoreAfterFeatureBitMask != NULL) &&
- FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->CoreAfterFeatureBitMask)) {
+ FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->CoreAfterFeatureBitMask))
+ {
return CoreDepType;
}
if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) &&
- FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->ThreadAfterFeatureBitMask)) {
+ FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->ThreadAfterFeatureBitMask))
+ {
return ThreadDepType;
}
@@ -294,17 +307,17 @@ DetectNoneNeighborhoodFeatureScope ( **/
BOOLEAN
AdjustFeaturesDependence (
- IN OUT CPU_FEATURES_ENTRY *PreviousFeature,
- IN OUT CPU_FEATURES_ENTRY *CurrentFeature,
- IN CPU_FEATURES_ENTRY *FindFeature,
- IN BOOLEAN Before
+ IN OUT CPU_FEATURES_ENTRY *PreviousFeature,
+ IN OUT CPU_FEATURES_ENTRY *CurrentFeature,
+ IN CPU_FEATURES_ENTRY *FindFeature,
+ IN BOOLEAN Before
)
{
- CPU_FEATURE_DEPENDENCE_TYPE PreDependType;
- CPU_FEATURE_DEPENDENCE_TYPE CurrentDependType;
+ CPU_FEATURE_DEPENDENCE_TYPE PreDependType;
+ CPU_FEATURE_DEPENDENCE_TYPE CurrentDependType;
- PreDependType = DetectFeatureScope(PreviousFeature, Before, FindFeature->FeatureMask);
- CurrentDependType = DetectFeatureScope(CurrentFeature, Before, FindFeature->FeatureMask);
+ PreDependType = DetectFeatureScope (PreviousFeature, Before, FindFeature->FeatureMask);
+ CurrentDependType = DetectFeatureScope (CurrentFeature, Before, FindFeature->FeatureMask);
//
// If previous feature has no dependence with the find featue.
@@ -336,16 +349,16 @@ AdjustFeaturesDependence ( **/
VOID
AdjustEntry (
- IN LIST_ENTRY *FeatureList,
- IN OUT LIST_ENTRY *FindEntry,
- IN OUT LIST_ENTRY *CurrentEntry,
- IN BOOLEAN Before
+ IN LIST_ENTRY *FeatureList,
+ IN OUT LIST_ENTRY *FindEntry,
+ IN OUT LIST_ENTRY *CurrentEntry,
+ IN BOOLEAN Before
)
{
- LIST_ENTRY *PreviousEntry;
- CPU_FEATURES_ENTRY *PreviousFeature;
- CPU_FEATURES_ENTRY *CurrentFeature;
- CPU_FEATURES_ENTRY *FindFeature;
+ LIST_ENTRY *PreviousEntry;
+ CPU_FEATURES_ENTRY *PreviousFeature;
+ CPU_FEATURES_ENTRY *CurrentFeature;
+ CPU_FEATURES_ENTRY *FindFeature;
//
// For CPU feature which has core or package type dependence, later code need to insert
@@ -363,11 +376,10 @@ AdjustEntry ( if (Before) {
PreviousEntry = GetPreviousNode (FeatureList, FindEntry);
} else {
-
PreviousEntry = GetNextNode (FeatureList, FindEntry);
}
- CurrentFeature = CPU_FEATURE_ENTRY_FROM_LINK (CurrentEntry);
+ CurrentFeature = CPU_FEATURE_ENTRY_FROM_LINK (CurrentEntry);
RemoveEntryList (CurrentEntry);
if (IsNull (FeatureList, PreviousEntry)) {
@@ -407,7 +419,6 @@ AdjustEntry ( }
}
-
/**
Checks and adjusts current CPU features per dependency relationship.
@@ -419,14 +430,14 @@ AdjustEntry ( **/
BOOLEAN
InsertToBeforeEntry (
- IN LIST_ENTRY *FeatureList,
- IN LIST_ENTRY *CurrentEntry,
- IN UINT8 *FeatureMask
+ IN LIST_ENTRY *FeatureList,
+ IN LIST_ENTRY *CurrentEntry,
+ IN UINT8 *FeatureMask
)
{
- LIST_ENTRY *CheckEntry;
- CPU_FEATURES_ENTRY *CheckFeature;
- BOOLEAN Swapped;
+ LIST_ENTRY *CheckEntry;
+ CPU_FEATURES_ENTRY *CheckFeature;
+ BOOLEAN Swapped;
Swapped = FALSE;
@@ -441,6 +452,7 @@ InsertToBeforeEntry ( Swapped = TRUE;
break;
}
+
CheckEntry = CheckEntry->ForwardLink;
}
@@ -458,14 +470,14 @@ InsertToBeforeEntry ( **/
BOOLEAN
InsertToAfterEntry (
- IN LIST_ENTRY *FeatureList,
- IN LIST_ENTRY *CurrentEntry,
- IN UINT8 *FeatureMask
+ IN LIST_ENTRY *FeatureList,
+ IN LIST_ENTRY *CurrentEntry,
+ IN UINT8 *FeatureMask
)
{
- LIST_ENTRY *CheckEntry;
- CPU_FEATURES_ENTRY *CheckFeature;
- BOOLEAN Swapped;
+ LIST_ENTRY *CheckEntry;
+ CPU_FEATURES_ENTRY *CheckFeature;
+ BOOLEAN Swapped;
Swapped = FALSE;
@@ -480,6 +492,7 @@ InsertToAfterEntry ( Swapped = TRUE;
break;
}
+
CheckEntry = CheckEntry->ForwardLink;
}
@@ -493,22 +506,22 @@ InsertToAfterEntry ( **/
VOID
CheckCpuFeaturesDependency (
- IN LIST_ENTRY *FeatureList
+ IN LIST_ENTRY *FeatureList
)
{
- LIST_ENTRY *CurrentEntry;
- CPU_FEATURES_ENTRY *CpuFeature;
- LIST_ENTRY *CheckEntry;
- CPU_FEATURES_ENTRY *CheckFeature;
- BOOLEAN Swapped;
- LIST_ENTRY *TempEntry;
- LIST_ENTRY *NextEntry;
+ LIST_ENTRY *CurrentEntry;
+ CPU_FEATURES_ENTRY *CpuFeature;
+ LIST_ENTRY *CheckEntry;
+ CPU_FEATURES_ENTRY *CheckFeature;
+ BOOLEAN Swapped;
+ LIST_ENTRY *TempEntry;
+ LIST_ENTRY *NextEntry;
CurrentEntry = GetFirstNode (FeatureList);
while (!IsNull (FeatureList, CurrentEntry)) {
- Swapped = FALSE;
+ Swapped = FALSE;
CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (CurrentEntry);
- NextEntry = CurrentEntry->ForwardLink;
+ NextEntry = CurrentEntry->ForwardLink;
if (CpuFeature->BeforeAll) {
//
// Check all features dispatched before this entry
@@ -526,8 +539,10 @@ CheckCpuFeaturesDependency ( Swapped = TRUE;
break;
}
+
CheckEntry = CheckEntry->ForwardLink;
}
+
if (Swapped) {
CurrentEntry = NextEntry;
continue;
@@ -550,11 +565,13 @@ CheckCpuFeaturesDependency ( RemoveEntryList (CurrentEntry);
InsertHeadList (CheckEntry, CurrentEntry);
CurrentEntry = TempEntry;
- Swapped = TRUE;
+ Swapped = TRUE;
break;
}
+
CheckEntry = CheckEntry->ForwardLink;
}
+
if (Swapped) {
CurrentEntry = NextEntry;
continue;
@@ -622,18 +639,18 @@ CheckCpuFeaturesDependency ( **/
RETURN_STATUS
RegisterCpuFeatureWorker (
- IN CPU_FEATURES_DATA *CpuFeaturesData,
- IN CPU_FEATURES_ENTRY *CpuFeature
+ IN CPU_FEATURES_DATA *CpuFeaturesData,
+ IN CPU_FEATURES_ENTRY *CpuFeature
)
{
- EFI_STATUS Status;
- CPU_FEATURES_ENTRY *CpuFeatureEntry;
- LIST_ENTRY *Entry;
- BOOLEAN FeatureExist;
+ EFI_STATUS Status;
+ CPU_FEATURES_ENTRY *CpuFeatureEntry;
+ LIST_ENTRY *Entry;
+ BOOLEAN FeatureExist;
- FeatureExist = FALSE;
+ FeatureExist = FALSE;
CpuFeatureEntry = NULL;
- Entry = GetFirstNode (&CpuFeaturesData->FeatureList);
+ Entry = GetFirstNode (&CpuFeaturesData->FeatureList);
while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) {
CpuFeatureEntry = CPU_FEATURE_ENTRY_FROM_LINK (Entry);
if (CompareMem (CpuFeature->FeatureMask, CpuFeatureEntry->FeatureMask, CpuFeaturesData->BitMaskSize) == 0) {
@@ -643,6 +660,7 @@ RegisterCpuFeatureWorker ( FeatureExist = TRUE;
break;
}
+
Entry = Entry->ForwardLink;
}
@@ -661,55 +679,71 @@ RegisterCpuFeatureWorker ( if (CpuFeature->GetConfigDataFunc != NULL) {
CpuFeatureEntry->GetConfigDataFunc = CpuFeature->GetConfigDataFunc;
}
+
if (CpuFeature->SupportFunc != NULL) {
CpuFeatureEntry->SupportFunc = CpuFeature->SupportFunc;
}
+
if (CpuFeature->InitializeFunc != NULL) {
CpuFeatureEntry->InitializeFunc = CpuFeature->InitializeFunc;
}
+
if (CpuFeature->FeatureName != NULL) {
if (CpuFeatureEntry->FeatureName == NULL) {
CpuFeatureEntry->FeatureName = AllocatePool (CPU_FEATURE_NAME_SIZE);
ASSERT (CpuFeatureEntry->FeatureName != NULL);
}
+
Status = AsciiStrCpyS (CpuFeatureEntry->FeatureName, CPU_FEATURE_NAME_SIZE, CpuFeature->FeatureName);
ASSERT_EFI_ERROR (Status);
FreePool (CpuFeature->FeatureName);
}
+
if (CpuFeature->ThreadBeforeFeatureBitMask != NULL) {
if (CpuFeatureEntry->ThreadBeforeFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->ThreadBeforeFeatureBitMask);
}
+
CpuFeatureEntry->ThreadBeforeFeatureBitMask = CpuFeature->ThreadBeforeFeatureBitMask;
}
+
if (CpuFeature->ThreadAfterFeatureBitMask != NULL) {
if (CpuFeatureEntry->ThreadAfterFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->ThreadAfterFeatureBitMask);
}
+
CpuFeatureEntry->ThreadAfterFeatureBitMask = CpuFeature->ThreadAfterFeatureBitMask;
}
+
if (CpuFeature->CoreBeforeFeatureBitMask != NULL) {
if (CpuFeatureEntry->CoreBeforeFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->CoreBeforeFeatureBitMask);
}
+
CpuFeatureEntry->CoreBeforeFeatureBitMask = CpuFeature->CoreBeforeFeatureBitMask;
}
+
if (CpuFeature->CoreAfterFeatureBitMask != NULL) {
if (CpuFeatureEntry->CoreAfterFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->CoreAfterFeatureBitMask);
}
+
CpuFeatureEntry->CoreAfterFeatureBitMask = CpuFeature->CoreAfterFeatureBitMask;
}
+
if (CpuFeature->PackageBeforeFeatureBitMask != NULL) {
if (CpuFeatureEntry->PackageBeforeFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->PackageBeforeFeatureBitMask);
}
+
CpuFeatureEntry->PackageBeforeFeatureBitMask = CpuFeature->PackageBeforeFeatureBitMask;
}
+
if (CpuFeature->PackageAfterFeatureBitMask != NULL) {
if (CpuFeatureEntry->PackageAfterFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->PackageAfterFeatureBitMask);
}
+
CpuFeatureEntry->PackageAfterFeatureBitMask = CpuFeature->PackageAfterFeatureBitMask;
}
@@ -719,6 +753,7 @@ RegisterCpuFeatureWorker ( FreePool (CpuFeature->FeatureMask);
FreePool (CpuFeature);
}
+
//
// Verify CPU features dependency can change CPU feature order
//
@@ -735,12 +770,12 @@ RegisterCpuFeatureWorker ( **/
VOID
SetCpuFeaturesBitMask (
- IN UINT8 **FeaturesBitMask,
- IN UINT32 Feature,
- IN UINTN BitMaskSize
+ IN UINT8 **FeaturesBitMask,
+ IN UINT32 Feature,
+ IN UINTN BitMaskSize
)
{
- UINT8 *CpuFeaturesBitMask;
+ UINT8 *CpuFeaturesBitMask;
ASSERT (FeaturesBitMask != NULL);
CpuFeaturesBitMask = *FeaturesBitMask;
@@ -751,7 +786,7 @@ SetCpuFeaturesBitMask ( }
CpuFeaturesBitMask += (Feature / 8);
- *CpuFeaturesBitMask |= (UINT8) (1 << (Feature % 8));
+ *CpuFeaturesBitMask |= (UINT8)(1 << (Feature % 8));
}
/**
@@ -803,27 +838,27 @@ SetCpuFeaturesBitMask ( RETURN_STATUS
EFIAPI
RegisterCpuFeature (
- IN CHAR8 *FeatureName OPTIONAL,
- IN CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc OPTIONAL,
- IN CPU_FEATURE_SUPPORT SupportFunc OPTIONAL,
- IN CPU_FEATURE_INITIALIZE InitializeFunc OPTIONAL,
+ IN CHAR8 *FeatureName OPTIONAL,
+ IN CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc OPTIONAL,
+ IN CPU_FEATURE_SUPPORT SupportFunc OPTIONAL,
+ IN CPU_FEATURE_INITIALIZE InitializeFunc OPTIONAL,
...
)
{
- EFI_STATUS Status;
- VA_LIST Marker;
- UINT32 Feature;
- CPU_FEATURES_ENTRY *CpuFeature;
- UINT8 *FeatureMask;
- UINT8 *ThreadBeforeFeatureBitMask;
- UINT8 *ThreadAfterFeatureBitMask;
- UINT8 *CoreBeforeFeatureBitMask;
- UINT8 *CoreAfterFeatureBitMask;
- UINT8 *PackageBeforeFeatureBitMask;
- UINT8 *PackageAfterFeatureBitMask;
- BOOLEAN BeforeAll;
- BOOLEAN AfterAll;
- CPU_FEATURES_DATA *CpuFeaturesData;
+ EFI_STATUS Status;
+ VA_LIST Marker;
+ UINT32 Feature;
+ CPU_FEATURES_ENTRY *CpuFeature;
+ UINT8 *FeatureMask;
+ UINT8 *ThreadBeforeFeatureBitMask;
+ UINT8 *ThreadAfterFeatureBitMask;
+ UINT8 *CoreBeforeFeatureBitMask;
+ UINT8 *CoreAfterFeatureBitMask;
+ UINT8 *PackageBeforeFeatureBitMask;
+ UINT8 *PackageAfterFeatureBitMask;
+ BOOLEAN BeforeAll;
+ BOOLEAN AfterAll;
+ CPU_FEATURES_DATA *CpuFeaturesData;
FeatureMask = NULL;
ThreadBeforeFeatureBitMask = NULL;
@@ -832,8 +867,8 @@ RegisterCpuFeature ( CoreAfterFeatureBitMask = NULL;
PackageBeforeFeatureBitMask = NULL;
PackageAfterFeatureBitMask = NULL;
- BeforeAll = FALSE;
- AfterAll = FALSE;
+ BeforeAll = FALSE;
+ AfterAll = FALSE;
CpuFeaturesData = GetCpuFeaturesData ();
if (CpuFeaturesData->FeaturesCount == 0) {
@@ -844,7 +879,7 @@ RegisterCpuFeature ( //
ASSERT (PcdGetSize (PcdCpuFeaturesSetting) == PcdGetSize (PcdCpuFeaturesCapability));
ASSERT (PcdGetSize (PcdCpuFeaturesSetting) == PcdGetSize (PcdCpuFeaturesSupport));
- CpuFeaturesData->BitMaskSize = (UINT32) PcdGetSize (PcdCpuFeaturesSetting);
+ CpuFeaturesData->BitMaskSize = (UINT32)PcdGetSize (PcdCpuFeaturesSetting);
}
VA_START (Marker, InitializeFunc);
@@ -853,19 +888,27 @@ RegisterCpuFeature ( //
// It's invalid to require a feature is before AND after all other features.
//
- ASSERT ((Feature & (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL))
- != (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL));
+ ASSERT (
+ (Feature & (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL))
+ != (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL)
+ );
//
// It's invalid to require feature A is before AND after before feature B,
// either in thread level, core level or package level.
//
- ASSERT ((Feature & (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER))
- != (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER));
- ASSERT ((Feature & (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER))
- != (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER));
- ASSERT ((Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER))
- != (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER));
+ ASSERT (
+ (Feature & (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER))
+ != (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER)
+ );
+ ASSERT (
+ (Feature & (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER))
+ != (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER)
+ );
+ ASSERT (
+ (Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER))
+ != (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER)
+ );
if (Feature < CPU_FEATURE_THREAD_BEFORE) {
BeforeAll = ((Feature & CPU_FEATURE_BEFORE_ALL) != 0) ? TRUE : FALSE;
AfterAll = ((Feature & CPU_FEATURE_AFTER_ALL) != 0) ? TRUE : FALSE;
@@ -885,8 +928,10 @@ RegisterCpuFeature ( } else if ((Feature & CPU_FEATURE_PACKAGE_AFTER) != 0) {
SetCpuFeaturesBitMask (&PackageAfterFeatureBitMask, Feature & ~CPU_FEATURE_PACKAGE_AFTER, CpuFeaturesData->BitMaskSize);
}
+
Feature = VA_ARG (Marker, UINT32);
}
+
VA_END (Marker);
CpuFeature = AllocateZeroPool (sizeof (CPU_FEATURES_ENTRY));
@@ -905,7 +950,7 @@ RegisterCpuFeature ( CpuFeature->SupportFunc = SupportFunc;
CpuFeature->InitializeFunc = InitializeFunc;
if (FeatureName != NULL) {
- CpuFeature->FeatureName = AllocatePool (CPU_FEATURE_NAME_SIZE);
+ CpuFeature->FeatureName = AllocatePool (CPU_FEATURE_NAME_SIZE);
ASSERT (CpuFeature->FeatureName != NULL);
Status = AsciiStrCpyS (CpuFeature->FeatureName, CPU_FEATURE_NAME_SIZE, FeatureName);
ASSERT_EFI_ERROR (Status);
@@ -927,18 +972,18 @@ GetAcpiCpuData ( VOID
)
{
- EFI_STATUS Status;
- UINTN NumberOfCpus;
- UINTN NumberOfEnabledProcessors;
- ACPI_CPU_DATA *AcpiCpuData;
- UINTN TableSize;
- CPU_REGISTER_TABLE *RegisterTable;
- UINTN Index;
- EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer;
-
- AcpiCpuData = (ACPI_CPU_DATA *) (UINTN) PcdGet64 (PcdCpuS3DataAddress);
+ EFI_STATUS Status;
+ UINTN NumberOfCpus;
+ UINTN NumberOfEnabledProcessors;
+ ACPI_CPU_DATA *AcpiCpuData;
+ UINTN TableSize;
+ CPU_REGISTER_TABLE *RegisterTable;
+ UINTN Index;
+ EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer;
+
+ AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);
if (AcpiCpuData == NULL) {
- AcpiCpuData = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (ACPI_CPU_DATA)));
+ AcpiCpuData = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (ACPI_CPU_DATA)));
ASSERT (AcpiCpuData != NULL);
ZeroMem (AcpiCpuData, sizeof (ACPI_CPU_DATA));
@@ -952,14 +997,15 @@ GetAcpiCpuData ( AcpiCpuData->NumberOfCpus = (UINT32)NumberOfCpus;
}
- if (AcpiCpuData->CpuFeatureInitData.RegisterTable == 0 ||
- AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0) {
+ if ((AcpiCpuData->CpuFeatureInitData.RegisterTable == 0) ||
+ (AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0))
+ {
//
// Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for all CPUs
//
- NumberOfCpus = AcpiCpuData->NumberOfCpus;
- TableSize = 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE);
- RegisterTable = AllocatePages (EFI_SIZE_TO_PAGES (TableSize));
+ NumberOfCpus = AcpiCpuData->NumberOfCpus;
+ TableSize = 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE);
+ RegisterTable = AllocatePages (EFI_SIZE_TO_PAGES (TableSize));
ASSERT (RegisterTable != NULL);
for (Index = 0; Index < NumberOfCpus; Index++) {
@@ -976,9 +1022,11 @@ GetAcpiCpuData ( RegisterTable[NumberOfCpus + Index].AllocatedSize = 0;
RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0;
}
+
if (AcpiCpuData->CpuFeatureInitData.RegisterTable == 0) {
AcpiCpuData->CpuFeatureInitData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable;
}
+
if (AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0) {
AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);
}
@@ -995,14 +1043,14 @@ GetAcpiCpuData ( STATIC
VOID
EnlargeRegisterTable (
- IN OUT CPU_REGISTER_TABLE *RegisterTable
+ IN OUT CPU_REGISTER_TABLE *RegisterTable
)
{
EFI_PHYSICAL_ADDRESS Address;
UINTN UsedPages;
UsedPages = RegisterTable->AllocatedSize / EFI_PAGE_SIZE;
- Address = (UINTN)AllocatePages (UsedPages + 1);
+ Address = (UINTN)AllocatePages (UsedPages + 1);
ASSERT (Address != 0);
//
@@ -1011,8 +1059,8 @@ EnlargeRegisterTable ( //
if (RegisterTable->AllocatedSize > 0) {
CopyMem (
- (VOID *) (UINTN) Address,
- (VOID *) (UINTN) RegisterTable->RegisterTableEntry,
+ (VOID *)(UINTN)Address,
+ (VOID *)(UINTN)RegisterTable->RegisterTableEntry,
RegisterTable->AllocatedSize
);
@@ -1045,27 +1093,27 @@ EnlargeRegisterTable ( **/
VOID
CpuRegisterTableWriteWorker (
- IN BOOLEAN PreSmmFlag,
- IN UINTN ProcessorNumber,
- IN REGISTER_TYPE RegisterType,
- IN UINT64 Index,
- IN UINT8 ValidBitStart,
- IN UINT8 ValidBitLength,
- IN UINT64 Value,
- IN BOOLEAN TestThenWrite
+ IN BOOLEAN PreSmmFlag,
+ IN UINTN ProcessorNumber,
+ IN REGISTER_TYPE RegisterType,
+ IN UINT64 Index,
+ IN UINT8 ValidBitStart,
+ IN UINT8 ValidBitLength,
+ IN UINT64 Value,
+ IN BOOLEAN TestThenWrite
)
{
- CPU_FEATURES_DATA *CpuFeaturesData;
- ACPI_CPU_DATA *AcpiCpuData;
- CPU_REGISTER_TABLE *RegisterTable;
- CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
+ CPU_FEATURES_DATA *CpuFeaturesData;
+ ACPI_CPU_DATA *AcpiCpuData;
+ CPU_REGISTER_TABLE *RegisterTable;
+ CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
CpuFeaturesData = GetCpuFeaturesData ();
if (CpuFeaturesData->RegisterTable == NULL) {
AcpiCpuData = GetAcpiCpuData ();
ASSERT ((AcpiCpuData != NULL) && (AcpiCpuData->CpuFeatureInitData.RegisterTable != 0));
- CpuFeaturesData->RegisterTable = (CPU_REGISTER_TABLE *) (UINTN) AcpiCpuData->CpuFeatureInitData.RegisterTable;
- CpuFeaturesData->PreSmmRegisterTable = (CPU_REGISTER_TABLE *) (UINTN) AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable;
+ CpuFeaturesData->RegisterTable = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.RegisterTable;
+ CpuFeaturesData->PreSmmRegisterTable = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable;
}
if (PreSmmFlag) {
@@ -1081,10 +1129,10 @@ CpuRegisterTableWriteWorker ( //
// Append entry in the register table.
//
- RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;
+ RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;
RegisterTableEntry[RegisterTable->TableLength].RegisterType = RegisterType;
- RegisterTableEntry[RegisterTable->TableLength].Index = (UINT32) Index;
- RegisterTableEntry[RegisterTable->TableLength].HighIndex = (UINT32) RShiftU64 (Index, 32);
+ RegisterTableEntry[RegisterTable->TableLength].Index = (UINT32)Index;
+ RegisterTableEntry[RegisterTable->TableLength].HighIndex = (UINT32)RShiftU64 (Index, 32);
RegisterTableEntry[RegisterTable->TableLength].ValidBitStart = ValidBitStart;
RegisterTableEntry[RegisterTable->TableLength].ValidBitLength = ValidBitLength;
RegisterTableEntry[RegisterTable->TableLength].Value = Value;
@@ -1110,18 +1158,18 @@ CpuRegisterTableWriteWorker ( VOID
EFIAPI
CpuRegisterTableWrite (
- IN UINTN ProcessorNumber,
- IN REGISTER_TYPE RegisterType,
- IN UINT64 Index,
- IN UINT64 ValueMask,
- IN UINT64 Value
+ IN UINTN ProcessorNumber,
+ IN REGISTER_TYPE RegisterType,
+ IN UINT64 Index,
+ IN UINT64 ValueMask,
+ IN UINT64 Value
)
{
- UINT8 Start;
- UINT8 End;
- UINT8 Length;
+ UINT8 Start;
+ UINT8 End;
+ UINT8 Length;
- Start = (UINT8)LowBitSet64 (ValueMask);
+ Start = (UINT8)LowBitSet64 (ValueMask);
End = (UINT8)HighBitSet64 (ValueMask);
Length = End - Start + 1;
CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index, Start, Length, Value, FALSE);
@@ -1144,18 +1192,18 @@ CpuRegisterTableWrite ( VOID
EFIAPI
CpuRegisterTableTestThenWrite (
- IN UINTN ProcessorNumber,
- IN REGISTER_TYPE RegisterType,
- IN UINT64 Index,
- IN UINT64 ValueMask,
- IN UINT64 Value
+ IN UINTN ProcessorNumber,
+ IN REGISTER_TYPE RegisterType,
+ IN UINT64 Index,
+ IN UINT64 ValueMask,
+ IN UINT64 Value
)
{
- UINT8 Start;
- UINT8 End;
- UINT8 Length;
+ UINT8 Start;
+ UINT8 End;
+ UINT8 Length;
- Start = (UINT8)LowBitSet64 (ValueMask);
+ Start = (UINT8)LowBitSet64 (ValueMask);
End = (UINT8)HighBitSet64 (ValueMask);
Length = End - Start + 1;
CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index, Start, Length, Value, TRUE);
@@ -1178,18 +1226,18 @@ CpuRegisterTableTestThenWrite ( VOID
EFIAPI
PreSmmCpuRegisterTableWrite (
- IN UINTN ProcessorNumber,
- IN REGISTER_TYPE RegisterType,
- IN UINT64 Index,
- IN UINT64 ValueMask,
- IN UINT64 Value
+ IN UINTN ProcessorNumber,
+ IN REGISTER_TYPE RegisterType,
+ IN UINT64 Index,
+ IN UINT64 ValueMask,
+ IN UINT64 Value
)
{
UINT8 Start;
UINT8 End;
UINT8 Length;
- Start = (UINT8)LowBitSet64 (ValueMask);
+ Start = (UINT8)LowBitSet64 (ValueMask);
End = (UINT8)HighBitSet64 (ValueMask);
Length = End - Start + 1;
CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index, Start, Length, Value, FALSE);
@@ -1208,14 +1256,15 @@ PreSmmCpuRegisterTableWrite ( **/
BOOLEAN
IsCpuFeatureSetInCpuPcd (
- IN UINT8 *CpuBitMask,
- IN UINTN CpuBitMaskSize,
- IN UINT32 Feature
+ IN UINT8 *CpuBitMask,
+ IN UINTN CpuBitMaskSize,
+ IN UINT32 Feature
)
{
if ((Feature >> 3) >= CpuBitMaskSize) {
return FALSE;
}
+
return ((*(CpuBitMask + (Feature >> 3)) & (1 << (Feature & 0x07))) != 0);
}
@@ -1236,7 +1285,7 @@ IsCpuFeatureSetInCpuPcd ( BOOLEAN
EFIAPI
IsCpuFeatureSupported (
- IN UINT32 Feature
+ IN UINT32 Feature
)
{
return IsCpuFeatureSetInCpuPcd (
@@ -1260,7 +1309,7 @@ IsCpuFeatureSupported ( BOOLEAN
EFIAPI
IsCpuFeatureInSetting (
- IN UINT32 Feature
+ IN UINT32 Feature
)
{
return IsCpuFeatureSetInCpuPcd (
@@ -1280,11 +1329,11 @@ IsCpuFeatureInSetting ( VOID
EFIAPI
SwitchBspAfterFeaturesInitialize (
- IN UINTN ProcessorNumber
+ IN UINTN ProcessorNumber
)
{
- CPU_FEATURES_DATA *CpuFeaturesData;
+ CPU_FEATURES_DATA *CpuFeaturesData;
- CpuFeaturesData = GetCpuFeaturesData ();
+ CpuFeaturesData = GetCpuFeaturesData ();
CpuFeaturesData->BspNumber = ProcessorNumber;
}
diff --git a/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c b/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c index 8e2a420f80..e0149df044 100644 --- a/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c +++ b/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c @@ -27,10 +27,10 @@ InternalX86GetTimerFrequency ( VOID
)
{
- UINTN Divisor;
+ UINTN Divisor;
GetApicTimerState (&Divisor, NULL, NULL);
- return PcdGet32(PcdFSBClock) / (UINT32)Divisor;
+ return PcdGet32 (PcdFSBClock) / (UINT32)Divisor;
}
/**
@@ -48,13 +48,13 @@ InternalX86GetTimerFrequency ( VOID
EFIAPI
InternalX86Delay (
- IN UINT32 Delay
+ IN UINT32 Delay
)
{
- INT32 Ticks;
- UINT32 Times;
- UINT32 InitCount;
- UINT32 StartTick;
+ INT32 Ticks;
+ UINT32 Times;
+ UINT32 InitCount;
+ UINT32 StartTick;
//
// In case Delay is too larger, separate it into several small delay slot.
@@ -65,13 +65,13 @@ InternalX86Delay ( //
InitCount = GetApicTimerInitCount ();
ASSERT (InitCount != 0);
- Times = Delay / (InitCount / 2);
- Delay = Delay % (InitCount / 2);
+ Times = Delay / (InitCount / 2);
+ Delay = Delay % (InitCount / 2);
//
// Get Start Tick and do delay
//
- StartTick = GetApicTimerCurrentCount ();
+ StartTick = GetApicTimerCurrentCount ();
do {
//
// Wait until time out by Delay value
@@ -111,7 +111,7 @@ InternalX86Delay ( UINTN
EFIAPI
MicroSecondDelay (
- IN UINTN MicroSeconds
+ IN UINTN MicroSeconds
)
{
InternalX86Delay (
@@ -139,7 +139,7 @@ MicroSecondDelay ( UINTN
EFIAPI
NanoSecondDelay (
- IN UINTN NanoSeconds
+ IN UINTN NanoSeconds
)
{
InternalX86Delay (
@@ -200,8 +200,8 @@ GetPerformanceCounter ( UINT64
EFIAPI
GetPerformanceCounterProperties (
- OUT UINT64 *StartValue OPTIONAL,
- OUT UINT64 *EndValue OPTIONAL
+ OUT UINT64 *StartValue OPTIONAL,
+ OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
@@ -212,7 +212,7 @@ GetPerformanceCounterProperties ( *EndValue = 0;
}
- return (UINT64) InternalX86GetTimerFrequency ();
+ return (UINT64)InternalX86GetTimerFrequency ();
}
/**
@@ -229,7 +229,7 @@ GetPerformanceCounterProperties ( UINT64
EFIAPI
GetTimeInNanoSecond (
- IN UINT64 Ticks
+ IN UINT64 Ticks
)
{
UINT64 Frequency;
@@ -251,9 +251,9 @@ GetTimeInNanoSecond ( // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,
// i.e. highest bit set in Remainder should <= 33.
//
- Shift = MAX (0, HighBitSet64 (Remainder) - 33);
- Remainder = RShiftU64 (Remainder, (UINTN) Shift);
- Frequency = RShiftU64 (Frequency, (UINTN) Shift);
+ Shift = MAX (0, HighBitSet64 (Remainder) - 33);
+ Remainder = RShiftU64 (Remainder, (UINTN)Shift);
+ Frequency = RShiftU64 (Frequency, (UINTN)Shift);
NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
return NanoSeconds;
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c index 24bd6d0a94..249cd40f9d 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c @@ -14,9 +14,9 @@ ///
/// Page Table Entry
///
-#define IA32_PG_P BIT0
-#define IA32_PG_RW BIT1
-#define IA32_PG_PS BIT7
+#define IA32_PG_P BIT0
+#define IA32_PG_RW BIT1
+#define IA32_PG_PS BIT7
/**
@@ -28,14 +28,14 @@ **/
VOID
StmGen4GPageTable (
- IN UINTN PageTableBase
+ IN UINTN PageTableBase
)
{
- UINTN Index;
- UINT32 *Pte;
- UINT32 Address;
+ UINTN Index;
+ UINT32 *Pte;
+ UINT32 Address;
- Pte = (UINT32*)(UINTN)PageTableBase;
+ Pte = (UINT32 *)(UINTN)PageTableBase;
Address = 0;
for (Index = 0; Index < SIZE_4KB / sizeof (*Pte); Index++) {
@@ -63,7 +63,7 @@ StmGen4GPageTable ( UINT32
EFIAPI
SmmStmExceptionHandler (
- IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
+ IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
)
{
// TBD - SmmStmExceptionHandler, record information
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c index fa3a866ab6..78de7f8407 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c @@ -34,8 +34,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// MSRs required for configuration of SMM Code Access Check
//
-#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
-#define SMM_CODE_ACCESS_CHK_BIT BIT58
+#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
+#define SMM_CODE_ACCESS_CHK_BIT BIT58
//
// Set default value to assume SMRR is not supported
@@ -86,7 +86,7 @@ CpuFeaturesLibInitialization ( AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
FamilyId = (RegEax >> 8) & 0xf;
ModelId = (RegEax >> 4) & 0xf;
- if (FamilyId == 0x06 || FamilyId == 0x0f) {
+ if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
ModelId = ModelId | ((RegEax >> 12) & 0xf0);
}
@@ -110,7 +110,7 @@ CpuFeaturesLibInitialization ( // SMRR Physical Base and SMM Physical Mask MSRs are not available.
//
if (FamilyId == 0x06) {
- if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) {
+ if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || (ModelId == 0x35) || (ModelId == 0x36)) {
mSmrrSupported = FALSE;
}
}
@@ -123,7 +123,7 @@ CpuFeaturesLibInitialization ( // Processor Family MSRs
//
if (FamilyId == 0x06) {
- if (ModelId == 0x17 || ModelId == 0x0f) {
+ if ((ModelId == 0x17) || (ModelId == 0x0f)) {
mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;
mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;
}
@@ -204,7 +204,7 @@ SmmCpuFeaturesInitializeProcessor ( //
// Configure SMBASE.
//
- CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+ CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
//
@@ -216,7 +216,7 @@ SmmCpuFeaturesInitializeProcessor ( // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)
// is set, then the MSR is locked and can not be modified.
//
- if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) {
+ if (mSmrrSupported && (mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE)) {
FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);
if ((FeatureControl & BIT3) == 0) {
if ((FeatureControl & BIT0) == 0) {
@@ -242,7 +242,8 @@ SmmCpuFeaturesInitializeProcessor ( //
if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
(CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
- ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {
+ ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))
+ {
//
// Print message and halt if CPU is Monarch
//
@@ -263,7 +264,7 @@ SmmCpuFeaturesInitializeProcessor ( AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
FamilyId = (RegEax >> 8) & 0xf;
ModelId = (RegEax >> 4) & 0xf;
- if (FamilyId == 0x06 || FamilyId == 0x0f) {
+ if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
ModelId = ModelId | ((RegEax >> 12) & 0xf0);
}
@@ -276,10 +277,11 @@ SmmCpuFeaturesInitializeProcessor ( // Intel(R) Core(TM) Processor Family MSRs.
//
if (FamilyId == 0x06) {
- if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46 ||
- ModelId == 0x3D || ModelId == 0x47 || ModelId == 0x4E || ModelId == 0x4F ||
- ModelId == 0x3F || ModelId == 0x56 || ModelId == 0x57 || ModelId == 0x5C ||
- ModelId == 0x8C) {
+ if ((ModelId == 0x3C) || (ModelId == 0x45) || (ModelId == 0x46) ||
+ (ModelId == 0x3D) || (ModelId == 0x47) || (ModelId == 0x4E) || (ModelId == 0x4F) ||
+ (ModelId == 0x3F) || (ModelId == 0x56) || (ModelId == 0x57) || (ModelId == 0x5C) ||
+ (ModelId == 0x8C))
+ {
//
// Check to see if the CPU supports the SMM Code Access Check feature
// Do not access this MSR unless the CPU supports the SmmRegFeatureControl
@@ -382,7 +384,7 @@ SmmCpuFeaturesDisableSmrr ( )
{
if (mSmrrSupported && mNeedConfigureMtrrs) {
- AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);
+ AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);
}
}
@@ -397,7 +399,7 @@ SmmCpuFeaturesReenableSmrr ( )
{
if (mSmrrSupported && mNeedConfigureMtrrs) {
- AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
+ AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
}
}
@@ -458,9 +460,10 @@ SmmCpuFeaturesIsSmmRegisterSupported ( IN SMM_REG_NAME RegName
)
{
- if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
+ if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
return TRUE;
}
+
return FALSE;
}
@@ -483,9 +486,10 @@ SmmCpuFeaturesGetSmmRegister ( IN SMM_REG_NAME RegName
)
{
- if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
+ if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);
}
+
return 0;
}
@@ -508,7 +512,7 @@ SmmCpuFeaturesSetSmmRegister ( IN UINT64 Value
)
{
- if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
+ if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
}
}
@@ -605,9 +609,8 @@ SmmCpuFeaturesCompleteSmmReadyToLock ( VOID *
EFIAPI
SmmCpuFeaturesAllocatePageTableMemory (
- IN UINTN Pages
+ IN UINTN Pages
)
{
return NULL;
}
-
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c index c92387625d..4e8f897f5e 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -24,21 +24,21 @@ #include "CpuFeaturesLib.h"
#include "SmmStm.h"
-#define TXT_EVTYPE_BASE 0x400
-#define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
+#define TXT_EVTYPE_BASE 0x400
+#define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
-#define RDWR_ACCS 3
-#define FULL_ACCS 7
+#define RDWR_ACCS 3
+#define FULL_ACCS 7
EFI_HANDLE mStmSmmCpuHandle = NULL;
-BOOLEAN mLockLoadMonitor = FALSE;
+BOOLEAN mLockLoadMonitor = FALSE;
//
// Template of STM_RSC_END structure for copying.
//
-GLOBAL_REMOVE_IF_UNREFERENCED STM_RSC_END mRscEndNode = {
- {END_OF_RESOURCES, sizeof (STM_RSC_END)},
+GLOBAL_REMOVE_IF_UNREFERENCED STM_RSC_END mRscEndNode = {
+ { END_OF_RESOURCES, sizeof (STM_RSC_END) },
};
GLOBAL_REMOVE_IF_UNREFERENCED UINT8 *mStmResourcesPtr = NULL;
@@ -52,7 +52,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mStmState = 0; // System Configuration Table pointing to STM Configuration Table
//
GLOBAL_REMOVE_IF_UNREFERENCED
-EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol = {
+EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol = {
LoadMonitor,
AddPiResource,
DeletePiResource,
@@ -60,10 +60,7 @@ EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol = { GetMonitorState,
};
-
-
-
-#define CPUID1_EDX_XD_SUPPORT 0x100000
+#define CPUID1_EDX_XD_SUPPORT 0x100000
//
// External global variables associated with SMI Handler Template
@@ -146,10 +143,10 @@ SmmCpuFeaturesLibStmConstructor ( //
// Retrieve MSEG location from MSEG SRAM HOB
//
- SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);
+ SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);
if (SmramDescriptor->PhysicalSize > 0) {
- mMsegBase = (UINTN)SmramDescriptor->CpuStart;
- mMsegSize = (UINTN)SmramDescriptor->PhysicalSize;
+ mMsegBase = (UINTN)SmramDescriptor->CpuStart;
+ mMsegSize = (UINTN)SmramDescriptor->PhysicalSize;
}
} else if (PcdGet32 (PcdCpuMsegSize) > 0) {
//
@@ -162,6 +159,7 @@ SmmCpuFeaturesLibStmConstructor ( DEBUG ((DEBUG_ERROR, "Not enough SMRAM resource to allocate MSEG size %08x\n", PcdGet32 (PcdCpuMsegSize)));
}
}
+
if (mMsegBase > 0) {
DEBUG ((DEBUG_INFO, "MsegBase: 0x%08x, MsegSize: 0x%08x\n", mMsegBase, mMsegSize));
}
@@ -251,16 +249,16 @@ SmmCpuFeaturesInstallSmiHandler ( IN UINT32 Cr3
)
{
- EFI_STATUS Status;
- TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
- VOID *Hob;
- UINT32 RegEax;
- UINT32 RegEdx;
- EFI_PROCESSOR_INFORMATION ProcessorInfo;
+ EFI_STATUS Status;
+ TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
+ VOID *Hob;
+ UINT32 RegEax;
+ UINT32 RegEdx;
+ EFI_PROCESSOR_INFORMATION ProcessorInfo;
CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET), &gcStmPsd, sizeof (gcStmPsd));
- Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET);
- Psd->SmmGdtPtr = GdtBase;
+ Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET);
+ Psd->SmmGdtPtr = GdtBase;
Psd->SmmGdtSize = (UINT32)GdtSize;
//
@@ -293,49 +291,49 @@ SmmCpuFeaturesInstallSmiHandler ( //
// Set the value at the top of the CPU stack to the CPU Index
//
- *(UINTN*)(UINTN)gStmSmiStack = CpuIndex;
+ *(UINTN *)(UINTN)gStmSmiStack = CpuIndex;
//
// Copy template to CPU specific SMI handler location
//
CopyMem (
- (VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET),
- (VOID*)gcStmSmiHandlerTemplate,
+ (VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET),
+ (VOID *)gcStmSmiHandlerTemplate,
gcStmSmiHandlerSize
);
Psd->SmmSmiHandlerRip = SmBase + SMM_HANDLER_OFFSET + gcStmSmiHandlerOffset;
- Psd->SmmSmiHandlerRsp = (UINTN)SmiStack + StackSize - sizeof(UINTN);
+ Psd->SmmSmiHandlerRsp = (UINTN)SmiStack + StackSize - sizeof (UINTN);
Psd->SmmCr3 = Cr3;
- DEBUG((DEBUG_INFO, "CpuSmmStmExceptionStackSize - %x\n", PcdGet32(PcdCpuSmmStmExceptionStackSize)));
- DEBUG((DEBUG_INFO, "Pages - %x\n", EFI_SIZE_TO_PAGES(PcdGet32(PcdCpuSmmStmExceptionStackSize))));
- Psd->StmProtectionExceptionHandler.SpeRsp = (UINT64)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));
+ DEBUG ((DEBUG_INFO, "CpuSmmStmExceptionStackSize - %x\n", PcdGet32 (PcdCpuSmmStmExceptionStackSize)));
+ DEBUG ((DEBUG_INFO, "Pages - %x\n", EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize))));
+ Psd->StmProtectionExceptionHandler.SpeRsp = (UINT64)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));
Psd->StmProtectionExceptionHandler.SpeRsp += EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));
- Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)GetStmResource ();
+ Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)GetStmResource ();
//
// Get the APIC ID for the CPU specified by CpuIndex
//
Status = mSmmCpuFeaturesLibMpService->GetProcessorInfo (
- mSmmCpuFeaturesLibMpService,
- CpuIndex,
- &ProcessorInfo
- );
+ mSmmCpuFeaturesLibMpService,
+ CpuIndex,
+ &ProcessorInfo
+ );
ASSERT_EFI_ERROR (Status);
Psd->LocalApicId = (UINT32)ProcessorInfo.ProcessorId;
- Psd->AcpiRsdp = 0;
+ Psd->AcpiRsdp = 0;
Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
if (Hob != NULL) {
- Psd->PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
+ Psd->PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else {
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
- Psd->PhysicalAddressBits = (UINT8) RegEax;
+ Psd->PhysicalAddressBits = (UINT8)RegEax;
} else {
Psd->PhysicalAddressBits = 36;
}
@@ -385,6 +383,7 @@ SmmEndOfDxeEventNotify ( break;
}
}
+
if (Rsdp == NULL) {
for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {
if (CompareGuid (&(gST->ConfigurationTable[Index].VendorGuid), &gEfiAcpi10TableGuid)) {
@@ -416,8 +415,8 @@ StmSmmConfigurationTableInit ( VOID
)
{
- EFI_STATUS Status;
- VOID *Registration;
+ EFI_STATUS Status;
+ VOID *Registration;
Status = gSmst->SmmInstallProtocolInterface (
&mStmSmmCpuHandle,
@@ -468,19 +467,19 @@ GetMonitorState ( **/
BOOLEAN
HandleSingleResource (
- IN STM_RSC *Resource,
- IN STM_RSC *Record
+ IN STM_RSC *Resource,
+ IN STM_RSC *Record
)
{
- UINT64 ResourceLo;
- UINT64 ResourceHi;
- UINT64 RecordLo;
- UINT64 RecordHi;
+ UINT64 ResourceLo;
+ UINT64 ResourceHi;
+ UINT64 RecordLo;
+ UINT64 RecordHi;
ResourceLo = 0;
ResourceHi = 0;
- RecordLo = 0;
- RecordHi = 0;
+ RecordLo = 0;
+ RecordHi = 0;
//
// Calling code is responsible for making sure that
@@ -488,62 +487,69 @@ HandleSingleResource ( // thus we use just one of them as switch variable.
//
switch (Resource->Header.RscType) {
- case MEM_RANGE:
- case MMIO_RANGE:
- ResourceLo = Resource->Mem.Base;
- ResourceHi = Resource->Mem.Base + Resource->Mem.Length;
- RecordLo = Record->Mem.Base;
- RecordHi = Record->Mem.Base + Record->Mem.Length;
- if (Resource->Mem.RWXAttributes != Record->Mem.RWXAttributes) {
- if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {
- Record->Mem.RWXAttributes = Resource->Mem.RWXAttributes | Record->Mem.RWXAttributes;
- return TRUE;
- } else {
+ case MEM_RANGE:
+ case MMIO_RANGE:
+ ResourceLo = Resource->Mem.Base;
+ ResourceHi = Resource->Mem.Base + Resource->Mem.Length;
+ RecordLo = Record->Mem.Base;
+ RecordHi = Record->Mem.Base + Record->Mem.Length;
+ if (Resource->Mem.RWXAttributes != Record->Mem.RWXAttributes) {
+ if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {
+ Record->Mem.RWXAttributes = Resource->Mem.RWXAttributes | Record->Mem.RWXAttributes;
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+ }
+
+ break;
+ case IO_RANGE:
+ case TRAPPED_IO_RANGE:
+ ResourceLo = (UINT64)Resource->Io.Base;
+ ResourceHi = (UINT64)Resource->Io.Base + (UINT64)Resource->Io.Length;
+ RecordLo = (UINT64)Record->Io.Base;
+ RecordHi = (UINT64)Record->Io.Base + (UINT64)Record->Io.Length;
+ break;
+ case PCI_CFG_RANGE:
+ if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) ||
+ (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex))
+ {
return FALSE;
}
- }
- break;
- case IO_RANGE:
- case TRAPPED_IO_RANGE:
- ResourceLo = (UINT64) Resource->Io.Base;
- ResourceHi = (UINT64) Resource->Io.Base + (UINT64) Resource->Io.Length;
- RecordLo = (UINT64) Record->Io.Base;
- RecordHi = (UINT64) Record->Io.Base + (UINT64) Record->Io.Length;
- break;
- case PCI_CFG_RANGE:
- if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) ||
- (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex)) {
- return FALSE;
- }
- if (CompareMem (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof(STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) {
- return FALSE;
- }
- ResourceLo = (UINT64) Resource->PciCfg.Base;
- ResourceHi = (UINT64) Resource->PciCfg.Base + (UINT64) Resource->PciCfg.Length;
- RecordLo = (UINT64) Record->PciCfg.Base;
- RecordHi = (UINT64) Record->PciCfg.Base + (UINT64) Record->PciCfg.Length;
- if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) {
- if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {
- Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes;
- return TRUE;
- } else {
+
+ if (CompareMem (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof (STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) {
return FALSE;
}
- }
- break;
- case MACHINE_SPECIFIC_REG:
- //
- // Special case - merge MSR masks in place.
- //
- if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) {
+
+ ResourceLo = (UINT64)Resource->PciCfg.Base;
+ ResourceHi = (UINT64)Resource->PciCfg.Base + (UINT64)Resource->PciCfg.Length;
+ RecordLo = (UINT64)Record->PciCfg.Base;
+ RecordHi = (UINT64)Record->PciCfg.Base + (UINT64)Record->PciCfg.Length;
+ if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) {
+ if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {
+ Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes;
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+ }
+
+ break;
+ case MACHINE_SPECIFIC_REG:
+ //
+ // Special case - merge MSR masks in place.
+ //
+ if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) {
+ return FALSE;
+ }
+
+ Record->Msr.ReadMask |= Resource->Msr.ReadMask;
+ Record->Msr.WriteMask |= Resource->Msr.WriteMask;
+ return TRUE;
+ default:
return FALSE;
- }
- Record->Msr.ReadMask |= Resource->Msr.ReadMask;
- Record->Msr.WriteMask |= Resource->Msr.WriteMask;
- return TRUE;
- default:
- return FALSE;
}
+
//
// If resources are disjoint
//
@@ -557,6 +563,7 @@ HandleSingleResource ( if ((ResourceLo >= RecordLo) && (ResourceHi <= RecordHi)) {
return TRUE;
}
+
//
// Resources are overlapping.
// Resource and record are merged.
@@ -565,22 +572,22 @@ HandleSingleResource ( ResourceHi = (ResourceHi > RecordHi) ? ResourceHi : RecordHi;
switch (Resource->Header.RscType) {
- case MEM_RANGE:
- case MMIO_RANGE:
- Record->Mem.Base = ResourceLo;
- Record->Mem.Length = ResourceHi - ResourceLo;
- break;
- case IO_RANGE:
- case TRAPPED_IO_RANGE:
- Record->Io.Base = (UINT16) ResourceLo;
- Record->Io.Length = (UINT16) (ResourceHi - ResourceLo);
- break;
- case PCI_CFG_RANGE:
- Record->PciCfg.Base = (UINT16) ResourceLo;
- Record->PciCfg.Length = (UINT16) (ResourceHi - ResourceLo);
- break;
- default:
- return FALSE;
+ case MEM_RANGE:
+ case MMIO_RANGE:
+ Record->Mem.Base = ResourceLo;
+ Record->Mem.Length = ResourceHi - ResourceLo;
+ break;
+ case IO_RANGE:
+ case TRAPPED_IO_RANGE:
+ Record->Io.Base = (UINT16)ResourceLo;
+ Record->Io.Length = (UINT16)(ResourceHi - ResourceLo);
+ break;
+ case PCI_CFG_RANGE:
+ Record->PciCfg.Base = (UINT16)ResourceLo;
+ Record->PciCfg.Length = (UINT16)(ResourceHi - ResourceLo);
+ break;
+ default:
+ return FALSE;
}
return TRUE;
@@ -595,10 +602,10 @@ HandleSingleResource ( **/
VOID
AddSingleResource (
- IN STM_RSC *Resource
+ IN STM_RSC *Resource
)
{
- STM_RSC *Record;
+ STM_RSC *Record;
Record = (STM_RSC *)mStmResourcesPtr;
@@ -606,6 +613,7 @@ AddSingleResource ( if (Record->Header.RscType == END_OF_RESOURCES) {
break;
}
+
//
// Go to next record if resource and record types don't match.
//
@@ -613,12 +621,14 @@ AddSingleResource ( Record = (STM_RSC *)((UINTN)Record + Record->Header.Length);
continue;
}
+
//
// Record is handled inside of procedure - don't adjust.
//
if (HandleSingleResource (Resource, Record)) {
- return ;
+ return;
}
+
Record = (STM_RSC *)((UINTN)Record + Record->Header.Length);
}
@@ -626,19 +636,19 @@ AddSingleResource ( // Add resource to the end of area.
//
CopyMem (
- mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode),
+ mStmResourcesPtr + mStmResourceSizeUsed - sizeof (mRscEndNode),
Resource,
Resource->Header.Length
);
CopyMem (
- mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode) + Resource->Header.Length,
+ mStmResourcesPtr + mStmResourceSizeUsed - sizeof (mRscEndNode) + Resource->Header.Length,
&mRscEndNode,
- sizeof(mRscEndNode)
+ sizeof (mRscEndNode)
);
- mStmResourceSizeUsed += Resource->Header.Length;
+ mStmResourceSizeUsed += Resource->Header.Length;
mStmResourceSizeAvailable = mStmResourceTotalSize - mStmResourceSizeUsed;
- return ;
+ return;
}
/**
@@ -652,13 +662,13 @@ AddSingleResource ( **/
VOID
AddResource (
- IN STM_RSC *ResourceList,
- IN UINT32 NumEntries OPTIONAL
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
)
{
- UINT32 Count;
- UINTN Index;
- STM_RSC *Resource;
+ UINT32 Count;
+ UINTN Index;
+ STM_RSC *Resource;
if (NumEntries == 0) {
Count = 0xFFFFFFFF;
@@ -670,12 +680,14 @@ AddResource ( for (Index = 0; Index < Count; Index++) {
if (Resource->Header.RscType == END_OF_RESOURCES) {
- return ;
+ return;
}
+
AddSingleResource (Resource);
Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
}
- return ;
+
+ return;
}
/**
@@ -692,14 +704,14 @@ AddResource ( **/
BOOLEAN
ValidateResource (
- IN STM_RSC *ResourceList,
- IN UINT32 NumEntries OPTIONAL
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
)
{
- UINT32 Count;
- UINTN Index;
- STM_RSC *Resource;
- UINTN SubIndex;
+ UINT32 Count;
+ UINTN Index;
+ STM_RSC *Resource;
+ UINTN SubIndex;
//
// If NumEntries == 0 make it very big. Scan will be terminated by
@@ -724,21 +736,23 @@ ValidateResource ( switch (Resource->Header.RscType) {
case END_OF_RESOURCES:
if (Resource->Header.Length != sizeof (STM_RSC_END)) {
- return FALSE;
+ return FALSE;
}
+
//
// If we are passed actual number of resources to add,
// END_OF_RESOURCES structure between them is considered an
// error. If NumEntries == 0 END_OF_RESOURCES is a termination.
//
if (NumEntries != 0) {
- return FALSE;
+ return FALSE;
} else {
//
// If NumEntries == 0 and list reached end - return success.
//
return TRUE;
}
+
break;
case MEM_RANGE:
@@ -750,6 +764,7 @@ ValidateResource ( if (Resource->Mem.RWXAttributes > FULL_ACCS) {
return FALSE;
}
+
break;
case IO_RANGE:
@@ -761,35 +776,42 @@ ValidateResource ( if ((Resource->Io.Base + Resource->Io.Length) > 0xFFFF) {
return FALSE;
}
+
break;
case PCI_CFG_RANGE:
DEBUG ((DEBUG_INFO, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", Resource->PciCfg.OriginatingBusNumber, Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice, Resource->PciCfg.PciDevicePath[0].PciFunction));
- if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof(STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) {
+ if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof (STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) {
return FALSE;
}
+
for (SubIndex = 0; SubIndex <= Resource->PciCfg.LastNodeIndex; SubIndex++) {
if ((Resource->PciCfg.PciDevicePath[SubIndex].PciDevice > 0x1F) || (Resource->PciCfg.PciDevicePath[SubIndex].PciFunction > 7)) {
return FALSE;
}
}
+
if ((Resource->PciCfg.Base + Resource->PciCfg.Length) > 0x1000) {
return FALSE;
}
+
break;
case MACHINE_SPECIFIC_REG:
if (Resource->Header.Length != sizeof (STM_RSC_MSR_DESC)) {
return FALSE;
}
+
break;
- default :
+ default:
DEBUG ((DEBUG_ERROR, "ValidateResource - Unknown RscType(%x)\n", Resource->Header.RscType));
return FALSE;
}
+
Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
}
+
return TRUE;
}
@@ -808,13 +830,13 @@ ValidateResource ( **/
UINTN
GetResourceSize (
- IN STM_RSC *ResourceList,
- IN UINT32 NumEntries OPTIONAL
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
)
{
- UINT32 Count;
- UINTN Index;
- STM_RSC *Resource;
+ UINT32 Count;
+ UINTN Index;
+ STM_RSC *Resource;
Resource = ResourceList;
@@ -837,6 +859,7 @@ GetResourceSize ( if (Resource->Header.RscType == END_OF_RESOURCES) {
break;
}
+
Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
}
@@ -859,8 +882,8 @@ GetResourceSize ( EFI_STATUS
EFIAPI
AddPiResource (
- IN STM_RSC *ResourceList,
- IN UINT32 NumEntries OPTIONAL
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
)
{
EFI_STATUS Status;
@@ -884,7 +907,7 @@ AddPiResource ( //
// First time allocation
//
- NewResourceSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (ResourceSize + sizeof(mRscEndNode)));
+ NewResourceSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (ResourceSize + sizeof (mRscEndNode)));
DEBUG ((DEBUG_INFO, "Allocate - 0x%08x\n", NewResourceSize));
Status = gSmst->SmmAllocatePages (
AllocateAnyPages,
@@ -899,11 +922,11 @@ AddPiResource ( //
// Copy EndResource for initialization
//
- mStmResourcesPtr = (UINT8 *)(UINTN)NewResource;
+ mStmResourcesPtr = (UINT8 *)(UINTN)NewResource;
mStmResourceTotalSize = NewResourceSize;
- CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode));
- mStmResourceSizeUsed = sizeof(mRscEndNode);
- mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode);
+ CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof (mRscEndNode));
+ mStmResourceSizeUsed = sizeof (mRscEndNode);
+ mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof (mRscEndNode);
//
// Let SmmCore change resource ptr
@@ -925,6 +948,7 @@ AddPiResource ( if (EFI_ERROR (Status)) {
return Status;
}
+
CopyMem ((VOID *)(UINTN)NewResource, mStmResourcesPtr, mStmResourceSizeUsed);
mStmResourceSizeAvailable = NewResourceSize - mStmResourceSizeUsed;
@@ -934,7 +958,7 @@ AddPiResource ( );
mStmResourceTotalSize = NewResourceSize;
- mStmResourcesPtr = (UINT8 *)(UINTN)NewResource;
+ mStmResourcesPtr = (UINT8 *)(UINTN)NewResource;
//
// Let SmmCore change resource ptr
@@ -966,8 +990,8 @@ AddPiResource ( EFI_STATUS
EFIAPI
DeletePiResource (
- IN STM_RSC *ResourceList,
- IN UINT32 NumEntries OPTIONAL
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
)
{
if (ResourceList != NULL) {
@@ -975,12 +999,13 @@ DeletePiResource ( ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
+
//
// Delete all
//
- CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode));
- mStmResourceSizeUsed = sizeof(mRscEndNode);
- mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode);
+ CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof (mRscEndNode));
+ mStmResourceSizeUsed = sizeof (mRscEndNode);
+ mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof (mRscEndNode);
return EFI_SUCCESS;
}
@@ -1000,8 +1025,8 @@ DeletePiResource ( EFI_STATUS
EFIAPI
GetPiResource (
- OUT STM_RSC *ResourceList,
- IN OUT UINT32 *ResourceSize
+ OUT STM_RSC *ResourceList,
+ IN OUT UINT32 *ResourceSize
)
{
if (*ResourceSize < mStmResourceSizeUsed) {
@@ -1029,7 +1054,7 @@ EnableMsegMsr ( {
MSR_IA32_SMM_MONITOR_CTL_REGISTER SmmMonitorCtl;
- SmmMonitorCtl.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
+ SmmMonitorCtl.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
SmmMonitorCtl.Bits.Valid = 1;
AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, SmmMonitorCtl.Uint64);
}
@@ -1067,18 +1092,18 @@ GetVmcsSize ( **/
BOOLEAN
StmCheckStmImage (
- IN EFI_PHYSICAL_ADDRESS StmImage,
- IN UINTN StmImageSize
+ IN EFI_PHYSICAL_ADDRESS StmImage,
+ IN UINTN StmImageSize
)
{
- UINTN MinMsegSize;
- STM_HEADER *StmHeader;
- IA32_VMX_MISC_REGISTER VmxMiscMsr;
+ UINTN MinMsegSize;
+ STM_HEADER *StmHeader;
+ IA32_VMX_MISC_REGISTER VmxMiscMsr;
//
// Check to see if STM image is compatible with CPU
//
- StmHeader = (STM_HEADER *)(UINTN)StmImage;
+ StmHeader = (STM_HEADER *)(UINTN)StmImage;
VmxMiscMsr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);
if (StmHeader->HwStmHdr.MsegHeaderRevision != VmxMiscMsr.Bits.MsegRevisionIdentifier) {
DEBUG ((DEBUG_ERROR, "STM Image not compatible with CPU\n"));
@@ -1101,8 +1126,8 @@ StmCheckStmImage ( //
// We will create page table, just in case that SINIT does not create it.
//
- if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE(6)) {
- MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE(6);
+ if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE (6)) {
+ MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE (6);
}
}
@@ -1133,8 +1158,8 @@ StmCheckStmImage ( **/
VOID
StmLoadStmImage (
- IN EFI_PHYSICAL_ADDRESS StmImage,
- IN UINTN StmImageSize
+ IN EFI_PHYSICAL_ADDRESS StmImage,
+ IN UINTN StmImageSize
)
{
MSR_IA32_SMM_MONITOR_CTL_REGISTER SmmMonitorCtl;
@@ -1145,7 +1170,7 @@ StmLoadStmImage ( // Get MSEG base address from MSR_IA32_SMM_MONITOR_CTL
//
SmmMonitorCtl.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
- MsegBase = SmmMonitorCtl.Bits.MsegBase << 12;
+ MsegBase = SmmMonitorCtl.Bits.MsegBase << 12;
//
// Zero all of MSEG base address
@@ -1181,8 +1206,8 @@ StmLoadStmImage ( EFI_STATUS
EFIAPI
LoadMonitor (
- IN EFI_PHYSICAL_ADDRESS StmImage,
- IN UINTN StmImageSize
+ IN EFI_PHYSICAL_ADDRESS StmImage,
+ IN UINTN StmImageSize
)
{
MSR_IA32_SMM_MONITOR_CTL_REGISTER SmmMonitorCtl;
@@ -1201,7 +1226,7 @@ LoadMonitor ( }
// Record STM_HASH to PCR 0, just in case it is NOT TXT launch, we still need provide the evidence.
- TpmMeasureAndLogData(
+ TpmMeasureAndLogData (
0, // PcrIndex
TXT_EVTYPE_STM_HASH, // EventType
NULL, // EventLog
@@ -1226,7 +1251,7 @@ LoadMonitor ( **/
VOID *
-GetStmResource(
+GetStmResource (
VOID
)
{
@@ -1241,19 +1266,19 @@ GetStmResource( **/
VOID
NotifyStmResourceChange (
- VOID *StmResource
+ VOID *StmResource
)
{
UINTN Index;
TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
- Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET);
+ Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET);
Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
}
- return ;
-}
+ return;
+}
/**
This is STM setup BIOS callback.
@@ -1278,4 +1303,3 @@ SmmStmTeardown ( {
mStmState &= ~EFI_SM_MONITOR_STATE_ACTIVATED;
}
-
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h index da551cc4a6..597c3abf00 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h @@ -21,7 +21,7 @@ **/
VOID
StmGen4GPageTable (
- IN UINTN PageTableBase
+ IN UINTN PageTableBase
);
/**
@@ -42,10 +42,9 @@ StmGen4GPageTable ( UINT32
EFIAPI
SmmStmExceptionHandler (
- IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
+ IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
);
-
/**
Get STM state.
@@ -73,8 +72,8 @@ GetMonitorState ( EFI_STATUS
EFIAPI
LoadMonitor (
- IN EFI_PHYSICAL_ADDRESS StmImage,
- IN UINTN StmImageSize
+ IN EFI_PHYSICAL_ADDRESS StmImage,
+ IN UINTN StmImageSize
);
/**
@@ -94,7 +93,7 @@ EFI_STATUS EFIAPI
AddPiResource (
IN STM_RSC *ResourceList,
- IN UINT32 NumEntries OPTIONAL
+ IN UINT32 NumEntries OPTIONAL
);
/**
@@ -113,8 +112,8 @@ AddPiResource ( EFI_STATUS
EFIAPI
DeletePiResource (
- IN STM_RSC *ResourceList,
- IN UINT32 NumEntries OPTIONAL
+ IN STM_RSC *ResourceList,
+ IN UINT32 NumEntries OPTIONAL
);
/**
@@ -133,8 +132,8 @@ DeletePiResource ( EFI_STATUS
EFIAPI
GetPiResource (
- OUT STM_RSC *ResourceList,
- IN OUT UINT32 *ResourceSize
+ OUT STM_RSC *ResourceList,
+ IN OUT UINT32 *ResourceSize
);
/**
@@ -153,7 +152,7 @@ StmSmmConfigurationTableInit ( **/
VOID
NotifyStmResourceChange (
- IN VOID *StmResource
+ IN VOID *StmResource
);
/**
@@ -174,6 +173,6 @@ GetStmResource ( VOID
EFIAPI
SmmCpuFeaturesLibStmSmiEntryFixupAddress (
- );
+ );
#endif
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c index c8a3f58e0c..00ab9bd0cd 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c @@ -14,9 +14,9 @@ ///
/// Page Table Entry
///
-#define IA32_PG_P BIT0
-#define IA32_PG_RW BIT1
-#define IA32_PG_PS BIT7
+#define IA32_PG_P BIT0
+#define IA32_PG_RW BIT1
+#define IA32_PG_PS BIT7
/**
@@ -28,22 +28,22 @@ **/
VOID
StmGen4GPageTable (
- IN UINTN PageTableBase
+ IN UINTN PageTableBase
)
{
- UINTN Index;
- UINTN SubIndex;
- UINT64 *Pde;
- UINT64 *Pte;
- UINT64 *Pml4;
+ UINTN Index;
+ UINTN SubIndex;
+ UINT64 *Pde;
+ UINT64 *Pte;
+ UINT64 *Pml4;
- Pml4 = (UINT64*)(UINTN)PageTableBase;
+ Pml4 = (UINT64 *)(UINTN)PageTableBase;
PageTableBase += SIZE_4KB;
- *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P;
+ *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P;
- Pde = (UINT64*)(UINTN)PageTableBase;
+ Pde = (UINT64 *)(UINTN)PageTableBase;
PageTableBase += SIZE_4KB;
- Pte = (UINT64 *)(UINTN)PageTableBase;
+ Pte = (UINT64 *)(UINTN)PageTableBase;
for (Index = 0; Index < 4; Index++) {
*Pde = PageTableBase | IA32_PG_RW | IA32_PG_P;
@@ -75,7 +75,7 @@ StmGen4GPageTable ( UINT32
EFIAPI
SmmStmExceptionHandler (
- IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
+ IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
)
{
// TBD - SmmStmExceptionHandler, record information
diff --git a/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c b/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c index 6c2010dc0a..085a03e52a 100644 --- a/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c +++ b/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c @@ -69,7 +69,7 @@ ClearTopLevelSmiStatus ( EFI_STATUS
EFIAPI
PlatformSmmBspElection (
- OUT BOOLEAN *IsBsp
+ OUT BOOLEAN *IsBsp
)
{
return EFI_NOT_READY;
@@ -92,10 +92,10 @@ PlatformSmmBspElection ( EFI_STATUS
EFIAPI
GetPlatformPageTableAttribute (
- IN UINT64 Address,
- IN OUT SMM_PAGE_SIZE_TYPE *PageSize,
- IN OUT UINTN *NumOfPages,
- IN OUT UINTN *PageAttribute
+ IN UINT64 Address,
+ IN OUT SMM_PAGE_SIZE_TYPE *PageSize,
+ IN OUT UINTN *NumOfPages,
+ IN OUT UINTN *PageAttribute
)
{
return EFI_UNSUPPORTED;
diff --git a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c index 89b065cb3f..d661d85974 100644 --- a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c +++ b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c @@ -35,15 +35,15 @@ UINT64
EFIAPI
VmgExit (
- IN OUT GHCB *Ghcb,
- IN UINT64 ExitCode,
- IN UINT64 ExitInfo1,
- IN UINT64 ExitInfo2
+ IN OUT GHCB *Ghcb,
+ IN UINT64 ExitCode,
+ IN UINT64 ExitInfo1,
+ IN UINT64 ExitInfo2
)
{
GHCB_EVENT_INJECTION Event;
- Event.Uint64 = 0;
+ Event.Uint64 = 0;
Event.Elements.Vector = GP_EXCEPTION;
Event.Elements.Type = GHCB_EVENT_INJECTION_TYPE_EXCEPTION;
Event.Elements.Valid = 1;
@@ -65,8 +65,8 @@ VmgExit ( VOID
EFIAPI
VmgInit (
- IN OUT GHCB *Ghcb,
- IN OUT BOOLEAN *InterruptState
+ IN OUT GHCB *Ghcb,
+ IN OUT BOOLEAN *InterruptState
)
{
}
@@ -85,8 +85,8 @@ VmgInit ( VOID
EFIAPI
VmgDone (
- IN OUT GHCB *Ghcb,
- IN BOOLEAN InterruptState
+ IN OUT GHCB *Ghcb,
+ IN BOOLEAN InterruptState
)
{
}
@@ -104,8 +104,8 @@ VmgDone ( VOID
EFIAPI
VmgSetOffsetValid (
- IN OUT GHCB *Ghcb,
- IN GHCB_REGISTER Offset
+ IN OUT GHCB *Ghcb,
+ IN GHCB_REGISTER Offset
)
{
}
@@ -126,8 +126,8 @@ VmgSetOffsetValid ( BOOLEAN
EFIAPI
VmgIsOffsetValid (
- IN GHCB *Ghcb,
- IN GHCB_REGISTER Offset
+ IN GHCB *Ghcb,
+ IN GHCB_REGISTER Offset
)
{
return FALSE;
|