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* ArmPkg/ArmLib: Fix AARCH64 page table entry filling overrunGarrett Kirkendall2014-01-241-0/+2
| | | | | | | | | | | | | | | | | | | | Update the LastBlockEntry return value when allocating a new page table block and the parent page table entry is not valid. Discovered when producing page table entries for a memory region that spans multiple page table entries of a parent page table block. Not very memory space efficient because the rest of the code could calculate a required page level that is deeper than some blocks of the memory region might require. Case that found the problem: MemoryRegion->VirtualBase = 0 MemoryRegion->Length = 0x7F000000 This fix will create an un-needed level of page table for address range 0 -> 0x40000000 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15177 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CompilerIntrinsicsLib: Make __aeabi_memcpy the same as memcpyOlivier Martin2014-01-152-22/+21
| | | | | | | | | | | | | | | | | This code also removed some redundant instructions. __aeabi_memcpy doesn't require preservation of r0 (as memcpy does), which could save a push, but the code has been left to keep things consistent. The reason __aeabi_memcpy has been added to the .S file is so it will be available to toolchains that use the GCC assembler but the full ARM EABI (i.e. current LLVM) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15124 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmPkg.dec: Redefined PcdSystemMemory(Base|Size) as UINT64Olivier Martin2014-01-104-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | The System Memory region might be out of the 32-bit memory space. This change has been validated on the FVP AArch64 model using 4GB of DRAM at 0x8_0000_0000: - # System Memory (2GB) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000 + # System Memory (4GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000 EFI Shell and Linux kernel boot successfully. Note: This change has not been validated on AArch32. I expect some early assembly code to not work. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Removed 'inline' keywordOlivier Martin2013-12-101-1/+1
| | | | | | | | | | 'inline' keyword is not supported by the C89 (version used by EDK2). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14957 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/AArch64Mmu.h: Fix 'Shift is >= width of type'Olivier Martin2013-12-101-6/+6
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14956 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmDisassemblerLib: Fixed logical/bitwise operator confusionOlivier Martin2013-12-101-6/+6
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14955 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmMpCoreInfo.h: Fixed macro definitionOlivier Martin2013-12-101-1/+1
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14954 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Fixed the alignment of the relocated Device TreeOlivier Martin2013-11-281-1/+1
| | | | | | | | | | | | | When the Device Tree was loaded above the 32bit address space the operation: *RelocatedFdt = ALIGN ((UINT64)*RelocatedFdt, (UINT32)FdtAlignment); was returning an incorrect address. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14915 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/DebugPeCoffExtraActionLib: Fixed the printing of the location of the ↵Olivier Martin2013-11-281-3/+3
| | | | | | | | | | | | | EFI modules When loaded above the 32-bit address space the address requires more than 8 characters. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14913 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Removed LR adjustement for SVC callOlivier Martin2013-11-282-2/+0
| | | | | | | | | | | | The Link Register (LR) does not need adjustement when receiving a Supervisor Call (SVC). Note: SVC might be generated by debuggers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14911 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Move definition of ArmIsArchTimerImplemented / ArmReadIdPfrN to ArmLibOlivier Martin2013-11-284-33/+21
| | | | | | | | | | | These functions are not chipset specific. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14908 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/ArmVExpressPkg: Removed unused PCDs declaration from INF fileOlivier Martin2013-11-281-4/+1
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14907 6f19259b-4bc3-4df7-8a09-765794883524
* ARM Packages: Renamed PL390Gic driver into ArmGic driverOlivier Martin2013-10-2910-16/+16
| | | | | | | | | | | | The aim is to make this driver follows the ARM GIC specifications and be implementation independent. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14810 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/PL390Gic: Fixed setting of the Interrupt Processor Targets Registers ↵Olivier Martin2013-10-241-6/+6
| | | | | | | | | | | | | | when Uniprocessor When running on a uniprocessor implementation, the ICDIPTRn registers are RAZ (Read as Zero). So the previous assertion was not correct. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14798 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/Include/Chipset: Fix translation table address calculations for AARCH64Garrett Kirkendall2013-10-151-3/+3
| | | | | | | | | | | | | | TT_ADDRESS_* macros were not casting immediate values to UINTN. This causes shift operations to be off by 32-bits when calculating addresses above 4GB. Any address above 4GB was being improperly calculated. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14777 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Fixed confusion in AArch64 Table descriptor typesOlivier Martin2013-10-141-1/+1
| | | | | | | | | | | | Table Descriptor and Level-3 Block entry descriptors have the same translation table type value (ie: 0x3). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14771 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Revert change 'Fixed field shifting in CLIDR_EL1 (AArch64)'Olivier Martin2013-09-231-2/+4
| | | | | | | | | | | | The shift by 1 on the left was expected. It eases the access to CSSELR and set/way operations where the cache level field is at the BIT1 position. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14704 6f19259b-4bc3-4df7-8a09-765794883524
* SemihostFs: Fix check for read-only file or file-openOlivier Martin2013-09-231-2/+4
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14703 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Fixed the condition that checks if the level-1 descriptor ↵Olivier Martin2013-09-231-1/+1
| | | | | | | | | | | points to a level-2 page table Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14700 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Fixed field shifting in CLIDR_EL1 (AArch64)Olivier Martin2013-09-161-2/+2
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14677 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Fixed attribute setting in GetNextEntryAttribute()Olivier Martin2013-09-161-1/+1
| | | | | | | | | | | The wrong attribute was used to set the region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14676 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Exception Handling SP AdjustEugene Cohen2013-09-102-2/+2
| | | | | | | | | | | | | | The exception handling support code appears to adjust the stack pointer in the wrong direction. It decrements the stack pointer by 0x60, but this should be an increment (add) for the downward-growing stack. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14646 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuPei: Remove unused functions from the driverRoy Franz2013-09-031-106/+0
| | | | | | | | | | | | | | | | The ConfigureMmu() function is unused - the only call to it is commented out, and the functionality has been moved to InitMmu() in MemoryInitPeiLib.c. This change also removes the unused definitions from the file. Change-Id: Ice795bfee25c403142d0c078533f8a46d04f82e9 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Roy Franz <roy.franz@linaro.org> Signed-off-by:: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14621 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmDmaLib: Fixed the calculation of the Base Address of the BufferOlivier Martin2013-09-021-1/+1
| | | | | | | | | | | | | | | | | | The former calculation 'ALIGN_VALUE(*DeviceAddress - BASE_4KB - 1,BASE_4KB)' did not return the lowest aligned address. Example: *DeviceAddress = 0xB000C001; *DeviceAddress - BASE_4KB - 1 = 0xB000B000; Aligned value = 0xB000B000 + ((0x1000 - 0xB000B000)) & 0xFFF) = 0xB000B000 ... while we where expected 0xB000C000. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14618 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Fixed calculation of the Page Table Index (Level 2 Descriptor)Olivier Martin2013-09-021-2/+2
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14617 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Change comment to match code for setting of V bit in SCTLR ↵Roy Franz2013-09-022-2/+2
| | | | | | | | | | | | register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Roy Franz <roy.franz@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14616 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmGicLib.h: Added macro to retrieve the information from the ICCIDROlivier Martin2013-08-211-8/+13
| | | | | | | | | | | | These macros are helper functions to get the information from the GIC CPU Interface Identification register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14582 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPlatformPkg/Sec: Remove SCR and CPTR initialization from SetupExceptionLevel3Olivier Martin2013-08-211-18/+40
| | | | | | | | | | | This is already taken care by Sec when PcdTrustzoneSupport = TRUE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14580 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Added support to not set a memory region with the same attributeOlivier Martin2013-08-194-4/+364
| | | | | | | | | | | | Changing the attribute implies some cache management (clean & invalidate). Preventing the cache management should improve the performance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14568 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Added ConvertSectionAttributesToPageAttributes()Olivier Martin2013-08-193-12/+26
| | | | | | | | | | | This helper function converts the section attributes into their page equivalents. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14567 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Mmu.h: Added masks to extract attributes from Section and Page ↵Olivier Martin2013-08-191-1/+8
| | | | | | | | | | | entries Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14566 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Introduced TT_LAST_BLOCK_ADDRESS()Olivier Martin2013-08-192-3/+6
| | | | | | | | | | | This macro return the address of the last entry of a translation table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14565 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Fixed AArch64 MMU/GCD synchronizationOlivier Martin2013-08-192-8/+17
| | | | | | | | | | | | - Fix the length used to set the GCD Memory Space attribute - Print a warning message if the given length of a memory space region is not 4KB-aligned Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14562 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: AArch64: Fix wrong comparison of exception typeGirish K S2013-08-191-3/+3
| | | | | | | | | | | | | | | | | | | During the interrupt registration comparison is made against max value of exception types for ARMV7, but in the common handling function the check is made against max value of exceptions types for ARMV8. This can lead to undefined behaviour during registration of interrupts. This patch modifies the registration function to handle only AArch64 exceptions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Girish K S <ks.giri@samsung.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14561 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmV7Mmu.h: Fixed XN bit conversion from section to small/large page ↵Olivier Martin2013-08-061-2/+2
| | | | | | | | | | | format Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14523 6f19259b-4bc3-4df7-8a09-765794883524
* ARM: Remove NSACR from the common codeOlivier Martin2013-08-069-58/+54
| | | | | | | | | | | NSACR (Non-Secure Access Control Register) is AArch32 specific. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib: Fixed TBLs invalidation in EL1Olivier Martin2013-07-262-4/+4
| | | | | | | | | | | | | | 'tlb alle1' was used to invalidate the TLBs in EL1. Expect this instruction can only be invoked from EL2. The correct instruction to invalidate TLBs in EL1 is 'tlbi vmalle1' - it invalidates the TLBs of the current VMID. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14509 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/Library: AArch64 MMU EL1 supportOlivier Martin2013-07-261-4/+27
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14508 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg,ArmPlatformPkg: Free memory allocated by Get.*SpaceMap()Olivier Martin2013-07-262-7/+16
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14507 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib/AArch64: Use the appropriate macros and update commentsOlivier Martin2013-07-261-6/+8
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14506 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Update the AArch64 Image File Machine Type to match the PE/COFF specOlivier Martin2013-07-241-1/+1
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14502 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: AArch64 MPCore Linux 'spin-table' boot cache fixHarry Liebel2013-07-241-3/+2
| | | | | | | | | | | Clean data cache after initialising mailboxes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14501 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/ArmLib/AArch64: Fixed the calculation of the last entry in the ↵Olivier Martin2013-07-241-3/+5
| | | | | | | | | | Translation Table Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14500 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Added AArch64 support (missing files)Harry Liebel2013-07-181-0/+202
| | | | | | | | | | | | Some missing files from the initial AArch64 commit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14488 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/BdsLib: Added Aarch64 support for booting LinuxHarry Liebel2013-07-185-1/+430
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14487 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Added Aarch64 supportHarry Liebel2013-07-1858-43/+4786
| | | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14486 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/CpuDxe: Moved memory mapping functions that are not architecture ↵Olivier Martin2013-07-184-246/+276
| | | | | | | | | | | specific to 'CpuMmuCommon.c' Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14482 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg: Removed the non-used PCD PcdGicPrimaryCoreIdOlivier Martin2013-07-173-12/+0
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14480 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/PL390Gic: Populate the GIC Distributor Target Register with the GIC ↵Olivier Martin2013-07-171-5/+20
| | | | | | | | | | | | | | | CPU ID retrieved from the GIC The GIC CPU Id (the GIC CPU interface the CPU is connected to) can be retrieved by reading the first registers of the GIC CPU Target Registers. The first GIC Distributor Target registers correspond to the SGIs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14479 6f19259b-4bc3-4df7-8a09-765794883524
* ArmPkg/UncachedMemoryAllocationLib: Removed unused header (Protocol/Cpu.h)Olivier Martin2013-07-161-2/+0
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14469 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-29 07:25:40 +0000