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* Fix bug on SRIOV ReservedBusNum when ARI enable.Foster Nong2022-10-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a device which support both features SR-IOV/ARI has multi functions, which maybe support 8-255. After enable ARI forwarding in the root port and ARI Capable Hierarchy in the SR-IOV PF0. The device will support and expose multi functions(0-255) with ARI ID routing. In next device loop in below for() code, actually it still be in the same SR-IOV device, and just some PF which is over 8 or higher one(n*8), PciAllocateBusNumber() will allocate bus number(ReservedBusNum - TempReservedBusNum)) for this PF. if reset TempReservedBusNum as 0 in this case,it will allocate wrong bus number for this PF because TempReservedBusNum should be total previous PF's reserved bus numbers. code: for (Device = 0; Device <= PCI_MAX_DEVICE; Device++) { TempReservedBusNum = 0; for (Func = 0; Func <= PCI_MAX_FUNC; Func++) { // // Check to see whether a pci device is present // Status = PciDevicePresent ( PciRootBridgeIo, &Pci, StartBusNumber, Device, Func ); ... Status = PciAllocateBusNumber (PciDevice, *SubBusNumber, (UINT8)(PciDevice->ReservedBusNum - TempReservedBusNum), SubBusNumber); The solution is add a new flag IsAriEnabled to help handle this case. if ARI is enabled, then TempReservedBusNum will not be reset again during all functions(1-255) scan with checking flag IsAriEnabled. Signed-off-by: Foster Nong <foster.nong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg: Apply uncrustify changesMichael Kubacki2021-12-071-130/+127
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the MdeModulePkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
* MdeModulePkg/Bus/Pci/PciBusDxe: Support PCIe Resizable BAR CapabilityLuo, Heng2021-01-041-1/+3
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=313 Add PcdPcieResizableBarSupport to enable/disable PCIe Resizable BAR Capability fearture. Program the Resizable BAR Register if the device suports PCIe Resizable BAR Capability and PcdPcieResizableBarSupport is TRUE. Cc: Ray Ni <ray.ni@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Signed-off-by: Heng Luo <heng.luo@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg/Pci: Add DeviceSecurity support.Jiewen Yao2019-11-111-0/+1
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2303 Whenever a PCI device is discovered, PCI bus calls the EDKII_DEVICE_SECURITY_PROTOCOL to authenticate it. If the function returns success, the PCI bus allocates the resource and installs the PCI_IO for the device. If the function returns fail, the PCI bus skips the device. It is similar to EFI_SECURITY_ARCH_PROTOCOL, which is used to verify an EFI image. Cc: Jian J Wang <jian.j.wang@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Yun Lou <yun.lou@intel.com> Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* MdeModulePkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-091-7/+1
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
* MdeModulePkg/PciBus: Change PCI_IO_DEVICE.RomSize to UINT32 typeRay Ni2019-02-141-2/+2
| | | | | | | | | Per PCI Spec, the option ROM BAR is 32bit so the maximum option ROM size can be hold by UINT32 type. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg/PciBus: Shadow option ROM after BARs are programmedRuiyu Ni2018-12-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1376 Today's implementation reuses the 32bit MMIO resource requested by all PCI devices MMIO BARs when shadowing the option ROM. Take a simple example, a system has only one PCI device. It requires 8MB 32bit MMIO and contains a 4MB option ROM. Today's implementation only requests 8MB (max of 4M and 8M) 32bit MMIO from PciHostBridgeResourceAllocation protocol. Let's assume the MMIO range [3GB, 3GB+8MB) is allocated. The 3GB base address is firstly programmed to the option ROM BAR for option ROM shadow. Then the option ROM decoding is turned off and 3GB base address is programmed to the 32bit MMIO BAR. It doesn't cause issues when the device doesn't request too much MMIO. But when the device contains a 64bit MMIO BAR which requests 4GB MMIO and a 4MB option ROM. Let's assume [3GB, 3GB+8MB) 32bit MMIO range is allocated for the option ROM. When the option ROM is being shadowed, 64bit MMIO BAR is programmed to value 0, which means [0, 4GB) MMIO is given to the 64bit BAR. The range overlaps with the option ROM range which may cause the device malfunction (e.g.: option ROM cannot be read out) when the device has two separate decoders: one for MMIO BAR, the other for option ROM. The patch requests dedicated MEM32 resource for Option ROMs and moves the Option ROM shadow logic after all MMIO BARs are programmed. The MMIO BAR setting to 0 when shadowing Option ROM is also skipped because the MMIO BAR already contains the correct value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
* MdeModulePkg: Remove redundant library classes and GUIDsshenglei2018-08-201-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some redundant library classes and GUIDs have been removed in inf, .c and .h files. https://bugzilla.tianocore.org/show_bug.cgi?id=1044 https://bugzilla.tianocore.org/show_bug.cgi?id=1045 https://bugzilla.tianocore.org/show_bug.cgi?id=1047 https://bugzilla.tianocore.org/show_bug.cgi?id=1049 https://bugzilla.tianocore.org/show_bug.cgi?id=1051 https://bugzilla.tianocore.org/show_bug.cgi?id=1052 https://bugzilla.tianocore.org/show_bug.cgi?id=1053 https://bugzilla.tianocore.org/show_bug.cgi?id=1054 https://bugzilla.tianocore.org/show_bug.cgi?id=1055 https://bugzilla.tianocore.org/show_bug.cgi?id=1056 https://bugzilla.tianocore.org/show_bug.cgi?id=1017 https://bugzilla.tianocore.org/show_bug.cgi?id=1035 https://bugzilla.tianocore.org/show_bug.cgi?id=1033 https://bugzilla.tianocore.org/show_bug.cgi?id=1012 https://bugzilla.tianocore.org/show_bug.cgi?id=1011 https://bugzilla.tianocore.org/show_bug.cgi?id=1062 v2: 1. Correct copyright year. 2. Fix alignment issue in AcpiPlatformDxe.inf. 3. Add DevicePathLib which is removed before in I2cHostDxe.inf. 4. Update NvmExpressPei.inf, NvmExpressPei.h, IScsiDxe.inf, IScsiDxe.inf, IScsiDxe.h, DxeMain.inf, DxeMain.h, PiSmmCore.inf and PiSmmCore.h for https://bugzilla.tianocore.org/show_bug.cgi?id=1062. v3: 1. Add https://bugzilla.tianocore.org/show_bug.cgi?id=1062 to the link list. 2. Remove DevicePathLib from I2cHostDxe.inf. 3. Update NvmExpressPei.inf, NvmExpressPei.h, UfsPciHcDxe.inf, UfsPciHcDxe.h, I2cHostDxe.inf, AtaBusDxe.inf, IScsiDxe.inf, IScsiDxe.h, DxeMain.inf, DxeMain.h, PiSmmCore.inf and PiSmmCore.h for https://bugzilla.tianocore.org/show_bug.cgi?id=1062. (Forget to add UfsPciHcDxe.inf, UfsPciHcDxe.h, AtaBusDxe.inf, and I2cHostDxe.inf previously.) Cc: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shenglei <shenglei.zhang@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/PciBus: Revert "disable all BME when entering RT"Ruiyu Ni2017-11-221-2/+0
| | | | | | | | | | | | | This reverts commit 050763db0730a0bb46235cec87e3716632dc532c. "MdeModulePkg/PciBus: Disable BME of all devices when entering RT" We met some compatibility issues when doing Windows S4 resume. Reverting the BME disabling patches to fix the S4 resume issue. Signed-off-by: Ruiyu Ni <Ruiyu.ni@intel.com> Signed-off-by: Michael Turner <michael.turner@microsoft.com> Cc: Michael D Kinney <Michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* MdeModulePkg/PciBus: Disable BME of all devices when entering RTRuiyu Ni2017-11-071-0/+2
| | | | | | | | | | | | | | | The patch ensures all DMA transactions are blocked after ExitBootService. If a platform enables IOMMU before and needs disable IOMMU after ExitBootService, the IOMMU should be disabled after PCI bus driver disables BME. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Turner <michael.turner@microsoft.com> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <vanjeff_919@hotmail.com>
* MdeModulePkg/PciBus: Refine EFI_PCI_ROM_IMAGE_MAPPINGRuiyu Ni2017-10-311-6/+1
| | | | | | | | | | | | | The patch doesn't impact real functionality. It only renames EFI_PCI_ROM_IMAGE_MAPPING to PCI_ROM_IMAGE, and changes prototype of PciRomAddImageMapping so that no explicit type cast is needed when calling this function. It also removes unused field RomBase from PCI_IO_DEVICE structure. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/PciBus: Add IOMMU support.Jiewen Yao2017-05-171-0/+1
| | | | | | | | | | | | | | | | | | | | If IOMMU protocol is installed, PciBus need call IOMMU to set access attribute for the PCI device in Map/Ummap. Only after the access attribute is set, the PCI device can access the DMA memory. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Leo Duran <leo.duran@amd.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Previous patch Tested-by: Brijesh Singh <brijesh.singh@amd.com> Previous patch Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Leo Duran <leo.duran@amd.com>
* MdeModulePkg/Bus: Fix typos in commentsGary Lin2016-10-271-7/+7
| | | | | | | | | | | | | | | | | | | | - TURE -> TRUE - stoping -> stopping - doule -> double - Peroidic -> Periodic - stardard -> standard - a a -> a - reseting -> resetting - excute -> execute - connectted -> connected - Sumbit -> Submit Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gary Lin <glin@suse.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* MdeModulePkg/PciBus: do not improperly degrade resourceRuiyu Ni2016-05-231-1/+2
| | | | | | | | | | | | | | | | | PciBus driver originally always degrade (64->32) the MMIO resource for PCI BAR when the PCI device contains option ROM. But the degrade causes the PCI device can only use resource below 4GB which makes the resource allocation fails when the PCI device wants very big MMIO. The patch follows the PI spec (ECR 1529) to honor the granularity setting for PCI BAR from IncompatiblePciDeviceSupport so that even for PCI device which contains option ROM, the degrade doesn't happen if IncompatiblePciDeviceSupport returns 64 as granularity. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg/PciBus: Use shorter global variable nameRuiyu Ni2016-05-231-1/+1
| | | | | | | | | | Remove "Efi" from gEfiIncompatiblePciDeviceSupport to shorten the global variable name. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* MdeModulePkg/PciBus: Remove unused fields in PCI_BARRuiyu Ni2016-05-231-3/+1
| | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* Dispatch the UEFI option rom returned from PciPlatform/PciOverride protocol.Ruiyu Ni2015-01-201-6/+1
| | | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Chao B Zhang <chao.b.zhang@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16625 6f19259b-4bc3-4df7-8a09-765794883524
* Update all the code to consume the ConvertDevicePathToText, ↵Ruiyu Ni2013-07-261-2/+1
| | | | | | | | | | | | | | ConvertDevicePathNodeToText, ConvertTextToDevicePath and ConvertTextToDeviceNode APIs in DevicePathLib. Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Elvin Li <elvin.li@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14505 6f19259b-4bc3-4df7-8a09-765794883524
* Cache the state whether the ROM image contains EFI Option ROM when loading ↵niruiyu2012-09-071-1/+6
| | | | | | | | | the ROM content from PCI device to memory to avoid re-parsing the ROM image to check the EFI Option ROM. Signed-off-by: Ruiyu Ni<ruiyu.ni@intel.com> Reviewed-by: Elvin Li<elvin.li@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13707 6f19259b-4bc3-4df7-8a09-765794883524
* MdeModulePkg PciBusDxe: The PCI Bus Driver is updated to support multiple ↵rsun32011-10-281-0/+5
| | | | | | | | | | PCI bus ranges for a PCI root bridge. Signed-off-by: rsun3 Reviewed-by: vanjeff git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12600 6f19259b-4bc3-4df7-8a09-765794883524
* Print resource allocation/bar programming when PciBus driver does PCI BUS ↵niruiyu2011-08-041-1/+8
| | | | | | | | | enumeration. Signed-off-by: niruiyu Reviewed-by: rsun3 git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12087 6f19259b-4bc3-4df7-8a09-765794883524
* Clean ISA_IO/ISA_IO_16 and VGA_IO/VGA_IO_16 attribute usage in PCI bus ↵rsun32010-12-281-2/+2
| | | | | | | | | | | | | | driver/PCI host bridge drivers/LPC/VGA device drivers. 1. Fix the incorrect definition of EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 (does not conform to the UEFI spec) in PciIo.h. 2. Add missing definitions of ISA and VGA IO attributes in PCI Root Bridge IO protocol. 3. Improve the algorithm in the PCI bus driver to get PCI platform policy from PCI Platform Protocol and PCI Override Protocol. 4. Update the PCI bus driver to use the PCI platform policy to determine the supported attributes that are returned by the EFI_PCI_IO_PROTOCOL.Attributes() function. This is required by the PI spec. 5. Add a backward compatibility workaround for PCI VGA drivers in Option ROM, which typically sets VGA_IO without checking supported attributes. 6. Update the PCI host bridge driver in PcAtChipsetPkg to report VGA_IO_16 and ISA_IO_16 instead of VGA_IO/ISA_IO attributes. Modern chipsets don’t have hardware capability to control 10-bit or 16-bit decoding for ISA/VGA aliases. 7. Update LPC/VGA device drivers to check supported attributes of VGA_IO/VGA_IO_16 or ISA_IO/ISA_IO_16. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11204 6f19259b-4bc3-4df7-8a09-765794883524
* Update the PCI bus driver to correctly set the ↵rsun32010-12-141-0/+5
| | | | | | EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM attribute of PCI IO. Per UEFI spec, this attribute is used to determine if the ROM image is from the ROM BAR or from a platform specific location. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11159 6f19259b-4bc3-4df7-8a09-765794883524
* Fix bugs in the PCI bus driver to support SR-IOV.rsun32010-07-131-2/+2
| | | | | | | | | | 1. Expand the type of Offset in the _PCI_BAR structure from UINT8 to UINT16, because a VF BAR’s offset may be >= 0x100; 2. Enable ARI Capable Hierarchy for SR-IOV devices at earlier time because FirstVFOffset and VFStride of a SR-IOV device may change after its ARI Capable Hierarchy is set; 3. Change type of PcdSrIovSupport, PcdAriSupport, PcdMrIovSupport from FeatureFlag to [FixAtBuild, PcdDynamics], which allows SR-IOV/MR-IOV/ARI feature can be turn on/off dynamically, typically via a setup option. 4. Change PCI bus scan algorithm in PciScanBus() to prevent the case where some ARI extended functions may be skipped in the scan loop. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10644 6f19259b-4bc3-4df7-8a09-765794883524
* Update the copyright notice formathhtian2010-04-241-2/+2
| | | | git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10420 6f19259b-4bc3-4df7-8a09-765794883524
* Update PCI bus driver to support non-standard PCI to PCI bridge I/O window ↵rsun32009-12-241-0/+6
| | | | | | alignment, such as 2K/1K/512 byte. Feature PCD PcdPciBridgeIoAlignmentProbe is introduced to turn on/off this feature. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9598 6f19259b-4bc3-4df7-8a09-765794883524
* 1. Impl PI 1.2 PCI part. Major changes include:davidhuang2009-10-201-0/+382
a. Update PciBusDxe module, and move it from IntelFrameworkModulePkg to MdeModulePkg b. Move IncompatiblePciDeviceSupportDxe module from IntelFrameworkModulePkg to MdeModulePkg c. Update the related consumes in inf/dsc/fdf git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9347 6f19259b-4bc3-4df7-8a09-765794883524
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