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* UefiCpuPkg: Remove FIT based microcode shadow logic from MpInitLib.Siyuan Fu2020-02-141-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c7c964b and dd01704 add header file for FIT table and update MpInitLib to support FIT based microcode shadow operation. There are comments that FIT is Intel specific specification instead of industry standard, which should not be placed in EDK2 MdePkg and UefiCpuPkg. So this patch adds a platform PPI for the microcode shadow logic, and remove the FIT related code from EDK2. The FIT based microcode shadow support will be implemented as a new platform PEIM in IntelSiliconPkg in edk2-platforms. This patch doesn't provide a DXE version shadow microcode protocol, a platform which only uses DxeMpInitLib instance only supports PCD based microcode shadowing. A detailed design doc can be found here: https://edk2.groups.io/g/devel/files/Designs/2020/0214/Support%20 the%202nd%20Microcode%20FV%20Flash%20Region.pdf TEST: Tested on FIT enabled platform. BZ: https://tianocore.acgmultimedia.com/show_bug.cgi?id=2449 Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Siyuan Fu <siyuan.fu@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuFeature: Introduce First to indicate 1st unit.Ray Ni2020-02-141-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1584 The flow of CPU feature initialization logic is: 1. BSP calls GetConfigDataFunc() for each thread/AP; 2. Each thread/AP calls SupportFunc() to detect its own capability; 3. BSP calls InitializeFunc() for each thread/AP. There is a design gap in step #3. For a package scope feature that only requires one thread of each package does the initialization operation, what InitializeFunc() currently does is to do the initialization operation only CPU physical location Core# is 0. But in certain platform, Core#0 might be disabled in hardware level which results the certain package scope feature isn't initialized at all. The patch adds a new field First to indicate the CPU's location in its parent scope. First.Package is set for all APs/threads under first package; First.Core is set for all APs/threads under first core of each package; First.Thread is set for the AP/thread of each core. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Delete CPU_FEATURE_[BEFORE|AFTER]Ray Ni2020-02-141-12/+3
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1366 Commit b3c71b472dff2c02f0cc38d7a1959cfb2ba8420d supported MSR setting in different scopes. It added below macro: CPU_FEATURE_THREAD_BEFORE CPU_FEATURE_THREAD_AFTER CPU_FEATURE_CORE_BEFORE CPU_FEATURE_CORE_AFTER CPU_FEATURE_PACKAGE_BEFORE CPU_FEATURE_PACKAGE_AFTER And it re-interpreted CPU_FEATURE_BEFORE as CPU_FEATURE_THREAD_BEFORE and CPU_FEATURE_AFTER as CPU_FEATURE_THREAD_AFTER. This patch retires CPU_FEATURE_BEFORE and CPU_FEATURE_AFTER completely. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/Smm: Fix various typosAntoine Coeur2020-02-101-2/+2
| | | | | | | | | | | | | | Fix various typos in comments and documentation. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Antoine Coeur <coeur@gmx.fr> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <20200207010831.9046-79-philmd@redhat.com>
* UefiCpuPkg: Add definitions for EDKII microcode patch HOBHao A Wu2020-01-021-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2430 This commit will add the definitions for EDKII microcode patch HOB. The intention of adding this HOB is to provide a scheme to store the below information: A. The base address and size of the microcode patches that are being loaded (from flash) into memory; B. The information of detected microcode patch for each processor within the system. The producer of the HOB will be the UefiCpuPkg/MpInitLib (where the load, detect and apply of the microcode happen). The consumer of the HOB can be modules that want to detect/apply the microcode patch by themselves again later during the boot flow. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Siyuan Fu <siyuan.fu@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/RegisterCpuFeature: Remove CPU_FEATURE_XD macroRay Ni2019-11-131-1/+1
| | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2329 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros.Dong, Eric2019-08-212-1/+93
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 Add below new micros which test the current value before write the new value. Only write new value when current value not same as new value. CPU_REGISTER_TABLE_TEST_THEN_WRITE32 CPU_REGISTER_TABLE_TEST_THEN_WRITE64 CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD Also add below API: CpuRegisterTableTestThenWrite Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Cc: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg: Update code to include register definitions from MdePkgNi, Ray2019-08-093-4/+4
| | | | | | | Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg|MdePkg: Move Register/ folder to MdePkg/Include/Ni, Ray2019-08-0933-53504/+19
| | | | | | | | | | | | | | | | | | | | | | The patch moves all files under UefiCpuPkg/Include/Register/ to MdePkg/Include/Register using following detailed approaches: 1. Move UefiCpuPkg/Include/Register/Amd/ to MdePkg/Include/Register/Amd folder. 2. Move remaining in UefiCpuPkg/Include/Register/ to MdePkg/Include/Register/Intel folder. 3. Create wrapper header files under UefiCpuPkg/Include/Register/ to include the accordingly files in MdePkg/Include/Register/Intel. This is to avoid build break because code in other repos like edk2-platform includes the file from UefiCpuPkg. The wrapper header files will be removed after all consumers code is updated. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* MdePkg/Cpuid.h: Move Cpuid.h from UefiCpuPkg to MdePkgNi, Ray2019-08-091-3981/+2
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 MdeModulePkg/DxeIpl needs to get CPUID output for CPU 5-level paging capability detection. In order to use the macros/structures defined in UefiCpuPkg/Include/Register/Cpuid.h, the patch adds Intel/Cpuid.h to MdePkg/Include/Register/ directory and updates Cpuid.h in UefiCpuPkg to include the new one in MdePkg. Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Add new EDKII_PEI_MP_SERVICES2_PPIEric Dong2019-07-291-0/+279
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 Add definition for new EDKII_PEI_MP_SERVICES2_PPI. It includes all APIs existed in EFI_PEI_MP_SERVICES_PPI and add new API EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/MpInitLib.h: Add MpInitLibStartupAllCPUs API.Eric Dong2019-07-291-1/+35
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 Add new MpInitLibStartupAllCPUs API uses to start all processors at the same time. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg RegisterCpuFeaturesLib.h: Fix typo 'STRICK' to 'STRIKE'Star Zeng2019-06-131-1/+1
| | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1642 This patch fixes typo in CPU_FEATURE_THREE_STRICK_COUNTER. CPU_FEATURE_THREE_STRICK_COUNTER -> CPU_FEATURE_THREE_STRIKE_COUNTER Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0949-343/+49
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/Cpuid.h: Update CPUID.7H.ECX structure for 5-level pagingRay Ni2019-04-091-2/+5
| | | | | | | | Reserved6 is changed to Reserved7 because the bit width is changed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/LocalApicLib: Add GetProcessorLocation2ByApicId() APIRay Ni2019-04-081-1/+28
| | | | | | | | | | | GetProcessorLocation2ByApicId() extracts the package/die/tile/module/core/thread ID from the initial APIC ID. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhiqiang Qin <zhiqiang.qin@intel.com>
* UefiCpuPkg/Cpuid.h: Remove duplicated struct definition for leaf 1FHRay Ni2019-04-041-118/+8
| | | | | | | | | | | | | | | | Per SDM CPUID.0BH and CPUID.1FH outputs the same format of data in EAX/EBX/ECX/EDX except CPUID.1FH reports more level types such as module, tile, die. The patch removes the unnecessary duplicated structure definitions for CPUID.1FH because when the structure definitions for CPUID.0BH can be used for CPUID.1FH. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhiqiang Qin <zhiqiang.qin@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless functions.Eric Dong2019-04-041-35/+1
| | | | | | | | | | Remove useless APIs, simplify the code logic. BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/PiSmmCpu: Add Shadow Stack Support for X86 SMM.Jiewen Yao2019-02-281-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521 We scan the SMM code with ROPgadget. http://shell-storm.org/project/ROPgadget/ https://github.com/JonathanSalwan/ROPgadget/tree/master This tool reports the gadget in SMM driver. This patch enabled CET ShadowStack for X86 SMM. If CET is supported, SMM will enable CET ShadowStack. SMM CET will save the OS CET context at SmmEntry and restore OS CET context at SmmExit. Test: 1) test Intel internal platform (x64 only, CET enabled/disabled) Boot test: CET supported or not supported CPU on CET supported platform CET enabled/disabled PcdCpuSmmCetEnable enabled/disabled Single core/Multiple core PcdCpuSmmStackGuard enabled/disabled PcdCpuSmmProfileEnable enabled/disabled PcdCpuSmmStaticPageTable enabled/disabled CET exception test: #CF generated with PcdCpuSmmStackGuard enabled/disabled. Other exception test: #PF for normal stack overflow #PF for NX protection #PF for RO protection CET env test: Launch SMM in CET enabled/disabled environment (DXE) - no impact to DXE The test case can be found at https://github.com/jyao1/SecurityEx/tree/master/ControlFlowPkg 2) test ovmf (both IA32 and X64 SMM, CET disabled only) test OvmfIa32/Ovmf3264, with -D SMM_REQUIRE. qemu-system-x86_64.exe -machine q35,smm=on -smp 4 -serial file:serial.log -drive if=pflash,format=raw,unit=0,file=OVMF_CODE.fd,readonly=on -drive if=pflash,format=raw,unit=1,file=OVMF_VARS.fd QEMU emulator version 3.1.0 (v3.1.0-11736-g7a30e7adb0-dirty) 3) not tested IA32 CET enabled platform Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Merge StuffRsb.inc files into one in UefiCpuPkg/IncludeHao Wu2019-01-021-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1091 Previously, when compiling NASM source files, BaseTools did not support including files outside of the NASM source file directory. As a result, we duplicated multiple copies of "StuffRsb.inc" files in UefiCpuPkg. Those INC files contain the common logic to stuff the Return Stack Buffer and are identical. After the fix of BZ 1085: https://bugzilla.tianocore.org/show_bug.cgi?id=1085 The above support was introduced. Thus, this commit will merge all the StuffRsb.inc files in UefiCpuPkg into one file. The merged file will be named 'StuffRsbNasm.inc' and be placed under folder UefiCpuPkg/Include/. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Cpuid.h: Sync CPUID definition to latest SDM.Eric Dong2018-12-101-23/+597
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update CPUID definition to follow SDM 2018'11 version, changes Include: 1. Add new fields to the existed data structure, impact CPUIDs include: 1. CPUID_THERMAL_POWER_MANAGEMENT 0x06 CPUID_THERMAL_POWER_MANAGEMENT_EAX 2. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX 3. CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX 4. CPUID_EXTENDED_STATE 0x0D CPUID_EXTENDED_STATE_MAIN_LEAF_EAX CPUID_EXTENDED_STATE_SUB_LEAF_ECX 5. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX 6. CPUID_INTEL_SGX 0x12 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX 2. Add new data structures which not existed before, impact CPUID includes: 1. CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX 3. Remove fields which defined before, impact CPUID includes: 1. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX 4. Add new sub leaf which not existed before, impact CPUID includes: 1. CPUID_INTEL_RDT_ALLOCATION 0x10 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03 5. Add new CPUIDs which not exist before, new CPUIDs include: 1. CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18 2. CPUID_V2_EXTENDED_TOPOLOGY_ENUMERATION 0x1F Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib.h: Add new dependence types.Eric Dong2018-10-221-4/+17
| | | | | | | | | | | | | | | | | | V4 changes: 1. Update comments. v3 changes: 1. Move CPU_FEATURE_DEPENDENCE_TYPE definition to AcpiCpuData.h. 2. Add comments for CPU_FEATURE_BEFORE/CPU_FEATURE_AFTER. v1 changes: Add new core/package dependence types which consumed by different MSRs. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/Include/AcpiCpuData.h: Add Semaphore related Information.Eric Dong2018-10-221-1/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v3 changes: 1. Move CPU_FEATURE_DEPENDENCE_TYPE definition here from RegisterCpuFeaturesLib.h file. 2. Add Invalid type for REGISTER_TYPE which will be used in code. v2 changes: 1. Add more description about why we do this change. 2. Change structure field type from pointer to EFI_PHYSICAL_ADDRESS because it will be share between PEI and DXE. v1 Changes: In order to support semaphore related logic, add new definition for it. In a system which has multiple cores, current set register value task costs huge times. After investigation, current set MSR task costs most of the times. Current logic uses SpinLock to let set MSR task as an single thread task for all cores. Because MSR has scope attribute which may cause GP fault if multiple APs set MSR at the same time, current logic use an easiest solution (use SpinLock) to avoid this issue, but it will cost huge times. In order to fix this performance issue, new solution will set MSRs base on their scope attribute. After this, the SpinLock will not needed. Without SpinLock, new issue raised which is caused by MSR dependence. For example, MSR A depends on MSR B which means MSR A must been set after MSR B has been set. Also MSR B is package scope level and MSR A is thread scope level. If system has multiple threads, Thread 1 needs to set the thread level MSRs and thread 2 needs to set thread and package level MSRs. Set MSRs task for thread 1 and thread 2 like below: Thread 1 Thread 2 MSR B N Y MSR A Y Y If driver don't control execute MSR order, for thread 1, it will execute MSR A first, but at this time, MSR B not been executed yet by thread 2. system may trig exception at this time. In order to fix the above issue, driver introduces semaphore logic to control the MSR execute sequence. For the above case, a semaphore will be add between MSR A and B for all threads. Semaphore has scope info for it. The possible scope value is core or package. For each thread, when it meets a semaphore during it set registers, it will 1) release semaphore (+1) for each threads in this core or package(based on the scope info for this semaphore) 2) acquire semaphore (-1) for all the threads in this core or package(based on the scope info for this semaphore). With these two steps, driver can control MSR sequence. Sample code logic like below: // // First increase semaphore count by 1 for processors in this package. // for (ProcessorIndex = 0; ProcessorIndex < PackageThreadsCount ; ProcessorIndex ++) { LibReleaseSemaphore ((UINT32 *) &SemaphorePtr[PackageOffset + ProcessorIndex]); } // // Second, check whether the count has reach the check number. // for (ProcessorIndex = 0; ProcessorIndex < ValidApCount; ProcessorIndex ++) { LibWaitForSemaphore (&SemaphorePtr[ApOffset]); } Platform Requirement: 1. This change requires register MSR setting base on MSR scope info. If still register MSR for all threads, exception may raised. Known limitation: 1. Current CpuFeatures driver supports DXE instance and PEI instance. But semaphore logic requires Aps execute in async mode which is not supported by PEI driver. So CpuFeature PEI instance not works after this change. We plan to support async mode for PEI in phase 2 for this task. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Change to DOS format file.Eric Dong2018-09-301-272/+272
| | | | | | | | | | | | | Follow EDKII coding style, change file format to dos style. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1213 Cc: Dandan Bi <dandan.bi@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition.Eric Dong2018-09-261-9/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V3 changes include: 1. Keep the ReservedX not change if bit info not changed for this field. V2 changes include: 1. Use X in ReservedX fields from totally new value if MSR structure definition changed. For example, if in current structure, the max reserved variable is Reserved2, in new definition, reserved variable is begin with Reserved3. V1 Changes: Changes includes: 1. Update MSR structure definition, change some reserved fields to useful fields: 1. MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER 2. MSR_XEON_PHI_SMM_MCA_CAP_REGISTER 2. For MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER structure, it expand the field range. Old definition like below: typedef union { /// /// Individual bit fields /// struct { /// /// [Bits 15:0] LVL_2 Base Address (R/W). /// UINT32 Lvl2Base:16; /// /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the /// maximum C-State code name to be included when IO read to MWAIT /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4 /// is the max C-State to include 110b - C6 is the max C-State to include. /// UINT32 CStateRange:3; UINT32 Reserved1:13; UINT32 Reserved2:32; } Bits; /// /// All bit fields as a 32-bit value /// UINT32 Uint32; /// /// All bit fields as a 64-bit value /// UINT64 Uint64; } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER; This patch make below changes for this data structure, it expand "CStateRange" field width. old one: UINT32 CStateRange:3; UINT32 Reserved1:13; new one: UINT32 CStateRange:7; UINT32 Reserved1:9; Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition.Eric Dong2018-09-261-2/+12
| | | | | | | | | | | | | | | | | | | | | V3 changes include: 1. Keep ReservedX not change if bit info not changed for this field. V2 changes include: 1. Use X in ReservedX fields from totally new value if MSR structure definition changed. For example, if in current structure, the max reserved variable is Reserved2, in new definition, reserved variable is begin with Reserved3. V1 Changes includes: 1. Change fields which is reserved in old version: MSR_IA32_RTIT_CTL_REGISTER Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: Add new MSR name and keep old ↵Eric Dong2018-09-261-10/+24
| | | | | | | | | | | | | | | | | | | | one. Changes includes: 1. Change MSR name: 1. MSR_GOLDMONT_SGXOWNER0 => MSR_GOLDMONT_SGXOWNEREPOCH0 2. MSR_GOLDMONT_SGXOWNER1 => MSR_GOLDMONT_SGXOWNEREPOCH1 2. Keep old MSR definition (MSR_GOLDMONT_SGXOWNER0/1) for compatibility. 1. Define old MSR like below style: #define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and keep old one.Eric Dong2018-09-261-13/+27
| | | | | | | | | | | | | | | | | | Changes includes: 1. Change MSR name: 1. MSR_SKYLAKE_SGXOWNER0 => MSR_SKYLAKE_SGXOWNEREPOCH0 2. MSR_SKYLAKE_SGXOWNER1 => MSR_SKYLAKE_SGXOWNEREPOCH1 2. Keep old MSR definition(MSR_SKYLAKE_SGXOWNER0/1) for compatibility 1. Use below coding style to define old MSR #define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/CoreMsr.h: Remove old MSR.Eric Dong2018-09-261-48/+0
| | | | | | | | | | | | | | Changes includes: 1. Remove old MSR which not existed in 2018-05 version spec: 1. MSR_CORE_ROB_CR_BKUPTMPDR6 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/P6Msr.h: Remove old MSR.Eric Dong2018-09-261-48/+0
| | | | | | | | | | | | | Changes includes: 1. Remove MSR which not existed in 2018-05 version spec: MSR_P6_ROB_CR_BKUPTMPDR6. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR.Eric Dong2018-09-261-60/+0
| | | | | | | | | | | | | | Changes includes: 1. Remove old MSR which not existed in 2018-05 version spec: 1. MSR_CORE2_BBL_CR_CTL3 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR.Eric Dong2018-09-261-0/+64
| | | | | | | | | | | | | Changes includes: 1. Add new MSRs: MSR_IA32_L2_QOS_CFG/MSR_IA32_CSTAR. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs.Eric Dong2018-09-261-1/+1546
| | | | | | | | | | | | | | Changes includes: 1. Add new MSR definitions. 2. Add support platform info. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR.Eric Dong2018-09-261-3/+246
| | | | | | | | | | | | | | | | | | Changes includes: 1. Add new MSR definition: 1. MSR_XEON_PHI_PPIN_CTL 2. MSR_XEON_PHI_PPIN 3. MSR_XEON_PHI_MISC_FEATURE_ENABLES 4. MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 2. Add DisplayModule == 0x85 supports. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR.Eric Dong2018-09-263-2/+164
| | | | | | | | | | | | | Changes includes: 1. Add new MSR: MSR_*_MSRUNCORE_RATIO_LIMIT Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR.Eric Dong2018-09-261-0/+48
| | | | | | | | | | | | | Changes includes: 1. Add new MSR: MSR_SILVERMONT_PLATFORM_INFO Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for ↵Eric Dong2018-09-262-3/+276
| | | | | | | | | | | | | | | goldmont plus microarchitecture. Changes includes: 1. Add new MSR file which used for goldmont plus microarchitecture. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Include/Register/Msr: Update reference spec info.Eric Dong2018-09-2621-372/+359
| | | | | | | | | | | | | | | | | | Latest SDM has moved MSR related content from volume 3 chapter 35 to volume 4 chapter 2. Current MSR's comments need to be updated to reference the new chapter info. Changes includes: 1. Update referenced chapter info from some MSRs. 2. Update referenced SDM version info. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/AcpiCpuData.h: Remove AcpiNVS and Below 4G limitation.Eric Dong2018-08-161-22/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACPI_CPU_DATA structure first introduced to save data in normal boot phase. Also this data will be used in S3 phase by one PEI driver. So in first phase, this data is been defined to use ACPI NVS memory type and must below 4G. Later in order to fix potential security issue, PiSmmCpuDxeSmm driver added logic to copy ACPI_CPU_DATA (except ResetVector and Stack buffer) to smram at smm ready to lock point. ResetVector must below 1M and Stack buffer is write only in S3 phase, so these two fields not copy to smram. Also PiSmmCpuDxeSmm driver owned the task to restore the CPU setting and it's a SMM driver. After above change, the acpi nvs memory type and below 4G limitation is no longer needed. This change remove the limitation in the comments for ACPI_CPU_DATA definition. Cc: Marvin Häuser <Marvin.Haeuser@outlook.com> Cc: Fan Jeff <vanjeff_919@hotmail.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Clean up source filesLiming Gao2018-06-281-23/+23
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/MtrrLib: Add comments to recommend to use batch-set APIRuiyu Ni2018-01-241-0/+10
| | | | | | | | | | | | | MtrrSetMemoryAttributesInMtrrSettings() is a batch-set API. When setting multiple ranges of memory attributes, the single-set API (MtrrSetMemoryAttributeInMtrrSettings and MtrrSetMemoryAttribute) may fail, but batch-set API may succeed. Add comments to recommend caller to use batch-set API when setting multiple ranges. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Ming Shao <ming.shao@intel.com>
* UefiCpuPkg/MtrrLib: Update the comments for RETURN_BUFFER_TOO_SMALLRuiyu Ni2018-01-241-3/+7
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Ming Shao <ming.shao@intel.com>
* Revert "UefiCpuPkg: Check invalid RegisterCpuFeature parameter"Eric Dong2017-12-271-5/+0
| | | | | | | | | | | This reverts commit 5c59537c1092a1372913274636a8d766fdd97e61. Current code already has function IsCpuFeatureSupported to do the feature validation, not need this check logic anymore. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Check invalid RegisterCpuFeature parameterSong, BinX2017-12-131-0/+5
| | | | | | | | | | | | | | V2: Update function name, add more detail description. V1: Check and assert invalid RegisterCpuFeature function parameter Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* IntelSiliconPkg: Move MicrocodeUpdate from UefiCpuPkgStar Zeng2017-11-302-60/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=540 To consume FIT table for Microcode update, UefiCpuPkg/Feature/Capsule/MicrocodeUpdateDxe needs to be updated to consume IntelSiliconPkg/Include/IndustryStandard/FirmwareInterfaceTable.h, but UefiCpuPkg could not depend on IntelSiliconPkg. Since the Microcode update feature is specific to Intel, we can first move the Microcode update feature code from UefiCpuPkg to IntelSiliconPkg [first step], then update the code to consume FIT table [second step]. This patch series is for the first step. Note: No any code change in this patch, just move. Next patch will update MicrocodeUpdate to build with the package. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MtrrLib: Make comments align with functionDandan Bi2017-10-241-1/+1
| | | | | | | | Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg/MtrrLib: Update algorithm to calculate optimal settingsRuiyu Ni2017-10-161-2/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new algorithm converts the problem calculating optimal MTRR settings (using least MTRR registers) to the problem finding the shortest path in a graph. The memory required in extreme but rare case can be up to 256KB, so using local stack buffer is impossible considering current DxeIpl only allocates 128KB stack. The patch changes existing MtrrSetMemoryAttributeInMtrrSettings() and MtrrSetMemoryAttribute() to use the 4-page stack buffer for calculation. The two APIs return BUFFER_TOO_SMALL when the buffer is too small for calculation. The patch adds a new API MtrrSetMemoryAttribute*s*InMtrrSettings() to set multiple-range attributes in one function call. Since every call to MtrrSetMemoryAttributeInMtrrSettings (without-s) or MtrrSetMemoryAttribute() requires to calculate the MTRRs for the whole physical memory, combining multiple calls in one API can significantly reduce the calculation time. In theory, if N times of call to without-s API costs N seconds, the new API only costs 1 second. The new API uses the buffer supplied from caller to calculate MTRRs and returns BUFFER_TOO_SMALL when the buffer is too small for calculation. Test performed: 1. Random test a. Generate random memory settings, use the new algorithm to calculate the MTRRs. b. Read back the MTRRs and check the memory settings match the desired memory settings. c. Repeat the above #1 and #2 100000 times. 2. OVMF 32PEI + 64DXE boot to shell. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
* UefiCpuPkg/ArchitecturalMsr.h: Add RTIT TOPA table entry definition.Eric Dong2017-08-281-1/+78
| | | | | | | | | | | | Add RTIT TOPA table entry definition to architecturalMsr.h file. V2: Add RTIT_TOPA_MEMORY_SIZE definition to architecturalMsr.h file. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg MtrrLib: Remove deprecated micro.Eric Dong2017-08-071-27/+0
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg: Add Processor Trace feature definition.Eric Dong2017-08-041-0/+1
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 22:16:15 +0000