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* UefiCpuPkg/ResetVector: Remove AP waking vector from ResetVectorZhiguang Liu2023-09-182-19/+3
| | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4494 Current reset vector uses 0xffffffe0 as AP waking vector, and expects GenFv generates code aligned on a 4k boundary which will jump to this location. However, some issues are listed below 1. GenFV doesn't generate code as the comment expects, because GenFv assumes no modifications are required to the VTF-0 'Volume Top File'. 2. Even if removing VFT0 signature and let GenFv to modify, Genfv is hard-code using another flash address 0xffffffd0. 3. In the same patch series, AP waking vector code is removed from GenFv, because no such usage anymore. The existing of first two issues also approve the usage is not available for a long time. Therefore, remove AP waking vector related code. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/ResetVector: Cache Disable should not be set by default in CR0Wu, MingliangX2023-08-301-1/+1
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4511 With 64 bit build we are seeing the CD in control register CR 0 set. This causes the NEM to disabled for some specific bios profiles. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Wu, Mingliang <mingliangx.wu@intel.com>
* UefiCpuPkg/ResetVector: Remove pre-built binariesRay Ni2023-06-2716-199/+9
| | | | | | | | | | | | Because it's simpler for a platform to include the ResetVector source and having pre-built binaries add burdens of updating the pre-built binaries. This patch removes the pre-built binaries and the script that buids the pre-built binaries. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/ResetVector: Add guidance of FDF ffs ruleRay Ni2023-06-272-21/+25
| | | | | | | | | | | | | | | | | | | ResetVector assembly implementation puts "ALIGN 16" in the end to guarantee the final executable file size is multiple of 16 bytes. Because the module uses a special GUID which guarantees it's put in the very end of a FV, which should be also the end of the FD. All of these (file size is multiple of 16B, and the module is put at end of FV, FV is put at end of FD) guarantee the "JMP xxx" instruction is at FFFF_FFF0h. This patch updates INF file and ReadMe.txt to add guidance of FDF ffs rule for the ResetVector. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/ResetVector: Support 5 level page table in ResetVectorZhiguang Liu2023-05-302-0/+29
| | | | | | | | | | | | | | | | | | Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create 5 level page table. If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if 5level paging is supported, use PML5Table, otherwise, use PML4Table. If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level paging is not created, and 4level paging is at (4G-12K) and be used. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/ResetVector: Modify Page Table in ResetVectorLiu, Zhiguang2023-05-301-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In ResetVector, if create page table, its highest address is fixed because after page table, code layout is fixed(4K for normal code, and another 4K only contains reset vector code). Today's implementation organizes the page table as following if 1G page table is used: 4G-16K: PML4 page (PML4[0] points to 4G-12K) 4G-12K: PDP page CR3 is set to 4G-16K When 2M page table is used, the layout is as following: 4G-32K: PML4 page (PML4[0] points to 4G-28K) 4G-28K: PDP page (PDP entries point to PD pages) 4G-24K: PD page mapping 0-1G 4G-20K: PD page mapping 1-2G 4G-16K: PD page mapping 2-3G 4G-12K: PD page mapping 3-4G CR3 is set to 4G-32K CR3 doesn't point to a fixed location which is a bit hard to debug at runtime. The new page table layout will always put PML4 in highest address When 1G page table is used, the layout is as following: 4G-16K: PDP page 4G-12K: PML4 page (PML4[0] points to 4G-16K) When 2M page table is used, the layout is as following: 4G-32K: PD page mapping 0-1G 4G-28K: PD page mapping 1-2G 4G-24K: PD page mapping 2-3G 4G-20K: PD page mapping 3-4G 4G-16K: PDP page (PDP entries point to PD pages) 4G-12K: PML4 page (PML4[0] points to 4G-16K) CR3 is always set to 4G-12K So, this patch can improve debuggability by make sure the init CR3 pointing to a fixed address(4G-12K). Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asmLiu, Zhiguang2023-05-303-76/+33
| | | | | | | | | | | | | Combine PageTables1G.asm and PageTables2M.asm to reuse code. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/ResetVector: Simplify page table creation in ResetVectorLiu, Zhiguang2023-05-303-32/+24
| | | | | | | | | | | | | | | Currently, page table creation has many hard-code values about the offset to the start of page table. To simplify it, add Labels such as Pml4, Pdp and Pd, so that we can remove many hard-code values Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/ResetVector: Rename macros about page table.Liu, Zhiguang2023-05-302-22/+39
| | | | | | | | | | | | | | | | | | This patch only renames macro, with no code logic impacted. Two purpose to rename macro: 1. Align some macro name in PageTables1G.asm and PageTables2M.asm, so that these two files can be easily combined later. 2. Some Macro names such as PDP are not accurate, since 4 level page entry also uses this macro. PAGE_NLE (no leaf entry) is better Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Supporting S3 in 64bit PEIKuo, Ted2022-12-191-19/+44
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=4195 1.Updated the GDT table in VTF0 to align with the one in S3Resume2Pei. By doing so can simplify the changes to enable S3 in 64bit PEI. 2.Use SwitchStack() between PEI and SMM in S3 resume path when both are in the same execution mode. 3.Transfer from PEI to OS waking vector by calling SwitchStack() when both are in the same execution mode. 4.Removed the debug assertion in S3Resume.c to support 64bit PEI. Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com>
* UefiCpuPkg/ResetVector:Add Option to reserve 4K region at 4GBDuggapu, Chinni B2022-11-111-1/+9
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4140 Some implementations may need to keep the initial Reset code to be separated out from rest of the code.This request is to add padding at lower 4K region below 4 GB which will result having only few jmp instructions and data at that region. Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Duggapu Chinni B <chinni.b.duggapu@intel.com>
* UefiCpuPkg: Update BFV searching algorithm in VTF0Kuo, Ted2022-03-2810-15/+6
| | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3870 The new algorithm searches FFS3 GUID first and then FFS2 GUID at every 4KB address in the top 16MB just below 4GB. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Reviewed-by: Min Xu <min.m.xu@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com>
* UefiCpuPkg: Support FFS3 GUID in SearchForBfvBase.asmKuo, Ted2022-03-1410-10/+41
| | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3862 The new algorithm searches BFV address with FFS3 GUID first. If not found, it will search BFV address with FFS2 GUID. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com>
* UefiCpuPkg: VTF0 Linear-Address Translation to a 1-GByte Page till 512GBAshraf Ali S2021-09-1620-48/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access memory range till 512GByte via Linear- Address Translation to a 1-GByte Page. Build Tool: if the nasm is not found it will throw Build errors like FileNotFoundError: [WinError 2]The system cannot find the file specified run the command wil try except block to get meaningful error message Test Result: Tested in both Simulation environment and Hardware both works fine without any issues. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Cc: Sangeetha V <sangeetha.v@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Sahil Dureja <sahil.dureja@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
* UefiCpuPkg: ResetVector Tool additional debug printsAshraf Ali S2021-09-091-1/+4
| | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3506 Before executing the nasm command, added print statement to know what commands are executing. before printing the output file need check the status of command which is executed. if the status is 0 then only print the output file name. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Cc: Sangeetha V <sangeetha.v@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
* UefiCpuPkg: ResetVector Tool Support for Python 3Ashraf Ali S2021-09-092-5/+5
| | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3506 Build Scrips for Reset Vector currently based on Python 2 which is already EOL, needs to modify the build script based on Python 3 Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Debkumar De <debkumar.de@intel.com> Cc: Harry Han <harry.han@intel.com> Cc: Catharine West <catharine.west@intel.com> Cc: Sangeetha V <sangeetha.v@intel.com> Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
* UefiCpuPkg: Add a 16-bit protected mode code segment descriptorTom Lendacky2020-08-171-0/+9
| | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 A hypervisor is not allowed to update an SEV-ES guests register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead, an SEV-ES AP must be transition from 64-bit long mode to 16-bit real mode in response to an INIT-SIPI-SIPI sequence. This requires a 16-bit code segment descriptor. For PEI, create this descriptor in the reset vector GDT table. For DXE, create this descriptor from the newly reserved entry at location 0x28. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0927-180/+27
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Clean up source filesLiming Gao2018-06-283-6/+6
| | | | | | | | | 1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/ResetVector/Vtf0: document segment register setupLaszlo Ersek2017-11-172-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "Main.asm" calls TransitionFromReal16To32BitFlat (and does some other things) before it jumps to the platform's SEC entry point. TransitionFromReal16To32BitFlat enters big real mode, and sets the DS, ES, FS, GS, and SS registers to offset ("selector") LINEAR_SEL in the GDT (defined in "UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm"). The GDT entry ("segment descriptor") at LINEAR_SEL defines a segment covering the full 32-bit address space, meant for "read/write data". Document this fact for all the affected segment registers, as output parameters for TransitionFromReal16To32BitFlat, saying "Selector allowing flat access to all addresses". For 64-bit SEC, "Main.asm" calls Transition32FlatTo64Flat in addition, between calling TransitionFromReal16To32BitFlat and jumping to the SEC entry point. Transition32FlatTo64Flat enters long mode. In long mode, segmentation is largely ignored: - all segments are considered flat (covering the whole 64-bit address space), - with the (possible) exception of FS and GS, whose bases can still be changed, albeit with new methods, not through the GDT. (Through the IA32_FS_BASE and IA32_GS_BASE Model Specific Registers, and/or the WRFSBASE, WRGSBASE and SWAPGS instructions.) Thus, document the segment registers with the same "Selector allowing flat access to all addresses" language on the "Main.asm" level too, since that is valid for both 32-bit and 64-bit modes. (Technically, "Main.asm" does not return, but RBP/EBP, passed similarly to the SEC entry point, is already documented as an output parameter.) Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Eric Dong <eric.dong@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Suggested-by: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
* UefiCpuPkg: Convert all .uni files to utf-8Jordan Justen2015-12-156-0/+0
| | | | | | | | | | | | | To convert these files I ran: $ python3 BaseTools/Scripts/ConvertUni.py UefiCpuPkg Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19264 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: Convert non DOS format files to DOS formatGao, Liming2014-09-032-0/+0
| | | | | | | | | Module UNI and Package UNI files are not DOS format. Convert them to DOS format. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gao, Liming <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16047 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: INF/DEC file updates to EDK II packagesGao, Liming2014-08-286-0/+0
| | | | | | | | | | | | | | | | | | 2. Add MODULE_UNI_FILE file that contains the localized Abstract and Description of a module. a. Addresses an information gap between INF files and the UEFI Distribution Packaging Specification XML schema b. There will be an associated update to UPT in BaseTools to consume MODULE_UNI_FILE and associated UNI file during UDP creation that performs the INF -> XML conversion. c. There will be an associated update to UPT in BaseTools to produce MODULE_UNI_FILE and associated UNI file during UDP installation that performs the XML -> INF conversion. 3. Add Module Extra UNI file that provides the localized Name of a module. a. [UserExtensions.TianoCore."ExtraFiles"] provides an easy method for a module to specify extra files not listed in [Sources] or [Binaries] sections to be added to a UDP without having to list the files in the UPT package information data file. b. There will be an associated update to UPT in BaseTools to package up files listed in [UserExtensions.TianoCore."ExtraFiles"] during UDP creation. c. UNI file contains localized name of a module to go along with the localized Abstract and Description from the MODULE_UNI_FILE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gao, Liming <liming.gao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15934 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: INF/DEC file updates to EDK II packagesGao, Liming2014-08-283-1/+14
| | | | | | | | | | | | 1. Usage information in INF file comment blocks are either incomplete or incorrect. This includes usage information for Protocols/PPIs/GUIDs/PCDs/HOBs/Events/BootModes. The syntax for usage information in comment blocks is defined in the EDK II Module Information (INF) Specification Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gao, Liming <liming.gao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15933 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: Add ResetVector/FixupVtfJordan Justen2014-08-182-0/+92
| | | | | | | | | | | | | | | | | | | | This implements the older VTF ResetVector code often used on EDK II IA32 & X64 platforms. This VTF requires build time fixups in order to find the SEC entry point. The BaseTools GenFv tool has code that patches the jump target of the reset vector code to match the entry point of the SEC image in the PEI Firmware Volume. v2: * Rename from OldVtf to FixupVtf * Use EDK II extension of .nasmb rather than .nasmbin Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15826 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg VTF0 X64: Build page tables in NASM codeJordan Justen2014-08-185-97/+108
| | | | | | | | | | | | | | Previously, we would build the page tables in Tools/FixupForRawSection.py. In order to let NASM build VTF0 from source during the EDK II build process, we need to move this into the VTF0 NASM code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15822 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: Support building VTF0 ResetVector during the EDK II buildJordan Justen2014-08-183-5/+50
| | | | | | | | | | | | | | Using NASM we build VTF0 as part of the EDK II build process. v2: * Use EDK II extension of .nasmb rather than .nasmbin Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15821 6f19259b-4bc3-4df7-8a09-765794883524
* Fix ResetVectorVtf0.asm comment typoChen Fan2014-01-281-1/+1
| | | | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15193 6f19259b-4bc3-4df7-8a09-765794883524
* Fix CRLF formatTian, Hot2014-01-222-163/+163
| | | | | | Signed-off-by: Tian, Hot <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15162 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg/ResetVector/Vtf0: Move Page Table/CR3 setting to a new fileJordan Justen2013-09-243-4/+34
| | | | | | | | | | | | | | | | | | | | | Now, Transition32FlatTo64Flat calls SetCr3ForPageTables64 which is located in Ia32/PageTables64.asm. This change is required so OVMF can replace the code in Ia32/PageTables64.asm with code that generates page tables in RAM. Note: Since this change does not impact the functionality of the current VTF0 binaries, they are not being updated. The resulting new binaries were tested to verify there is no regression. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14714 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg VTF0: Fix support for finding SEC image of type TE.rsun32011-09-287-17/+21
| | | | | | | | | | Update Flat32SearchForSecEntryPoint assembly code to support finding an SEC image using the TE image format. Signed-off-by: rsun3 Reviewed-by: jljusten git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12462 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg VTF0: Rename README to ReadMe.txt, add nasm versionydong102011-09-201-1/+1
| | | | | | | | | | | * Rename README to ReadMe.txt * Document that nasm 2.03 or newer is required for building VTF0 Signed-off-by: ydong10 Reviewed-by: jljusten git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12384 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg VTF0: Add README, remove Makefilejljusten2011-09-152-42/+41
| | | | | | | | | | * Add README * Remove Makefile which is no longer used to build VTF0 Signed-off-by: jljusten Reviewed-by: geekboy15a git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12355 6f19259b-4bc3-4df7-8a09-765794883524
* UefiCpuPkg: Replace the un-necessary WBINVD instruction at the reset vector ↵rsun32011-08-047-2/+3
| | | | | | | | | with two NOPs in VTF0. Signed-off-by: rsun3 Reviewed-by: mdkinney git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12085 6f19259b-4bc3-4df7-8a09-765794883524
* Rename two files to follow the file naming convention.rsun32010-09-074-6/+185
| | | | git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10853 6f19259b-4bc3-4df7-8a09-765794883524
* Rename two files to follow the file naming convention.rsun32010-09-072-179/+0
| | | | git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10852 6f19259b-4bc3-4df7-8a09-765794883524
* Update the copyright notice formathhtian2010-04-2417-34/+34
| | | | git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10429 6f19259b-4bc3-4df7-8a09-765794883524
* Clean up EFI_SPECIFICATION_VERSION and PI_SPECIFICATION_VERSION.klu22010-02-251-2/+0
| | | | git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10077 6f19259b-4bc3-4df7-8a09-765794883524
* 1. Correct File header to ## @filelgao42010-02-231-3/+3
| | | | | | 2. Remove unnecessary .common] postfix on section. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10051 6f19259b-4bc3-4df7-8a09-765794883524
* Adding files from OvmfPkg to common location. This is so multiple packages ↵geekboy15a2010-02-0223-0/+1206
can use pre-built reset vector code. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9911 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-15 20:13:51 +0000