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* chipset_enable: add PCI ID for APL-I (Broxton)Jan Samek2020-07-101-0/+1
| | | | | | | | | | Change-Id: I48dba541b5893551f47f3d5ed422eb1dc36f5324 Signed-off-by: Jan Samek <jan.samek@siemens.com> Signed-off-by: Henning Schild <henning.schild@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* serial: Fix file read/write error handling for WindowsDavid Hendricks2020-07-071-8/+22
| | | | | | | | | | | | | | | | | | | File read/write semantics are different between POSIX and Windows. In particular Windows file read/write functions return a boolean type to indicate success or failure, while the POSIX equivalents return a signed integer indicating number of bytes read if successful or -1 if not. This attempts to correct some error handling paths for Windows and avoid invalid comparisons that were causing compilation issues. Reported on https://github.com/flashrom/flashrom/issues/149 Change-Id: Ib179d51ede2dbd38f54f3641bfe90340a6a87e31 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43051 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dediprog: Correct REQTYPE_OTHER_OUT macroDavid Hendricks2020-06-241-1/+1
| | | | | | | | | | | It's not used anywhere, but it should be correct if we continue to keep it in. Change-Id: I8a6941c2906dda2c5aac5e0af3364fd2ac5773f3 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree: Remove unneeded semicolons after loopsDavid Hendricks2020-06-242-2/+2
| | | | | | | | | | Trivial cleanup Change-Id: Id93a019a39b765c70b1a4eaeb25d9b582c3e4141 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mysteries_intel: Add a section for software vs hardware sequencingDavid Hendricks2020-06-201-0/+42
| | | | | | | | | | | This attempts to explain software sequencing, hardware sequencing, and the "Opaque flash chip". Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tests/spi25.c: Add unit-test coverage of spi95.cEdward O'Callaghan2020-06-173-0/+21
| | | | | | | | | | | | | | Add spi95.c unit-tests to spi25.c to avoid some clutter. BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I6de59451b82131b58114b268ff6dd0b18cd5952b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tests/: Add helper.c unit testsEdward O'Callaghan2020-06-174-0/+85
| | | | | | | | | | | | BUG=b:157280555 BRANCH=none TEST=builds Change-Id: If4a1fe7c499f51bb9d7cd48ef26caf9dfae3c1fa Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tests/: Add flashrom.c unit testsEdward O'Callaghan2020-06-174-0/+45
| | | | | | | | | | | | BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I2d9213f98c6c9639f2417466ba4895117e8d600a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add W25Q256.Wel-coderon2020-06-162-0/+42
| | | | | | | | | | | | Nicklas Lennert wrote me via the flashrom mailing list that he successfully ran read, write and verify cmd. Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Change-Id: I3608945a38b5ed42b8b2b9b2b388cdea97141d7b Reviewed-on: https://review.coreboot.org/c/flashrom/+/40855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* tests/: Add spi25.c unit testsEdward O'Callaghan2020-06-164-0/+196
| | | | | | | | | | | | BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* tests/: Add CMocka unit-test infrastructureEdward O'Callaghan2020-06-166-0/+105
| | | | | | | | | | | | | | | | This adds the CMocka unit-testing infrastructure into the meson build system which we will latter follow up with unit-tests for flashrom's core logic. BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I66665f56627b3d99049176bfbebbd771b080370a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libflashrom.c: Fix indentation of a braceAngel Pons2020-05-281-1/+1
| | | | | | | | | | | | It was indented with two spaces instead of one tab. Fix it. Change-Id: I18051ae4433b267b9552a034a67d7830b9206c20 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* libflashrom.c: Use casts on enum conversionsAngel Pons2020-05-281-2/+4
| | | | | | | | | | This allows flashrom to build with GCC 10. Change-Id: I2166cdf3681452631ef8e980face2924e9a6c81a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* Add board enable for ASUS P3B-FKeith Hui2020-05-192-1/+48
| | | | | | | | | | | With this change flashrom can detect, enable and flash on this board both under vendor BIOS and coreboot. Change-Id: I395ff50fbcda8ecdaa26033f0d99b2b0eb42f7ff Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* 82802ab.c: Remove duplicated checkAngel Pons2020-05-131-3/+3
| | | | | | | | | | Change-Id: I5d511d7ec254bdbd9926e6d8efc308fb2339cb81 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38661 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Debug flashrom crash when Write Protect is ONYuji Sasaki2020-05-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When hardware write protect is applied, flashrom crashed and generate coredump. spi_disable_blockprotect_generic() calls flash->chip->printlock() method when disable was failed, but this method is optional, can be NULL depends on type of flashrom chip. NULL pointer check before call is added to avoid crash. BRANCH=none BUG=b:129083894 TEST=Run on Mistral P2 (On CR50 console, run "wp disable") flashrom --wp-range 0 0x400000 flashrom --wp-enable (On CR50 console, run "wp enable") flashrom -r /tmp/test.bin Verify "Block protection could not be disabled!" is shown, but flash read completes. Signed-off-by: Yuji Sasaki <sasakiy@chromium.org> Change-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e Reviewed-on: https://chromium-review.googlesource.com/1535140 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: SANTHOSH JANARDHANA HASSAN <sahassan@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40468 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Enables USB retry for invalid write countBrian J. Nemec2020-05-081-3/+7
| | | | | | | | | | | | | | | | | | | | Enables the USB SPI transfer retry mechanism when the error code USB_SPI_WRITE_COUNT_INVALID is returned. This error code can indicate a recoverable USB transfer failure. BUG=b:153887087 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Modified ServoMicro to randomly corrupt USB packets when reading the packet length to replicate bad packets and the verify recovery is successful. Change-Id: I9e6b2ccec0b06aab0d6920f1bddf108058e5d6b1 Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41152 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Remove dead codeEdward O'Callaghan2020-05-071-33/+0
| | | | | | | | | | | | | | | Turns out the MST likely doesn't need these so-called defaults to be written for the purposes of spi flashing. BUG=b:152558985,b:148745673 BRANCH=none TEST=builds Change-Id: Ieb938cf0805b22692d61db23795208c9be962b60 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* realtek_mst_i2c_spi.c: Fix cmd timeout issueEdward O'Callaghan2020-05-071-8/+12
| | | | | | | | | | | | | | | | | | | | | Chip erasures take much longer than sector and bank erasures. Allow the wait loop helper to multiply the max timeout in this very specific case while quickly timeout for other ops that are expected to be shorter. V.2: Fix nonsense fall though warn-err BUG=b:152558985,b:148745673 BRANCH=none TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E && flashrom -p realtek_mst_i2c_spi:bus=8 -w foo (cycle).. Change-Id: I4a36aa3101827e69eb244775d25bbb476d4bb780 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* realtek_mst_i2c_spi.c: Fix _spi_write256() as documentedEdward O'Callaghan2020-05-061-22/+50
| | | | | | | | | | | | | | | | | | | | | | | | | Turns out broken erasures highlighted some of the issues in the write256 implementation. After a fair amount of time deciphering scarce documentation details a correct implementation was finally derived. V.2: Rename 'start_program() -> execute_write()' to clarify the intention and not to overload the term 'program' since the MST actually runs a 'program' itself. BUG=b:152558985,b:148745673 BRANCH=none TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E && flashrom -p realtek_mst_i2c_spi:bus=8 -w foo && flashrom -p realtek_mst_i2c_spi:bus=8 -r foo && hexdump -C foo Change-Id: If61ff95697f886d3301a907b76283322c39ef5c7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* realtek_mst_i2c_spi.c: Fix _spi_send_command cb for erasuresEdward O'Callaghan2020-05-061-9/+40
| | | | | | | | | | | | | | | | | | | | Before issuing SPI opcodes into 0x61 the top three BITS of 0x60 need to be carefully crafted. Correctly craft these in the case of SPI erasures and document this registers expectations. Clean up remaining debug comments while we are here. BUG=b:152558985,b:148745673 BRANCH=none TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E && flashrom -p realtek_mst_i2c_spi:bus=8 -r foo && hexdump -C foo Change-Id: Ib11ba8f63b11a1c5ebaa68deb7971648de8c2ecd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* raiden_debug_spi: Fix memleakPatrick Georgi2020-05-051-1/+3
| | | | | | | | | Change-Id: Ib9d99fefda812d20265db47be353c844f8b77129 Found-by: Coverity Scan #1420204 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi95: Check for success before using send_command's returned dataPatrick Georgi2020-05-051-1/+4
| | | | | | | | | | | If the transfer failed, the data might be invalid. Change-Id: I3ad9daa00a54e2a3954983cec91b6685f1a98880 Found-By: Coverity Scan #1405870 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* raiden_debug_spi.c: Clean up global stateEdward O'Callaghan2020-05-051-15/+42
| | | | | | | | | | | | | | | | | | | | | | The Chromium flashrom fork has very poor dispatch logic whereas upstream has proper inversion of control with a generic 'data' void * member to stuff long-lived state in. Leverage the member to store the USB descriptor state in during the life-time of the spi master. V.2: Remove unnecessary indirection as is the case in commit a25c13cdb601f9d43b0f8edad96f9489efcb4b37. BUG=b:140394053 BRANCH=none TEST=builds && detects flashchip name. Change-Id: Ida9dce97fef2c6dfd68a278c879917fdd3ff7fef Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40105 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Define some register namesEdward O'Callaghan2020-05-051-6/+14
| | | | | | | | | | | | | | | | Try to document some of the register magics with plausible names for readability. BUG=b:152558985,b:148745673 BRANCH=none TEST=builds Change-Id: I97313f6f14438e4cbfc62faa7242cf6fc271f387 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Makefile: Remove 'NEED_LIBUSB1' from lspcon requirementsEdward O'Callaghan2020-05-041-1/+0
| | | | | | | | | | | Since lspcon talks over i2c I doubt libusb is a build requirement, remove it. Change-Id: Ic4d71c10d2d8c0c881aa5732daed35c20d905a5e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* Initial Realtek MST i2c_spi supportEdward O'Callaghan2020-05-046-0/+487
| | | | | | | | | | | | | | | | | | | | | This spi master allows for programming of a Realtek RTD2142 MST with external SPI flash chip routed via its internal i2c transport mechanism. BUG=b:152558985,b:148745673 BRANCH=none TEST=echo "00000000:0004ffff fw" > layout && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -r && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -w && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-size && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-name Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40667 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libflashrom.c: Use correct type for sizeofAngel Pons2020-05-031-1/+1
| | | | | | | | | | | | | | | As we want to allocate an array of `flashrom_board_info` structs, use that type in sizeof. This did not cause problems as `board_info` was at least as big as `flashrom_board_info`, but nothing guarantees it. Change-Id: I66e875d54c9a7cc59898b072b052282b0b5cbb2f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39973 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable.c: Spell `BIOS` in uppercaseAngel Pons2020-05-031-1/+1
| | | | | | | | | | | | Intel document #336067 uses `BIOS Control` to refer to this register. Change-Id: Ib66547b2b5d77658ab1925e4ad3acfe44e14843c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40857 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "flashchips: port S25FS(128S) chip from chromiumos"Nico Huber2020-05-018-415/+6
| | | | | | | | | | | | | | | | | | | | | This reverts commit a3519561bd0fb44153bb376322b799000657576f. Breaks support for most SPI flash chips. It's too big and too invasive to be reviewed as a single commit. The changes to `spi_poll_wip():spi25.c` were not noticed in the original review that were from the similarly named function and file `s25f_poll_status():s25f.c` in the downstream Chromium fork. V.2: Rebase and rephrase commit msg to reflect how the issue slipped in. Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lspcon_i2c_spi.c: Prefix with fn name instead of just 'Error:'Shiyu Sun2020-05-011-8/+12
| | | | | | | | | | | | | | | | | Replace log lines with the prefix formatter '%s: ..' and pass '__func__' to the printers so that errors are prefixed with the function from which they originated. BUG=b:154285774 BRANCH=none TEST=build success Change-Id: If3205d8e453cfcd37f725b4fd135fe1221c913c0 Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40901 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* const'ify flashctx to align signatures with cros flashromEdward O'Callaghan2020-04-3026-53/+53
| | | | | | | | | | | | | | | | The ChromiumOS flashrom fork has since const'ify flashctx in a few places. This aligns the function signatures to match with downstream to ease forward porting patches out of downstream back into mainline flashrom. This patch is minimum viable alignment and so feedback is welcome. Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi.c: Improve handling of static bufferAngel Pons2020-04-251-3/+3
| | | | | | | | | | | | | | | If `buf` became NULL because of an error, subsequent calls to the `ft2232_spi_send_command` function with a smaller buffer size will result in a null pointer dereference. Add an additional null check before using `buf` to prevent that. Moreover, use `size_t` for the `bufsize` and `oldbufsize` variables, as it's what `realloc` uses. Change-Id: Idc4237ddca94c42ce2a930e6d00fd2d14e4f125c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39975 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25.c: Add a null checkAngel Pons2020-04-251-0/+2
| | | | | | | | | Change-Id: I5fcc23d81b8404af90768afa2954509bf334ab2c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39974 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lspcon_i2c_spi.c: Trivial style fixEdward O'Callaghan2020-04-241-1/+1
| | | | | | | | | Change-Id: I0675b467d7b0d24626a336033668bf80bfeeb815 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* stlinkv3_spi: Avoid division by zeroPatrick Georgi2020-04-241-2/+3
| | | | | | | | | | | Change-Id: I08c0612f3fea59add9bde2fb3cc5c4b5c3756516 Found-by: Coverity Scan #1412744 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* stlinkv3_spi: Fix memory leakPatrick Georgi2020-04-241-0/+1
| | | | | | | | | | | | Change-Id: Ic650b43395c64b1677f6e114b0faf42a3b7b3759 Found-by: Coverity Scan #1415214 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* usb_device: Fix memory leakPatrick Georgi2020-04-241-0/+2
| | | | | | | | | | | | Change-Id: I19c91ae881895ecc4ea85dcfd40a69bb58289a60 Found-by: Coverity Scan #1420203 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* raiden_debug_spi: Fix memleakPatrick Georgi2020-04-241-0/+3
| | | | | | | | | | | | Change-Id: I2701a8fbae63657edc9cc258666cc951f92b1115 Found-by: Coverity Scan #1420204 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* pcidev.c: Drop unused variableElyes HAOUAS2020-04-241-2/+1
| | | | | | | | | | Change-Id: I6eea3e34ed6fc5d3fe65d5cf7e7bfc5e571bfa73 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: port S25FS(128S) chip from chromiumossibradzic2020-04-228-6/+415
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This may seem too big just to support yet another flash chip, but in reality it brings support for whole new family of S25FS Spansion/Cypress flash chips. These chips require handling of some special status registers for erasing or writing, with very specific timing checks in place. For example, WIP status bit will remain being set to 1 if erase or programming errors occur, and in that case chip 'software reset' has to be performed otherwise the chip will remain unresponsive to all further commands. Also, special CR3NV register (Configuration Register 3 Nonvolatile) status bits needs to be read and set by using RDAR (ReaD Any Register) and WRAR (WRite Any Register) OP commands, and these states are needed to determine which type of reset feature is enabled at the time (legacy or S25FS type) in the first place, determine whether Uniform or Hybrid sector architecture is used at the time, or set programming buffer address wrap point (256 or 512 bytes). Furthermore, S25FS chip status register has to be restored to its original state (hence that ugly CHIP_RESTORE_CALLBACK) following erasing or writing, failing to do so may result in host being unable to access data on the chip at all. Finally, although this brings support for the whole family of chips, I only have one such chip to do the actual testing, S25FS128S (Small Sectors), which I had fully tested on ch341a and FT4232H programmers, with confirmed working probe, read, erase and write. Full summary of changes are here: flashchips: add new flashchip sctructure property: .reset add chip definitions: S25FS128S Large Sectors S25FS128S Small Sectors flash: add macro (chip_restore_func_data call-back): CHIP_RESTORE_CALLBACK flashrom: add struct: chip_restore_func_data add call-back function: register_chip_restore spi: add OP codes: CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST add register bit function definitions: CR3NV_ADDR, CR3NV_20H_NV add timers: T_W, T_RPH, T_SE spi25: refactor (based on chromiumos implementation) function: spi_poll_wip port these functions from chromiumos: probe_spi_big_spansion s25fs_software_reset s25f_legacy_software_reset s25fs_block_erase_d8 spi25_statusreg: port these functions from chromiumos: spi_restore_status s25fs_read_cr s25fs_write_cr s25fs_restore_cr3nv Most of the ported functions are originally from s25f.c found at https://chromium.googlesource.com/chromiumos/third_party/flashrom with exception of spi_restore_status which is defined in spi25_statusreg.c. The rest of macros and OP codes are defined in same files as in this commit. Change-Id: If659290874a4b9db6e71256bdef382d31b288e72 Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* lspcon_i2c_spi.c: Clean up some unnecessary indirectionEdward O'Callaghan2020-04-191-11/+7
| | | | | | | | | | | | | | | | | | Clean up some confusion of implicit copies by indirection. This allows the caller of register_spi_master() to have it's internal state in the expected way. Also add an error when the mpu reset fails on init. BUG=b:148746232,b:153027771,b:140394053 BRANCH=none TEST=builds Signed-off-by: Edward O'Callaghan <quasisec@google.com> Change-Id: I66ba4ffeb696309b8ad5b5ba58650630e8feefa9 Reviewed-on: https://review.coreboot.org/c/flashrom/+/40470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable.c: Disable SPI on ICH7 if booted from LPCAngel Pons2020-04-171-0/+8
| | | | | | | | | | | | | | | | | | | | | | Commit 92d6a86 ("Refactor Intel Chipset Enables") eliminated a check to disable SPI when ICH7 has booted from LPC, as the hardware does not support it. Therefore, when flashrom probes the SPI bus, it times out waiting for the hardware to react, for each and every SPI flash chip. This results in very long delays and countless instances of the error: Error: SCIP never cleared! To prevent this, bring back part of the lost check. Probing for LPC and FWH when booted from SPI does not seem to cause any problems on desktop mainboards with ICH7, so don't disable LPC nor FWH if that is the case. Tested on ECS 945G-M4 (ICH7, boots from LPC), works without errors. Change-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* cli_classic.c: Prevent memory leakAngel Pons2020-04-141-0/+3
| | | | | | | | | | | If the `--flash-contents` switch is specified more than once, it will result in a memory leak. Therefore, allow this option only once. Change-Id: I530933c9a6431580fe4645396bb363939472a80a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39972 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for Winbond W25Q64JWScott Chao2020-04-092-0/+41
| | | | | | | | | | | | | | BUG=b:153515968 BRANCH=kukui TEST=flash coreboot on kakadu and get successful result. Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967 Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40275 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add W25Q512JVJoel Stanley2020-04-082-0/+45
| | | | | | | | | | | | | https://www.winbond.com/resource-files/W25Q512JV%20DTR%20RevB%2006132019%20133.pdf Tested with dediprog SF100. Change-Id: I8d16f0918785795cc49500435a03641b87d706e9 Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi.c: change the chunksize from 256 to 270el-coderon2020-04-081-1/+1
| | | | | | | | | | | | | | | This is to really make use of page write time advantage. Because the Chunksize must be 256Byte raw data plus the address and cmd bytes. For details check: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/W2HULJTDPHWPBZY6MLM6TGT7RTHSGHON/ Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Change-Id: Iac067a23025e9df053ab9cd4e82a98de70046c18 Reviewed-on: https://review.coreboot.org/c/flashrom/+/39632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lspcon_i2c_spi.c: Add SPI-master support for PS17{5,6}Shiyu Sun2020-04-016-0/+556
| | | | | | | | | | | | | | | | | | | | | | | | This adds support for the Parade lspcon usb-c to HDMI protocol translater part that is i2c-controlled. The support allows the host to reach the SPI ROM that hangs off the part where it stores its firmware. Usage is as follows: flashrom -p lspcon_i2c_spi:bus=X where X is the bus number. BUG=b:148746232 BRANCH=none TEST=tested with following commands, read/write/erase works good. flashrom -p lspcon_i2c_spi:bus=7 -r /tmp/foo; flashrom -p lspcon_i2c_spi:bus=7 -E; flashrom -p lspcon_i2c_spi:bus=7 -w /tmp/foo; Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7 Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* i2c_helper: Add support for the Linux I2C subsystemShiyu Sun2020-04-014-0/+239
| | | | | | | | | | | | | | | | | See https://www.kernel.org/doc/Documentation/i2c/ for details. This creates common interface for I2C access functions, and adds implementation for linux I2C functions. BUG=b:148746232 BRANCH=none TEST=build success Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: Ie0487824dfb71970bede17f617dbbb30ddf78c12 Reviewed-on: https://review.coreboot.org/c/flashrom/+/39686 Tested-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Makefile: Fix 'CONFIG_ENABLE_LIBUSB1_PROGRAMMERS=no'Edward O'Callaghan2020-03-281-0/+1
| | | | | | | | | | | Turns out CONFIG_RAIDEN was missing in the LIBUSB1 as no overrides. Credit to HAOUAS Elyes for spotting this. Change-Id: I7dd26665a0133175949c11717837e9de68a1bf71 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-18 23:39:24 +0000