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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-02-16 16:20:19 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-03-10 17:07:08 +0100 |
| commit | 85af88b8f7d606be8a9b89fcda61a5df28a2028d (patch) | |
| tree | 550d0412b84fd6f665ef76c67f5fc5868fad7bbd /drivers/clk/renesas | |
| parent | 88ddf98aa511a5e0c2c76e5dfcf3c6b2581d0e85 (diff) | |
| download | linux-stable-85af88b8f7d606be8a9b89fcda61a5df28a2028d.tar.gz linux-stable-85af88b8f7d606be8a9b89fcda61a5df28a2028d.tar.bz2 linux-stable-85af88b8f7d606be8a9b89fcda61a5df28a2028d.zip | |
clk: renesas: r8a77980: Add Z2 clock
Add support for the Z2 (Cortex-A53 System CPU) clock on R-Car V3H, which
uses a fixed SYS-CPU divider.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/aad9eaa57acf65cbe43e4d374066a72d760d54d8.1676560357.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a77980-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index 6dc63eaf1155..bac92c606d0b 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -72,6 +72,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ + DEF_FIXED("z2", R8A77980_CLK_Z2, CLK_PLL2, 4, 1), DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1), |