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* treewide: Move list.h to commonlibMaximilian Brune2024-02-243-0/+69
| | | | | | | | | | | It is needed in order to move device_tree.c into commonlib in a subsequent commit. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I16eb7b743fb1d36301f0eda563a62364e7a9cfec Reviewed-on: https://review.coreboot.org/c/coreboot/+/77968 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib: Change GCD function to always use 64 bitsJulius Werner2024-02-082-3/+3
| | | | | | | | | | | | | | | | | | | | It seems that we have some applications where we need to calculate a GCD in 64 bits. Now, we could instantiate the algorithm multiple times for different bit width combinations to be able to use the most efficient one for each problem... but considering that the function usually only gets called once per callsite per stage, and that software emulation of 64-bit division on 32-bit systems doesn't take *that* long either, we would probably usually be paying more time loading the second instance of the function than we save with faster divisions. So let's just make things easy and always do it in 64-bit and then nobody has to spend time thinking on which version to call. Change-Id: I028361444c4048a0d76ba4f80c7334a9d9983c87 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80319 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
* commonlib: Add assembly optimization for ipchksum() on x86Julius Werner2024-02-021-1/+24
| | | | | | | | | | | | | | | This patch adds a bit of optimized assembly code to the ipchksum() algorithm for x86 targets in order to take advantage of larger load sizes and the add-with-carry instruction. The same assembly (with one minor manual tweak) works for both 32 and 64 bit mode (with most of the work being done by GCC which automatically inserts `rax` or `eax` in the inline assembly depending on the build target). Change-Id: I484620dc14679ff5ca02b2ced2f84650730a6efc Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80255 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib: Add assembly optimization for ipchksum() on arm64Julius Werner2024-02-021-0/+25
| | | | | | | | | | | | | | This patch adds a bit of optimized assembly code to the ipchksum() algorithm for arm64 targets in order to take advantage of larger load sizes and the add-with-carry instruction. This improves execution speed on a Cortex-A75 by more than 20x. Change-Id: I9c7bbc9d7a1cd083ced62fe9222592243a796077 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Yidi Lin <yidilin@google.com>
* lib: Move IP checksum to commonlibJulius Werner2024-02-023-0/+66
| | | | | | | | | | | | | | | | | | | | | | This patch moves the IP checksum algorithm into commonlib to prepare for it being shared with libpayload. The current implementation is ancient and pretty hard to read (and does some unnecessary questionable things like the type-punning stuff which leads to suboptimal code generation), so this reimplements it from scratch (that also helps with the licensing). This algorithm is prepared to take in a pre-calculated "wide" checksum in a machine-register-sized data type which is then narrowed down to 16 bits (see RFC 1071 for why that's valid). This isn't used yet (and the code will get optimized out), but will be used later in this patch series for architecture-specific optimization. Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
* acpi,arch,commonlib: Rename Makefiles from .inc to .mkMartin Roth2024-01-242-0/+0
| | | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ice5dadd3eaadfa9962225520a3a75b05b44518ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/80066 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* commonlib/bsd/compiler.h: Define __section(section) macroYu-Ping Wu2024-01-221-0/+4
| | | | | | | | | | | Define __section(section) to be a shorthand for __attribute__((__section__(section))). Change-Id: I67a37e5b2aae0bfa68b0319c477ab5d6c55e6501 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* commonlib/bsd: Tag CBMEM IDs deprecated for crashlogPratikkumar Prajapati2023-12-201-2/+2
| | | | | | | | | | | | | | | These IDs are not used as crashlog data is not stored in CBMEM now. (Ref CL: I43bb61485b77d786647900ca284b7f492f412aee Title: soc/intel/common,mtl: Refactor BERT generation flow for crashlog) BUG=b:298234592 TEST=Able to build REX. Change-Id: Ie38571dece89a995d582099d34f0a1dd57cb936f Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* vendorcode/amd/opensil: Add initial setup and API callsArthur Heymans2023-12-061-1/+3
| | | | | | | | | | | | | - First a console is set up for opensil. - After that a region in CBMEM is reserved and passed to opensil which will use it as a buffer for input/output information. - Finally opensil is called and the return value handled. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* commonlib/bsd: Use tabs instead of whitespacesVarshit Pandya2023-12-061-3/+3
| | | | | | | | | Change-Id: I05e7ba10e499ea1e824bdd6c87df05fc5a0864f8 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79400 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Allow to build romstage sources inside the bootblockArthur Heymans2023-11-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* commonlib: Add GCD functionYidi Lin2023-11-043-0/+36
| | | | | | | | | | | | | | | | Implement a simple GCD function. BUG=b:307790895 TEST=emerge-geralt coreboot TEST=make tests/commonlib/bsd/gcd-test Change-Id: I21819cda4299b3809b8ca7a95cbdc6a87e4b3481 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78798 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/fsp_relocate: Fix potential NULL pointer dereferenceJeremy Compostella2023-11-021-9/+3
| | | | | | | | | | | | | | | | | | | | | Commit 1df1cf994aa9 ("commonlib/fsp_relocate: add PE32 section support") introduced a potential NULL pointer dereference if there is PE32 binary to relocate outside of the first firmware volume. The `fih_offset' pointer was used as an output variable but now it is also used as an input variable to pass the FSP information header to the `pe_relocate()' function. This commit resolves this potential NULL-pointer dereference by passing the pointer systematically and without affecting the logic as it is only set if it has not been set before. Change-Id: I9fad90a60854d5f050aa044a5c0b3af91c99df4a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78501 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cbfs: Restore 32-bit padding in cbfs_headerIvan Jager2023-10-061-1/+1
| | | | | | | | | | | | | | | | | | It was changed from a fixed size-1 array to a flexible array in commit 242bac0e162c ("…: Use C99 flexible arrays") which resulted in a change to the serialized format as the header size was no longer the same. That broke other tools that read CBFS files, like diffoscope https://github.com/NixOS/nixpkgs/issues/256896 Change-Id: I4199dcc4823469c5986ac967a55b1c85cc62f780 Signed-off-by: Ivan Jager <aij+git@mrph.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78239 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* {commonlib, libpayload}: Add "has_external_display" in coreboot tableSubrata Banik2023-10-041-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a new coreboot table entry named "has_external_display" to understand if external display is attached. This information is useful to prevent graceful shutdown by payload when the LID is closed but an external display is present. This piece of the information will be gathered by coreboot and passed into the payload using this new entry aka external_display because payload (i.e., deptcharge) doesn't have any other way to determine if external display is available. BUG=b:299137940 TEST=Able to build and boot google/rex. w/o this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > System is powered off by depthcharge w/ this patch: LID closed and external display attached (HDMI) in developer mode (GBB 0x39): > Booted to OS and device is alive/usable Change-Id: I0fa7eee4c5a50371a7a66c6ca1ac2c7d046d010b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77796 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib: Make CBMEM_ID_CSE_BP_INFO little endian, fix id for stringSubrata Banik2023-09-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes the mistake introduced with 'commit 17cea380d985 ("commonlib: Add CBMEM ID to store CSE Boot Partition Info")' where single CBMEM ID name `CBMEM_ID_CSE_INFO` is associated with two different name description. Additionally, use little endian format for `CBMEM_ID_CSE_INFO` cbmem id. TEST=Build and boot google/rex. Able to fix the issue introduced in commit 17cea380d985 while running cbmem --list and verify that the associated name string is proper. Change-Id: I4235f1f6881ab86ccb252065e922d5d526f7f1f7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78110 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
* commonlib: Add CBMEM ID to store CSE Boot Partition InfoKrishna Prasad Bhat2023-09-231-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. In order to backup PSR data before initiating firmware downgrade, CSE Lite firmware supports a command to do this. This command works only after memory has been initialized. So the CSE firmware downgrade can be done only in post-RAM stage. CSE firmware sync actions will be moved to early ramstage to support this. Moving CSE firmware sync actions to ramstage results in cse_get_bp_info command taking additional boot time of ~45-55ms. To avoid this, cse_get_bp_info will be sent in early romstage and the response will be stored in cbmem to avoid sending the command again, and re-use in ramstage. This patch adds a CBMEM ID to store this CSE Boot Partition Info response in cbmem. BUG=b:273207144 Change-Id: I914befadab4ad0ac197435e2a2c4343a796b2b1b Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
* soc/intel/cmd/blk/cse: Shorten CBMEM field name for better alignmentDinesh Gehlot2023-09-131-1/+1
| | | | | | | | | | | | | | | | | This patch shortens the name of the CBMEM field CBMEM_ID_CSE_INFO from "CSE SPECIFIC INFORMATION" to "CSE SPECIFIC INFO" to improve the alignment of the text on the screen. The functionality of the field has not been changed. BUG=NA Test=Boot verified on rex board. Change-Id: I39c716dab7d02d49e7d552cff77d544a1c168433 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77743 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch to drivers/intel: Fix misspellings & capitalization issuesMartin Roth2023-09-084-4/+4
| | | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic52f01d1d5d86334e0fd639b968b5eed43a35f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77633 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib: Add ELOG_TYPE_FW_SPLASH_SCREEN eventLogSubrata Banik2023-08-291-0/+5
| | | | | | | | | | | | | | | | This patch adds a new eventLog type ELOG_TYPE_FW_SPLASH_SCREEN to support logging when we show firmware splash screen to the user. BUG=b:284799726 TEST=Event shows in eventlog when user selects BMP_LOGO and HAVE_FSP_LOGO_SUPPORT configs. Change-Id: Id1572ecb83ca025ff65608e7ae4f3a065024f6d4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77507 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib: Add PSR backup eventlog typesKrishna Prasad Bhat2023-08-251-0/+7
| | | | | | | | | | | | | | | | | | | | | Add new eventlog types to support logging of Platform Service Record (PSR) backup related messages. Eventlog entries are added on PSR data backup success/failure and also when PSR data is lost. BRANCH=None BUG=b:273207144 TEST=Verify elog event added after PSR data backup command is sent cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent ... ELOG: Event(B9) added with size 10 at 2023-07-27 06:44:49 UTC Change-Id: I01ce3f7ea24ff0fdbb7a202ec3c75973b59d4c14 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77004 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib: Remove unused CBMEM IDSubrata Banik2023-08-181-2/+0
| | | | | | | | | | | | | | This patch removes unused CBMEM ID named `CBMEM_ID_CSE_PARTITION_VERSION`. BUG=b:285405031 TEST=Able to build and boot google/rex w/o any compilation error. Change-Id: I83f53b7f64bdef62a8ee2061d5a9c9e22bc4b8a4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77179 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/cse: Refactor CSE RW FW Version implementationSubrata Banik2023-08-181-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a CSE firmware specific data in order to store Intel CSE and associated firmware related information which requires a sync between Pre-RAM and Post-RAM phase. This information will be used further to retrieve currently running CSE RW firmware instead of fetching the version information by sending a HECI cmd (which consumes 7ms-15ms depending upon the CSE operational state). Current implementation attempts to simply the CSE RW FW version store and retrieval operations as below * CSE sync in romstage (aka Pre-RAM) - Relying on .bss segment to store the CSE info data in absence of real physical memory and sync back into the CBMEM once available (after FSP-M exits). * CSE sync in ramstage (aka Post-RAM) - Directly stored the CSE RW version into the CBMEM (as CBMEM is online). BUG=b:285405031 TEST=Able to build and boot google/rex. Verified CSE RW FW version (for LITE SKU) is getting displayed without impacting the boot time. w/o this patch: 10:start of ramstage         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) w/ this patch: 10:start of ramstage                         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) Change-Id: Ia873af512851a682cf1fac0e128d842562a316ab Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77174 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* soc/intel: Update all references to ESE as ISSEUsha P2023-08-171-2/+2
| | | | | | | | | | | | | | | Intel has rebranded ESE as ISSE (Intel Silicon Security Engine),so all references to ESE is updated to ISSE in the current coreboot code. BUG=None TEST=Build all the variants based on Intel Meteor Lake SoC Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I1f8785704706d56a35e94a0f3386bc551cd1f263 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77241 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* commonlib,console,nb,sb,security: Add SPDX licenses to MakefilesMartin Roth2023-08-141-0/+2
| | | | | | | | | | | | | | | | | | | | | To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the commonlib, console, northbridge, security, and southbridge directories that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I02804a10d0b0355e41271a035613d9f3dfb122f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* commonlib/fsp_relocate: Fix pe_relocate() return value on successJeremy Compostella2023-08-051-1/+1
| | | | | | | | | | | | | | | | Similarly to te_relocate(), on success pe_relocate() should return 0. It has never been an issue so far as pe_relocate() return value is not tested. Change-Id: I8e531662952d12e1f0ffa34042dab778ea602bfc Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76891 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* commonlib/tpm_log_serialized.h: Use C99 flexible arraysElyes Haouas2023-08-011-1/+1
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I16ac584781214350355e0625f8a2eca39a37cf85 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* commonlib/timestamp_serialized.h: Use C99 flexible arraysElyes Haouas2023-08-011-1/+1
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Ibd1e4bc96a2f5eea746328a09d123629c20b272c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* commonlib/bsd/cbfs_serialized.h: Use C99 flexible arraysElyes Haouas2023-07-311-3/+3
| | | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I00807a435a21e078c89f797cfd0b00d03604ea0e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76786 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/commonlib/bsd/mem_chip_info.h: Use C99 flexible arraysElyes Haouas2023-07-301-1/+1
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Ia1d597c0e3e86db8c13829e58a8a27d9de1480b4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76788 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/fsp_relocate.c: Use C99 flexible arraysElyes Haouas2023-07-301-1/+1
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I52b5a83e7e484889bfef5a4e45a0279fadd58890 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* commonlib/coreboot_tables.h: Use C99 flexible arraysElyes Haouas2023-07-301-7/+7
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I495605190b2c6cd11c7f78727ab4611e10b4d9d3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/cbmem: add parsing of TPM logs per specsSergii Dmytruk2023-07-041-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CBMEM can contain log in different forms (at most one is present): - coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as LB_TAG_TPM_CB_LOG) - TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG) - TPM2 format (CBMEM_ID_TPM2_TCG_LOG) The last two follow specifications by Trusted Computing Group, but until now cbmem couldn't print them. These formats were added not so long ago in: - commit 4191dbf0c9a5 ("security/tpm: add TPM log format as per 1.2 spec") - commit 53db677586e3 ("security/tpm: add TPM log format as per 2.0 spec") These changes make cbmem utility check for existence of TPM1.2/TPM2 logs in CBMEM and add code necessary for parsing and printing of their entries. TEST=`cbmem -L` for CONFIG_TPM1=y case TCPA log: Specification: 1.21 Platform class: PC Client TCPA log entry 1: PCR: 2 Event type: Action Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e Event data: FMAP: FMAP TEST=`cbmem -L` for CONFIG_TPM2=y case TPM2 log: Specification: 2.00 Platform class: PC Client TPM2 log entry 1: PCR: 2 Event type: Action Digests: SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c Event data: FMAP: FMAP Change-Id: Ib76dc7dec56dd1789a219539a1ac05a958f47a5c Ticket: https://ticket.coreboot.org/issues/425 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68749 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/post_codes.h: Fix POST_EXIT_PCI_SCAN_BUS descriptionlilacious2023-06-251-2/+2
| | | | | | | | | | | | | | | Description of POST_EXIT_PCI_SCAN_BUS indicates the opposite of what its name suggests. Secondly, POST_ENTER_PCI_SCAN_BUS and POST_EXIT_PCI_SCAN_BUS have identical comments, which appears to be a copy-paste issue. Change the description accordingly. Change-Id: Ifc920651255bacf033cac39f0208d817f9ee84fc Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76047 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious2023-06-231-61/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* {commonlib/drivers}: Have option to store MRC version inside CBMEMSubrata Banik2023-06-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces CBMEM ID to store the MRC version (similar to existing implementation that stores the FSP-M version inside CBMEM ID) inside cbmem so the version information is available across the different coreboot stages. For example: * romstage: Use the CBMEM ID version information to check if the MRC cache is valid and need to erase the MRC cache * ramstage: Use the CBMEM ID to store the MRC cache into the non-volatile space. BUG=b:261689642 TEST=Able to build and boot google/rex and dump the MRC version as below. cbmem --list CBMEM table of contents: NAME ID START LENGTH ... 21. MRC VERSION 5f43524d 75ffeb60 00000004 ... localhost ~ # cbmem -r 5f43524d | hexdump 00000000 01 12 07 00 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I91f735239b33c6f8ba41c076048903e4b213c6a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75921 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/crashlog: Add support for IOE diePratikkumar Prajapati2023-06-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Intel Meteor Lake SOC has a separate I/O Expander (IOE) die. SRAM from this IOE die contains crashlog records for the IPs of the IOE die. This patch adds functions with empty implementation using __weak attribute for IOE die related crashlog, changes common data structures while maintaining backwards compatibility, and support for filling IOE crashlog records, guarded by SOC_INTEL_IOE_DIE_SUPPORT config and makes cl_get_pmc_sram_data function as weak because it needs SOC specific implementation. Bug=b:262501347 TEST=Able to build. With Meteor Lake SOC related patch, able to capture and decode crashlog Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75475 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/bsd/tpm_log_defs.h: replace macro with enumHimanshu Sahdev2023-05-281-19/+21
| | | | | | | | | | | replace multiple existing EV_* defines with enum ec_enum. Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Change-Id: Id58fc12134915cbeb41cccb54aae9bc3f7dde4b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75324 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib: compiler.h: Add __printf macroJeremy Compostella2023-05-151-0/+4
| | | | | | | | | | | | | | | | | | | | This patch adds the `__printf' macro to comply with checkpatch following warning: Prefer __printf(1, 2) over __attribute__((format(printf, 1, 2))) BRANCH=firmware-brya-14505.B TEST=Successful compilation with `__printf(1, 2)' instead of `__attribute__((format(printf, 1, 2)))' Change-Id: Ic2d90478ab0955c2ad0955e8cff5be76bfb2e741 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75159 Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEMSubrata Banik2023-04-211-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch implements an API that stores the CSE firmware version in the CBMEM table. The API will be called from RAMSTAGE based on boot state machine BS_PRE_DEVICE/BS_ON_EXIT Additionally, renamed ramstage_cse_fw_sync() to ramstage_cse_misc_ops() in order to add more CSE related operations at ramstage. This patch also adds a configuration option, 'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` config and platform should be flexible enough to opt out from enabling this feature. The cost of sending HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to read the CSE RW version on every cold reset (to cover the CSE update scenarios) and store into CBMEM to avoid the cost of resending the HECI command in all consecutive warm boots. Later boot stages can just read the CBMEM ID to retrieve the ISH version if required. Finally, ensure this feature is platform specific hence, getting enabled for the platform that would like to store the ISH version into the CBMEM and parse to perform some additional work. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* commonlib: Add new "DMU load completed" TSBora Guvendik2023-04-041-0/+2
| | | | | | | | | | | | | | | | | | | | | 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Boot to OS, check cbmem -t Change-Id: I4d2da820f39c40ea864d15d25a94a68497b2af3d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74047 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/coreboot_tables.h: Fix typo in enum type nameAngel Pons2023-04-031-1/+1
| | | | | | | | | | | | | Fix a typo in an enum's type name, "tmp" ---> "tpm". The enum type is not used anywhere in the coreboot tree. Change-Id: Ie7529e7ee80aa9661ec053da8211c2c3295b3942 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* commonlib/coreboot_tables.h: Replace spaces with tabsAngel Pons2023-04-021-1/+1
| | | | | | | | | | | | Indent with tabs for the sake of consistency with the rest of the code. Change-Id: Ibd325a7a8348cc1f9023e54dceab40d02a0df233 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* security/tpm: add TPM log format as per 2.0 specSergii Dmytruk2023-03-041-0/+37
| | | | | | | | | | | | | | Used by default for all boards with TPM2 which don't specify log format explicitly. Change-Id: I0fac386bebab1b7104378ae3424957c6497e84e1 Ticket: https://ticket.coreboot.org/issues/422 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* security/tpm: add TPM log format as per 1.2 specSergii Dmytruk2023-03-042-3/+45
| | | | | | | | | | | | | Used by default for all boards with TPM1 which don't specify log format explicitly. Ticket: https://ticket.coreboot.org/issues/423 Change-Id: I89720615a75573d44dd0a39ad3d7faa78f125843 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* lib: set up specific purpose memory as LB_MEM_SOFT_RESERVEDJonathan Zhang2023-03-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CXL (Compute Express Link) [1] is a cache-coherent interconnect standard for processors, memory expansion and accelerators. CXL memory is provided through CXL device which is connected through CXL/PCIe link, while regular system memory is provided through DIMMs plugged into DIMM slots which are connected to memory controllers of processor. With CXL memory, the server's memory capacity is increased. CXL memory is in its own NUMA domain, with longer latency and added bandwidth, comparing to regular system memory. Host firmware may present CXL memory as specific purpose memory. Linux kernel dax driver provides direct access to such differentiated memory. In particular, hmem dax driver provides direct access to specific purpose memory. Specific purpose memory needs to be represented in e820 table as soft reserved, as described in [2]. Add IORESOURCE_SOFT_RESERVE resource property to indicate (memory) resource that needs to be soft reserved. Add soft_reserved_ram_resource macro to allow soc/mb code to add memory resource as soft reserved. [1] https://www.computeexpresslink.org/ [2] https://web.archive.org/web/20230130233752/https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.32&id=262b45ae3ab4bf8e2caf1fcfd0d8307897519630 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52585 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* commonlib/bsd, libpayload: Do not include helpers.h in stddef.hThomas Heijligen2023-02-162-0/+2
| | | | | | | | | | | | `stddef.h` should only provide the definitions defined by ISO or Posix. The included `commonlib/bsd/helpers.h` provide a lot of non standard definitions that may interfere with definitions from the application. Change-Id: Ia71edbc3ffe6694ff4b971decf3a41f915264bc8 Signed-off-by: Thomas Heijligen <src@posteo.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70116 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/storage: Add attach callback to sdhci_ctrlrShelley Chen2023-02-083-5/+24
| | | | | | | | | | | | | | | | Adding a attach callback function pointer in case a platform needs to execute anything before the standard initialization of the sdhci mem controller. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I0f37ec09d083922cad5ecd3c47b184cf3311fe2d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* bsd/cb_err: Add error code for UEFI variable storePatrick Rudolph2023-02-071-0/+10
| | | | | | | | | | | Add a new set of errors that will be used by the introduced EFI non-volatile variable store in flash. Change-Id: I6baea9fb138d1a2755d22a3d587105793adb9c90 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* src: Move POST_BOOTBLOCK_CAR to common postcodes and use itMartin Roth2023-02-071-0/+6
| | | | | | | | | | | | | | | | | | This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific postcodes into the common postcode list, and uses it for the cache-as-RAM init as needed. Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in most of the others, the values were consolidated into 0x21. This will change the value on some platforms. Any conflicts should get sorted out later in the conversion process. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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