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* soc/intel/common/graphics: Add another Meteor Lake device IDWonkyu Kim2022-07-071-1/+2
| | | | | | | | | | | | | Add 0x7d55 as another ID for Meteor Lake graphics controllers. TEST=Boot with MTL silicon to check coreboot log for DID2 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
* soc/intel: Add Raptor Lake device IDszhixingma2022-06-281-1/+4
| | | | | | | | | | | | | | | | | | Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Booted to OS on adlrvp + rpl silicon Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Add Meteor Lake SA device IDSubrata Banik2022-06-221-0/+1
| | | | | | | | | | | | | | | Add Meteor Lake SA device ID 0x7d14 (4+8, 15W). BUG=b:224325352 TEST=Able to build MTL SoC and verified SA DID is now shown proper. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake/report_platform.c: Add ADL-S identificationMichał Żygowski2022-06-171-0/+15
| | | | | | | | | | | | | Based on DOC #619501, #619362 and #618427 TEST=Boot MSI PRO Z690-A DDR4 WIFI and see the silicon info is reported as ADL-S. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I8051113515ef63fc4687f53d25140a3f55aadb6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driverSubrata Banik2022-06-031-4/+4
| | | | | | | | | | | | | | | | | | | | | This patch removes the MTL CNVi DIDs macros from IA common code and is added into the generic wifi driver. As per Intel Connectivity Platform BIOS Guide, Connectivity Controller IP for MTL-P is `Magnetar` and supported CRF is `Typhoon Peak 2`. Previously Garfield Peak DIDs for Alder Lake SoC also added similarly to generic wifi drivers. BUG=b:224325352 TEST=Able to build and boot on MTL emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib98762749c71f63df3e8d03be910539469359c68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
* soc/intel/ehl: Use defines for Ethernet controller IDsMario Scheithauer2022-05-201-0/+5
| | | | | | | | | | Use defines for a better reading of the code. Change-Id: I8e696240d649c0ea2341b8f04b62eebffebc1d57 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64519 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/wifi/generic: Add new device IDBora Guvendik2022-05-161-0/+1
| | | | | | | | | | New device id 0x51f1 is added. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I695309d529a117bad68fc89a7f136e69cecb95d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel: Add Raptor Lake device IDsBora Guvendik2022-05-161-3/+56
| | | | | | | | | | | | | | | | Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs. References: RaptorLake External Design Specification Volume 1 (640555) 600/700 Series PCH External Design Specification Volume 1 (626817) Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
* drivers/net/r8168: Add support for Realtek RTL8111KRaihow Shi2022-03-241-3/+4
| | | | | | | | | | | | | | The Realtek RT8168 and RTL8111K have a similar programming interface, therefore add the PCI device ID for the RTL8111K into driver for support. BUG=b:226253265 TEST=emerge-brask coreboot chromeos-bootimage. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I5ad8f14483393d6f25026847cc0d4229d362bba0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* soc/intel/adl-n: Add device ID for TCSS XHCIMaulik V Vaghela2022-03-231-0/+1
| | | | | | | | | | | | | | | | | | | | This patch adds TCSS XHCI device ID for ADL-N CPU which is required for USB3 port enumeration. Document Reference: 645548 revision 1.0 (Chapter 2.3) BUG=None BRANCH=None TEST=Check if device is detected correctly and ACPI entries are generated for device 0d.0 Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/common: Include Meteor Lake device IDsWonkyu Kim2022-03-091-0/+87
| | | | | | | | | | Reference: chapter2 in Meteor Lake EDS vol1 (640228) Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62581 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src: Make PCI ID define names shorterFelix Singer2022-03-071-4122/+4122
| | | | | | | | | | | | | | | | | | Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/amd/sabrina: Add XHCI configurationJon Murphy2022-02-281-0/+1
| | | | | | | | | | | | | | Add xhci 2 controller support for additional USB port/ Dummy setting BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/alderlake: Correct Alder Lake M/N ESPI device IDKrishna Prasad Bhat2022-02-161-1/+1
| | | | | | | | | | | | | Alder Lake M/N ESPI ID 18 was incorrectly assigned to be 0x5482. Assign it to the correct value. Reference documents: 619501, 645548. Change-Id: I08bd218fd128497825b96aa5b9496826afa620d2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61947 Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-NUsha P2022-02-111-61/+61
| | | | | | | | | | | | | | | Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M IDs in the current code. Hence rename those device IDs as ADL_M_N and use them for Alder Lake-N platform. Document Number: 619501, 645548 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/intel/common: Add Crash Log and PMC SRAM PCI device IDsTim Wawrzynczak2022-02-101-4/+8
| | | | | | | | | | | | | Add Alder Lake and Tiger Lake specific Crash Log and PMC SRAM device IDs. Document Number: 619501, 645548 Change-Id: I64b58b8c345bd54774c4dab7b65258714cd8dc9e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/intel/alderlake: Add Alder Lake P IGD device IDsKane Chen2022-01-311-0/+3
| | | | | | | | | | | | | | This patch adds additional IGD device IDs as per document 638514. BUG=b:216420554 TEST=coreboot is able to probe the IGD device during PCI enumeration. Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61441 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Include Alder Lake-N device IDsUsha P2022-01-251-0/+12
| | | | | | | | | | | | Add Alder Lake-N System Agent, PCIE, UFS, IPU and CNVI device IDs. Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0a383816f818b794cf1211766c27937b3b8daa31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/intel/common: Add Alder Lake N eMMC device IDKrishna Prasad Bhat2022-01-181-0/+1
| | | | | | | | | | | | | | Add eMMC device ID for Alder Lake N SOC. Reference: Alder Lake N Platform EDS Volume 1 (Doc# 645548) Change-Id: Id35ec2d508bec8ff7d6f1c5fbfaf209d42b25c72 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* pci_ids.h: Make Denverton IDs consistent with other Intel SoCsJeff Daly2022-01-171-32/+32
| | | | | | | | | | | Align Denverton PCI ID define names with other Intel SoCs. Also, update the names in SoC code accordingly. Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* include/device/pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoCFelix Held2022-01-121-0/+16
| | | | | | | | | | | | The PCI IDs of the ACP (audio co-processor), the non-GPU HDA audio, the SMBus and the LPC devices haven't changed from the previous generations of Zen-based APUs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I41e0a57671b9ef2938b7798d5826de43bea8fe12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/intel/alderlake: Update the ADL-P SKU parameters for VR domainsCurtis Chen2022-01-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | We support all the ADL-P 15W/28W/45W SKU's and map them with the latest VR configurations. These config values are generated by iPDG application with ADL-P platform package tool. RDC Kit ID for the iPDG tools * Intel(R) Platform Design Studio Installer: 610905 * Intel(R) Platform Design Studio - Libraries: 613643 * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345 * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261 BUG=b:211365920 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen@intel.com> Change-Id: Ida7a6df0422a9a3972646cb3bdd0112b5efa2755 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* drivers/net/r8168: Add support for Realtek RT8125Alan Huang2021-12-031-0/+2
| | | | | | | | | | | | | | | | The Realtek RT8168 and RT8125 have a similar programming interface, therefore add the PCI device ID for the RT8125 into driver for support. BUG=b:193750191 TEST=emerge-brask coreboot chromeos-bootimage. Test on brask whose NIC is RT8125. Check if the default MAC is written into the NIC. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: Iaa4c41f94fd6e5fd6393abbb30bfc22a149f5d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Include Alder Lake-N device IDsUsha P2021-11-291-0/+7
| | | | | | | | | | | | | Add Alder Lake-N specific CPU, System Agent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 645548 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* soc/intel/elkhartlake: Update SA DIDs TableRick Lee2021-11-251-0/+2
| | | | | | | | | | | | | Update SA table as per latest EDS (Doc no: 601458). Add extra SKUs accordingly. Signed-off-by: Rick Lee <rick.lee@intel.com> Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
* drivers/genesyslogic/gl9750: Add driver for Genesys Logic GL9750Ben Chuang2021-11-231-1/+2
| | | | | | | | | | | | | | | | | The device is a PCIe Gen1 to SD 3.0 card reader controller to be used in the Chromebook. The datasheet name is GL9750S and the revision is 01. The patch disables ASPM L0s. BUG=b:206014046 TEST=Verify GL9750 enters L1 by observing CLKREQ# de-asserts. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDsTracy Wu2021-11-121-0/+4
| | | | | | | | | | | | | | | | | List of changes: 1. Add PEG60/10/62 IDs (0x464d/0x460d/0x463d) into device/pci_ids.h 2. Add these new IDs into pcie_device_ids[] in pcie.c BUG=b:205668996 TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDsFelix Held2021-11-021-2/+0
| | | | | | | | | | | | | | | | PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS redefine the same values that are already defined by PCI_DEVICE_ID_AMD_CZ_LPC and PCI_DEVICE_ID_AMD_CZ_SMBUS, so drop PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS. Also add some comments to the places in the code where the defines are used to clarify which ID is used on which hardware generation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Reviewed-on: https://review.coreboot.org/c/coreboot/+/58696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* include/device/pci_ids: move AMD device IDs below AMD vendor IDFelix Held2021-10-261-132/+134
| | | | | | | | | | | | | Half of the AMD PCI device ID definitions were below the ATI vendor ID, so move those below the AMD PCI vendor ID definition. The entries are kept in the order they were before and added before the existing AMD device ID definitions below the AMD vendor ID definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I34ffdc49884737541b8653bebf023a68050375d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* include/device/pci_ids: fix typo in PCI_DEVICE_ID_AMD_FE_GATE_700DFelix Held2021-10-261-1/+1
| | | | | | | | | | | The definitions isn't used in either spelling. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6faea2b9c89f0bd3c164a6dc76fac5ea712d313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/alderlake: Add GFx Device ID 0x46c3Selma Bensaid2021-09-291-0/+1
| | | | | | | | | | | | This CL adds support for new ADL-M graphics Device ID 0x46c3. TEST=boot to OS Change-Id: Ib55fb501f96fe9bcc328202511bbfe84a3122285 Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/adl: Update PCI ID for ADL-M SKUSumeet Pawnikar2021-08-201-1/+1
| | | | | | | | | | | | | | Update PCI ID for ADL-M as per document 643775. BUG=None BRANCH=None Change-Id: Ia2c5ce270bc421d8a41cc4bc6ce0b51987d2aaec Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Add TGL-H PCI IDsJeremy Soller2021-08-191-0/+79
| | | | | | | | | | | | | | | Add TGL-H PCI IDs from the Processor and PCH EDS docs. Reference: - Intel doc 615985 - Intel doc 575683 Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Add GFx Device ID 0x46aaBora Guvendik2021-08-051-0/+1
| | | | | | | | | | | | | This CL adds support for new ADL-M graphics Device ID 0x46aa. TEST=boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib24b494b0eedad447f3b2a3d1d80c9941680c25d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Add support for I2C6 and I2C7Varshit B Pandya2021-07-201-0/+2
| | | | | | | | | | | | As per the EDS revision 1.3 add support for I2C6 and I2C7. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id918d55e48b91993af9de8381995917aef55edc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/graphics: add GPU PCI ID for BarceloFelix Held2021-07-171-1/+2
| | | | | | | | | | | | | | | | Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify that that is the one for Cezanne. BUG=b:193888172 Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Add GFx Device ID 0x46a6Maulik V Vaghela2021-07-141-0/+1
| | | | | | | | | | | | | | This CL adds support for new ADL graphics Device ID 0x46a6. TEST=Build and boot Adlrvp board Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56026 Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Add GFx Device ID 0x46b3Meera Ravindranath2021-06-211-0/+1
| | | | | | | | | | | | | | | | | List of changes: 1. Add new GFx ID 0x46B3 into device/pci_ids.h 2. Update new GFx ID into common graphics.c 3. Add new GFx ID description into report_platform.c TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I4343c7343875eb40c2955f6f4dd98d6446852dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* soc/intel: Add Alder Lake's GT device IDSridhar Siricilla2021-06-081-0/+1
| | | | | | | | | | | | | | | | Add Alder Lake specific graphics device ID. The document# 641765 lists the id 0x46a8. TEST=Verify boot on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6f36256505a3e07c6197079ea2013991e841401b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55256 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Update SA & IGD DIDs TableTan, Lean Sheng2021-05-261-12/+16
| | | | | | | | | | | | Update SA & IGD DIDs table as per latest EDS (Doc no: 601458). Add extra SKUs and fix the mismatched SKU numbers accordingly. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I62fd9e6a7cf0fc6f541f3d6d9edd31d41db7279f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* soc/intel/common: Add Alder Lake device IDsSumeet R Pawnikar2021-05-211-1/+4
| | | | | | | | | | | | | Add Alder Lake specific Host and Graphics device IDs. As per latest document number: 619501, these IDs got an update. Change-Id: I548a903714ccc7470f1425ac67c0c66522437365 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54674 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela2021-05-141-0/+1
| | | | | | | | | | | | | | Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel: Add Z370, H310C and B365 device IDsAngel Pons2021-04-281-0/+3
| | | | | | | | | | | | | | | Intel document 335192-004 contains the PCI device IDs for Z370 and H310C, but lacks the ID for B365. The ID appears on some websites: https://linux-hardware.org/index.php?id=pci:8086-a2cc-1849-a2cc Change-Id: Iea3c435713c46854c5271fbc266f47ba4573db52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52703 Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Add Kaby Lake PCH-U base device IDAngel Pons2021-04-281-0/+1
| | | | | | | | | | | | | | Taken from Intel document 334658-003 (7th Generation Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel Processor Family I/O for U Quad Core Platforms, Datasheet - Volume 1 of 2). Change-Id: I1d48c8868e1e5d453d599ecec835938ce09935d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52702 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Rename 200-series PCH device IDsAngel Pons2021-04-281-41/+41
| | | | | | | | | | | | | | | | | The code name for these PCHs is Union Point, abbreviated as `UPT`. There are some 300-series Union Point PCHs (H310C, B365, Z370) which are meant to be paired with Coffee Lake CPUs instead of Skylake or Kaby Lake CPUs, and referring to them as `KBP` (Kaby Point, I guess) would be confusing. Tested with BUILD_TIMELESS=1, HP 280 G2 remains identical. Change-Id: I1a49115ae7ac37e76ce8d440910fb59926f34fac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52700 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake MMaulik V Vaghela2021-04-061-0/+2
| | | | | | | | | | | | | | Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c TEST=Check if platform information print is coming properly in coreboot Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block: Add PCI IDs for EmmitsBurg PCHJonathan Zhang2021-03-111-0/+3
| | | | | | | | | | | | | | | | | According to Intel EmmitsBurg EDS, doc# 606161: * Add PCI devid for SPI. * Add PCI devid for ESPI (LPC). EmmitsBurg (EBG) PCH is used in the chipset with Sapphire Rapids Scalable Processor (SPR-SP). Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ie8925cb739c95c34febf9002149de437d19c8234 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/broadwell/pch: Use Lynx Point smbus.cAngel Pons2021-03-051-0/+1
| | | | | | | | | | | | Continue unifying Lynx Point and Wildcat Point (PCH for Broadwell) code. Define the WPT-LP SMBus PCI device ID, add it to smbus.c of Lynx Point, and drop all now-unnecessary SMBus code from Broadwell. Change-Id: I864d7c2dd47895a3c559e2f1219425cda9fd0c17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* sb/intel/ibexpeak: Add all PCI IDs for LPCAngel Pons2021-02-271-0/+10
| | | | | | | | | | | | | | | Taken from document 322170-028 (5 series specification update). Tested on out-of-tree HP ProBook 6550b (HM57), fixes several issues. Without this patch, EHCI controllers had no IRQ assigned and there were unexpected exceptions about NMIs. With this patch, the issues are gone. Change-Id: Icd31dd89ba49e38a5e4c108a8361dbf636332ab8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51066 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/data_fabric: add missing data fabric device function 7Felix Held2021-02-241-0/+1
| | | | | | | | | | | | The device function is missing in the PCI device table in the PPR, but is present in the hardware. Verified on a Mandolin board with PCO APU. The corresponding ticket for the PPR is DESPCSOC-6667. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie91438bc905691d443ca4e7841549d1e3bca39ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/51041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-28 19:35:30 +0000