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* mb/siemens/mc_ehl3: Add PTN3460 eDP-to-LVDS bridgeJan Samek2023-01-204-1/+100
| | | | | | | | | | | | | | | | | | | | This board contains in addition to its base variant, mc_ehl2, an LCD panel driven through the PTN3460 eDP-to-LVDS bridge. This patch enables the PTN3460 support by adding the device to devicetree.cb and board-specific configuration parameters in lcd_panel.c, based upon a similar implementation in siemens/mc_apl7. BUG=none TEST=Boot with the LCD panel attached and observe whether the picture is stable and free of artifacts coming from wrong resolution, timing etc. Change-Id: Ib8a1a6f47053406e42554c2dd33684165d54be08 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl3: Use device/mmio.h instead of device/pci_ops.hJan Samek2023-01-191-1/+1
| | | | | | | | | | | | | | | | | The {read,write}{16,32}() functions used in this file come from the mmio.h header, so include it directly. BUG=none TEST=Read out the SD card controller (device 1a.1) PCI registers in Linux and check whether the values reflect the ones defined in this file. Change-Id: Iff7b55ef2bf98371b7d7d9114ccf3ebed64772a2 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72009 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl: Remove '_' from mc_ehl3 part numberJan Samek2023-01-181-1/+1
| | | | | | | | | | | Change MAINBOARD_PART_NUMBER Kconfig value for mc_ehl3 from "MC_EHL3" to "MC EHL3". Change-Id: Ie548607c5fb62faaed4921af714bc9b912e558a8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71775 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard: Remove duplicated <soc/gpio.h>Elyes Haouas2023-01-132-2/+0
| | | | | | | | | | <gpio.h> chain-include <soc/gpio.h>. Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/siemens/mc_ehl1: Enable real-time tuningWerner Zeh2023-01-111-0/+3
| | | | | | | | | | | | Enable the real-time tuning to improve performance in the real-time environment for this mainboard. Change-Id: I91ad7ca58add92b5cc66148aff8378890ee217eb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71234 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl1: Limit SATA speed to Gen 2Werner Zeh2023-01-101-0/+1
| | | | | | | | | | | | | | Due to mainboard restrictions a SATA link at Gen 3 (6 Gbps) can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection. Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71230 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/siemens/mc_apl{4,7}: Limit I2C bus speed to 100 kHz on bus 7Werner Zeh2022-12-234-0/+35
| | | | | | | | | | | | | | | | | | Due to a high I2C bus load on the mainboard I2C frequency of 400 kHz leads to poor signaling. Therefore limit the I2C speed to 100 kHz for this bus. In addition, add a generic I2C device with 100 kHz bus speed to the devicetree so that the OS will not switch to higher clock rates, too. Test= Measure the I2C signals at coreboot and OS runtime and ensure the clock is always at 100 kHz. Change-Id: I6b0a642cd3f5b77331663ac8c76ed0a116ae77ca Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71227 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl3/devicetree.cb: Remove TSN GbE 0Jan Samek2022-12-211-16/+0
| | | | | | | | | | | Remove the PSE TSN GbE device #0 as it's unused on the board and not visible during the PCI enumeration. Change-Id: I4a7d0e437c4f4a12d3a07564cddeafb7c697c6d3 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70700 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl3/mainboard.c: Remove XIO2001 register tweaksJan Samek2022-12-211-12/+1
| | | | | | | | | | | | Contrary to mc_ehl2, which this variant is based on, this board doesn't contain the TI XIO2001 PCIe-to-PCI bridge, which makes the attempts to modify the bridge's registers unnecessary. Change-Id: I6597ceb78e4c790c08a0dfa9535dece33a8f95b8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70854 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl3/devicetree.cb: Adapt PCIe root port settingsJan Samek2022-12-171-8/+12
| | | | | | | | | | | | Based upon hardware differences from mc_ehl2, disable RP7 and enable RP3 and RP5. Change-Id: Iecaa3098c3e4c9ce15254bb8bd1fe6da86d6e706 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70689 Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl3: Add board variant based on mc_ehl2Jan Samek2022-12-178-0/+557
| | | | | | | | | | | | | | | | | Add a new mc_ehl variant, which is based on mc_ehl2 implementation. This patch uses a copy of mc_ehl2 with changes only in naming as a starting point for the new mc_ehl3 variant. Follow-up patches will introduce the functional changes against mc_ehl3. Change-Id: Ie8c18b4f16d88b175ce576c2ef4c2e6ee0b4c306 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas2022-12-101-1/+1
| | | | | | | | | | | | | <device/mmio.h>` chain-include `<arch/mmio.h>: https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes Also sort includes while on it. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/siemens/*/Makefile.inc: Remove path to non-existent folderElyes Haouas2022-12-092-2/+0
| | | | | | | | | | Found using 'Wmissing-include-dirs' command option. Change-Id: Ie9ff43432215ebc89e6c1ea5f86b248e7fecd943 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70396 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Disable GSPI2 controllerMario Scheithauer2022-12-011-2/+0
| | | | | | | | | | | | | GSPI2 interface is not used on this mainboard and can be disabled. It will in addition remove the warning of a leftover static device in the log. Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/siemens/mc_ehl2: Disable L1 prefetcherMario Scheithauer2022-11-251-0/+3
| | | | | | | | | | | | | | As for mainboard mc_ehl1, a hard real-time dependency is also required for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: I07b27dd672533e693a6c2987d16f54333850760e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Enable downshift for Marvell PHYsMario Scheithauer2022-11-241-0/+3
| | | | | | | | | | | Set downshift counter to 2 for all Marvell PHYs on this mainboard before the PHY downshifts to the next highest speed. Change-Id: I32b5f25a3e1e0f962dff3110143e236992ef8e7d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69887 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Enable Marvell PHY interruptMario Scheithauer2022-11-241-0/+6
| | | | | | | | | | | On this mainboard Marvell PHY INTn is routed to LED[2] pin. Change-Id: I28a78afdcf0599bb998f906ce8056a0586e24f33 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69434 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driverMario Scheithauer2022-11-242-3/+40
| | | | | | | | | | | | | | | | | | | | | This mainboard has three Marvel PHYs connected to the internal SOC GbE controllers. The default LED status after HW reset of this PHYs shows a different mode than what is needed. LED[2] is not connected on this mainboard. This patch sets the following LED status: LED[0] - 7 = On - 1000 Mbps Link, Off - Else LED[1] - 1 = On - Link, Blink - Activity, Off - No Link LED[2] - not connected TEST=Try different register values to verify LED feature. Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69387 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2/devicetree.cb: Use RV3028 bus_speed instead of dummy i2c ↵Jan Samek2022-11-181-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | device Instead of creating a dummy I2C device in order to force Linux to decrease the I2C bus speed, use the own 'bus_speed' field of RV3028 device config structure. Linux should always set the bus speed to the speed of the slowest device sitting on the bus. Hence the dummy device is not needed here anymore. BUG=none TEST=See if the RV3028 RTC is visible and working (date/time can be set/read) in Linux. At the time, a driver modification is needed to add a match table for the "MCRY3028" ACPI HID. A proper kernel patch is pending. Change-Id: I6e269dc67d1fe2a6747fcf3bee224def7b553f08 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69544 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/siemens/mc_ehl2: Provide I2C timing parameter for SSDTWerner Zeh2022-11-091-0/+12
| | | | | | | | | | | | | | | Provide timing parameter for SSDT generation to achieve the requested 100 kHz speed with a high accuracy. Test: Measure I2C bus clock, high and low times during I2C access from Linux and confirm they match the specification. Change-Id: Ifb6019421b612133b8f25c076519bc0e7200dad8 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/siemens/mc_ehl2: Add dummy I2C devices to limit the I2C speed in OSWerner Zeh2022-11-091-1/+14
| | | | | | | | | | | | | | | In Linux, the I2C speed defaults to 400 kHz if there is no device registered in ACPI which requests a different speed. Due to board limitations (layout, bus load), 400 kHz are too fast which results in a timing violation. Therefore, add a dummy I2C device to both used I2C buses (I2C1 and I2C2) with a speed of 100 kHz. This will limit the bus speed in Linux accordingly. Change-Id: I507c53c9ec7f763cef18903609231b1a66ed98fa Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/siemens/mc_ehl: Remove spd.bin from CBFSWerner Zeh2022-10-2910-172/+1
| | | | | | | | | | | | | The SPD data for DRAM init has moved into the hwinfo data structure and is therefore not used from spd.bin anymore. spd.bin will not receive any updates, changes will only be done in hwinfo. There is no reason to keep spd.bin around so remove it for both variants. Change-Id: Ie6091b655ba7ff2e01b684266ce34b85593b8623 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/siemens/mc_apl2: Enable early POST through NC_FPGAJan Samek2022-10-273-0/+28
| | | | | | | | | | | | | | | | | | Enable early POST code output for this mainboard, using the NC FPGA device on PCIe. This requires the parent PCI bridge to be initialized early. BUG=none TEST=boot on siemens/mc_apl2 and observe whether the POST codes coming from before FSP-M init are visible Change-Id: Ice5fe26e11d0513e6bb0a20f1d8f0483d7b3dc6a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl1: Disable L1 prefetcherWerner Zeh2022-10-251-0/+3
| | | | | | | | | | | | | | | The highly real time driven application executed on mc_ehl1 has shown that the L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68668 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* mb/siemens/mc_ehl: Add FIVR config to devicetree for all variantsWerner Zeh2022-10-222-0/+12
| | | | | | | | | | | | | Add a config for FIVR in devicetree for both, mc_ehl1 and mc_ehl2 variants in order to provide the real delay value for the VCC supply rail. This delay is needed to enable proper switching between different VCC levels based on current system state. Change-Id: Ibccb8ea1b42ccd2ff0a37cbd9651528a2a55ebd6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/siemens/mc_apl*: Enable early PCI bridge before FSP-MAngel Pons2022-10-221-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Apollo Lake seems to start with PCIe root ports unusable/uninitialized before FspMemoryInit() is called and FSP-M properly initializes these root ports. However, we need the root ports accessible before FspMemoryInit() in certain cases, such as emitting POST codes through a PCIe device. For the initialization to happen properly, certain register writes specified in Apollo Lake IAFW BIOS spec, vol. 2 (#559811), chapter 3.3.1 have to be done. BUG=none TEST=Boot on siemens/mc_apl2 with NC_FPGA_POST_CODE enabled and check that the POST codes are emitted before FspMemoryInit(). Change-Id: If782bfdd5f499dd47c085a0a16b4b15832bc040e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68223 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Use preset driver strength for SD-CardMario Scheithauer2022-10-071-0/+8
| | | | | | | | | | | The intention of predefining driver strength is to avoid that the OS SD-Card driver changes this setting. Change-Id: I02fdac94462da1cd77f8dc972faf16f28d94c946 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_apl7: Enable libgfxinit for the boardJan Samek2022-09-223-0/+17
| | | | | | | | | | | Add the gma-mainboard.ads for display output definition and enable the libgfxinit usage in mainboard Kconfig. Change-Id: I7e7a44736a8136b5320821e744134c7d64c7f1b4 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67683 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_apl7/Kconfig: Enable PTN3460 early initJan Samek2022-09-221-0/+4
| | | | | | | | | | | | | Enable early initialization of the PTN3460 DP-to-LVDS bridge on this board in order to allow showing the bootsplash screen at coreboot runtime. Change-Id: Ib1b727cef5fb8bea2d6d6c9896ad0107caeea51a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67682 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_apl1: Do not wait for legacy devices on mc_apl7Werner Zeh2022-09-191-1/+1
| | | | | | | | | | | | Since there are no legacy devices on the variant mc_apl7 do not wait for them on mc_apl7. Change-Id: Ia4e6c0fb495a347be51bd6604a1d9b73098fb7b6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67684 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Limit SD-Card speed modes to DDR50Werner Zeh2022-09-071-0/+24
| | | | | | | | | | | | | | Due to layout restrictions on mc_ehl2, the SD-card interface is limited to operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not supported. Limit the capabilities in the SD card controller to DDR50 mode only so that the SD card driver in OS will choose the right mode for operation even if the attached SD card supports higher modes. Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/siemens/mc_ehl2: Set I2C bus 1 speed to 100 kHzWerner Zeh2022-09-071-0/+3
| | | | | | | | | | | Since the new RTC is located in I2C bus 1 now, set the bus speed to 100 kHz as well. Change-Id: Ica9468e559bc654545592a9b4d23f3164eafca8a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67102 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Change to new RTC RV3028-C7Werner Zeh2022-09-072-10/+7
| | | | | | | | | | | | | | | | Since the latest redesign a new RTC was introduced on mc_ehl2. Instead of the old RX6110SA the new Micro Crystal RTC RV3028 is used now. Since the address of this new RTC conflicts with an EEPROM on I2C bus 2, the new RTC was moved to I2C bus 1. As the mainboard is not finished yet, there are no incompatibility issues with this change. Every new mainboard will have the new RTC and the older mainboards are not delivered yet. Change-Id: I3dd00855b8c9b22bdea21d3c8563cdb392868751 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* mb/siemens/mc_ehl: Move RTC Kconfig option to variant levelWerner Zeh2022-09-073-1/+2
| | | | | | | | | | | | With a redesign of mc_ehl2 the used RTC was changed. In order to be able to select a different RTC type for every variant move the RTC Kconfig switch into the variant's Kconfig file. Change-Id: Ia24703ede6a935e3b9886df87237857baec7d6a0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67100 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/**/dsdt.asl: Drop misleading "OEM revision" commentAngel Pons2022-08-163-3/+3
| | | | | | | | | | | | | | | | It is highly unlikely that the "OEM revision" of the DSDT is 0x20110725 on mainboards with a chipset not yet released on 2011-07-25. Since this comment is most likely to have been copy-pasted from other boards, drop it from boards which use a chipset newer than Sandy/Ivy Bridge. Change-Id: If2f61d09082806b461878a76b286204ae56bf0eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* mb/**/dsdt.asl: Drop superfluous commentsAngel Pons2022-08-162-8/+0
| | | | | | | | | | | | | | These comments don't add much value, so remove them. Change-Id: I7e9692e3fe82345cb7ddcb11c32841c69768cd36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66713 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* mb/siemens/mc_apl7: Disable VBOOT and TPMUwe Poeche2022-06-272-22/+2
| | | | | | | | | | | | | mc_apl7 does not use security features like VBOOT and TPM. Test: flash mc_apl4 mainboard and ensure the disabled features via log. Change-Id: I16683b92deb047208848b69c5aa79dc4212ce930 Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65284 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_apl1: Add new mainboard variant mc_apl7Uwe Poeche2022-06-238-0/+683
| | | | | | | | | | | | | | | | This patch adds a new mainboard variant called mc_apl7 which is based on mc_apl4. So far only the names have been adjusted with no further changes. Following commits will introduce the needed changes for this mainboard variant. Test: build mc_apl7, flash to mc_apl4 and compare log level 8 output Change-Id: Ie9f2f5c29d071de442f8f3e3eaf4b3c2a6b8920f Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65283 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: Hook Up SataPortEnable to devicetreeSean Rhodes2022-06-206-0/+12
| | | | | | | | | | | | Hook Up SataPortsEnable to the devicetree. As the default value is 0, set both [0] and [1] in all mainboards so they aren't affected. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Hook up FSP hyper-threading setting to option APIFelix Singer2022-05-261-2/+0
| | | | | | | | | | | | | | | | | | | | | Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting from the FSP to the option API so that related mainboards don't have to do that. Unless otherwise configured (e.g. the CMOS setting or overriden by the mainboard code), the value from the Kconfig setting `FSP_HYPERTHREADING` is used. Also, remove related code from the following mainboards, since it is obsolete now. * siemens/chili * starlabs/laptop/cml Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/siemens/mc_ehl: Disable RAPLUwe Poeche2022-05-231-0/+1
| | | | | | | | | | | | | | | Disable RAPL for all mainboards based on mc_ehl for stable real time mode of CPUs. Test: Boot mc_ehl1 with this patch and ensure the bits in the MCBAR register are cleared. Change-Id: Ie58a4b6444d5be088ac2b25ff0a2f5cd33120ace Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Invert PHY IRQ from falling edge to rising edgeMario Scheithauer2022-05-211-0/+3
| | | | | | | | | | | | There are three external Marvell PHY 88E1512 on this mainboard. The PHY IRQ comes with a falling edge but the EHL MAC side needs a rising edge signal. For that reason, we need an inversion of the IRQ polarity. Change-Id: Id3caf582b4434b046779f5733e6ad9b57528ce35 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Quick fix for PSE TSN phy interface typeLean Sheng Tan2022-05-201-2/+0
| | | | | | | | | | | | | Based on quick fix on this commit 7b0fe59be (soc/intel/ehl: Fix logical bug for PseTsnGbePhyInterfaceType), disable PSE TSN SGMII as the original intention is to set the PSE TSN phy interface as RGMII. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Id2e05b19f156621a945110791038bc0d19a0aad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* intel/common/block: Provide RAPL and min clock ratio switches in commonUwe Poeche2022-05-185-5/+5
| | | | | | | | | | | | | | | | | | There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mainboard/**/devicetree.cb: Fix typoAngel Pons2022-05-172-2/+2
| | | | | | | | | | | | | repalcement ---> replacement Change-Id: I486170e89f75fa7c01c7322bb8db783fd4f61931 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64404 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Enable SMBus depending on dev stateAngel Pons2022-05-172-2/+0
| | | | | | | | | | | | | Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's state in the devicetree. This avoids having to manually make sure the SMBus PCI device and the `SmbusEnable` setting are in sync. Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridgeMario Scheithauer2022-05-171-0/+8
| | | | | | | | | | | | On this mainboard there are legacy PCI devices connected behind a PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This patch disables the unused PCI clock outputs on the XIO2001 bridge. Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63931 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Enable TSN GbE driverMario Scheithauer2022-05-161-0/+1
| | | | | | | | | | | | | | | | This variant uses all three EHL Ethernet GbE-TSN Controller so enable the TSN GbE driver in order to set the needed MAC addresses. The required function to retrieve a valid MAC address was already implement in the common mainboard.c for mc_ehl. TEST: - Boot mc_ehl2 into Linux and check MAC addr via 'ip a' Change-Id: Ia052c44feb606f9e1d31d047f2acc67e3226a895 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Set PCH TSN link speed to 1 Gbps in devicetreeMario Scheithauer2022-05-161-1/+1
| | | | | | | | | | | TSN runs in SGMII mode on this mainboard. This requires setting the link speed to 1 Gbps. Change-Id: I9f1da971b4de5671d6d38be6dbc50edbbe20d157 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/siemens/mc_ehl2: Adjust PSE TSN settings in devicetreeMario Scheithauer2022-05-161-0/+4
| | | | | | | | | | | | | | | | | | | This mainboard uses all three internal Ethernet GbE-TSN controllers. Two of them are initialized by the Programmable Services Engine (PSE). This patch enables the Serial Gigabit Media Independent Interface (SGMII) mode for GbE PSE0 and GbE PSE1. By setting PCH PSE DMA pins to host owned, the IO is under control of the IA processor cores through system software. TEST: - Boot mc_ehl2 into Linux and check inet addr via 'ip a' Change-Id: I74e660548b2c44d5dbdb6023d5a36cfdd7e96f43 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-08 11:48:12 +0000