summaryrefslogtreecommitdiffstats
path: root/src/northbridge/intel
Commit message (Expand)AuthorAgeFilesLines
* nb/intel/haswell: Decouple mainboard USB config from MRCAngel Pons2021-03-253-19/+85
* nb/intel/haswell: Limit mainboard USB config array lengthsAngel Pons2021-03-232-4/+10
* nb/intel/haswell: Use unshifted SPD addresses in mainboardsAngel Pons2021-03-232-3/+6
* nb/intel/haswell: Confine `pei_data` uses to raminit.cAngel Pons2021-03-233-133/+127
* nb/intel/haswell: Consolidate memory-down SPD handlingAngel Pons2021-03-192-7/+43
* mb/google/slippy: Correct memory-down SPD handlingAngel Pons2021-03-191-4/+5
* sb/intel/lynxpoint: Move S3 check out of `early_pch_init`Angel Pons2021-03-151-12/+7
* sb/intel/lynxpoint: Replace HPET_ADDRAngel Pons2021-03-151-1/+1
* nb/intel/haswell: Finalize northbridge in ramstageAngel Pons2021-03-104-40/+33
* nb/intel/haswell/pcie.c: Add missing pre-ASPM initAngel Pons2021-03-103-0/+125
* nb/intel/haswell: Indent PCI ops with tabsAngel Pons2021-03-071-5/+5
* nb/intel/sandybridge: Clean up `dram_timing` functionAngel Pons2021-03-011-27/+11
* nb/intel/haswell: Fix DPR size handlingTim Wawrzynczak2021-03-011-2/+2
* nb/intel/sandybridge: Ensure tXP and tXPDLL do not overflowAngel Pons2021-03-011-3/+4
* memory_info.h: Store SMBIOS error correction typeAngel Pons2021-03-012-6/+6
* nb/intel/ironlake: Avoid casting pointers to structsAngel Pons2021-02-271-14/+16
* nb/intel/ironlake: Handle broken ME firmwareAngel Pons2021-02-271-3/+5
* nb/intel/ironlake: Rewrite early QPI initAngel Pons2021-02-243-68/+102
* nb/intel/haswell/northbridge.c: Correct DPR handlingAngel Pons2021-02-241-14/+11
* nb/intel/ironlake: Correct even more replay issuesAngel Pons2021-02-241-7/+10
* nb/intel/ironlake: Relocate early QuickPath initAngel Pons2021-02-243-103/+107
* nb/intel/ironlake: Deduplicate programming 274/265 valuesAngel Pons2021-02-241-30/+16
* nb/intel/ironlake: Split out some QuickPath init codeAngel Pons2021-02-244-737/+755
* nb/intel/ironlake: Remove unnecessary declarationAngel Pons2021-02-241-4/+0
* nb/intel/ironlake: Fix more replay issuesAngel Pons2021-02-241-24/+33
* nb/intel/ironlake: Fix some replay issuesAngel Pons2021-02-241-47/+64
* nb/intel/ironlake: Correct `set_4cf`Angel Pons2021-02-241-15/+16
* device/device.c: Rename .disable to .vga_disableArthur Heymans2021-02-243-3/+3
* nb/intel/haswell/pcie.c: remove disable NOPArthur Heymans2021-02-241-7/+0
* nb/intel/sandybridge/pcie.c: remove disable NOPArthur Heymans2021-02-241-7/+0
* nb/intel/ironlake: Drop redundant clear of SLP_TYPKyösti Mälkki2021-02-232-15/+0
* nb/intel/x4x: Use a variable for s3resumeKyösti Mälkki2021-02-231-2/+5
* nb/intel/x4x,sandybridge: Move INITRAM timestampsKyösti Mälkki2021-02-234-7/+7
* nb/intel/x4x,sandybridge: Move romstage_handoff_init() callKyösti Mälkki2021-02-236-17/+12
* nb/intel/haswell: Use cbmem_recovery()Kyösti Mälkki2021-02-231-14/+15
* nb/intel/sandybridge: Remove stale FIXME about ECC supportAngel Pons2021-02-221-1/+0
* nb/intel/ironlake: Do not call `collect_system_info` twiceAngel Pons2021-02-221-15/+7
* nb/intel/pineview: Drop unused `GPIO32` macroAngel Pons2021-02-181-2/+0
* nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400Angel Pons2021-02-181-1/+1
* nb/intel/sandybridge: Clean up `dram_freq` functionAngel Pons2021-02-181-10/+10
* nb/intel/haswell: Drop incorrect MMIO_PAVP_MSG writeAngel Pons2021-02-181-3/+0
* nb/intel/i945: Use UPMC4 macroElyes HAOUAS2021-02-161-2/+2
* nb/intel: Add missing <types.h>Elyes HAOUAS2021-02-166-5/+8
* nb/intel: Remove unused <string.h>Elyes HAOUAS2021-02-162-2/+0
* nb/intel/sandybridge: Fix description of auto-precharge bitAngel Pons2021-02-162-2/+2
* vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki2021-02-162-6/+0
* nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki2021-02-164-8/+6
* nb/intel/sandybridge,haswell: Use chromeos_reserve_ram_oops()Kyösti Mälkki2021-02-164-20/+7
* nb/i945/raminit.c: Don't hard code 'bool integrated_graphics'Elyes HAOUAS2021-02-161-0/+3
* src: use ARRAY_SIZE where possiblePatrick Georgi2021-02-152-3/+2
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 10:54:47 +0000