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path:
root
/
src
/
soc
/
intel
/
alderlake
/
chipset.cb
Commit message (
Expand
)
Author
Age
Files
Lines
*
soc/intel/alderlake: RPL-P power limits and VR settings
Jeremy Compostella
2022-07-04
1
-0
/
+18
*
soc/intel/alderlake: add power limits for Alder Lake-N SKUs
Vidya Gopalakrishnan
2022-06-02
1
-0
/
+18
*
soc/intel/alderlake: Add support for UFS controller
Meera Ravindranath
2022-04-13
1
-0
/
+1
*
soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config
Subrata Banik
2022-01-25
1
-1
/
+1
*
soc/intel/alderlake: Add ADL-P 2+8+2 (28W) VR config
Curtis Chen
2022-01-21
1
-1
/
+1
*
soc/intel/alderlake: Add eMMC device into chipset.cb
Krishna Prasad Bhat
2022-01-18
1
-0
/
+2
*
soc/intel/alderlake: Update the ADL-P SKU parameters for VR domains
Curtis Chen
2022-01-10
1
-15
/
+9
*
soc/intel/alderlake: Add ADLP 4+4+2 power configurations
Curtis Chen
2021-11-25
1
-1
/
+7
*
soc/intel/alderlake: Set `pch_thermal_trip` for Dynamic Thermal Shutdown
Subrata Banik
2021-11-20
1
-0
/
+5
*
soc/intel/alderlake: add power limits for Alder Lake-M 282 SKU
Sumeet Pawnikar
2021-10-01
1
-1
/
+6
*
soc/intel/alderlake: Add ADLP 242 power configurations
Tracy Wu
2021-09-29
1
-0
/
+5
*
soc/intel/alderlake: set power limits dynamically for thermal
Sumeet Pawnikar
2021-09-03
1
-5
/
+11
*
soc/intel/adl: Update power limits for ADL-M SKU
Sumeet Pawnikar
2021-08-20
1
-0
/
+6
*
soc/intel/alderlake: set default PL4 values for different SKUs
Sumeet Pawnikar
2021-08-19
1
-0
/
+4
*
mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cb
MAULIK V VAGHELA
2021-08-10
1
-0
/
+2
*
soc/intel/alderlake: Add support for I2C6 and I2C7
Varshit B Pandya
2021-07-20
1
-0
/
+2
*
soc/intel/alderlake: Correct Bus and Device of Touch Host Controller
Varshit B Pandya
2021-07-05
1
-2
/
+2
*
soc/intel/adl: Add SKU specific power limits support
Sumeet Pawnikar
2021-06-07
1
-0
/
+21
*
soc/intel/alderlake: Add IDE-R and KT device into chipset.cb
Subrata Banik
2021-06-05
1
-0
/
+2
*
soc/intel/alderlake: Add CrashLog implementation for Intel ADL
Francois Toguo
2021-05-06
1
-1
/
+1
*
soc/intel/alderlake: Remove obsolete CNVi Bluetooth PCI device
Cliff Huang
2021-03-15
1
-1
/
+0
*
soc/intel/adl, mb/google/brya: Add IPU to devicetree
Tim Wawrzynczak
2021-03-05
1
-0
/
+1
*
soc/intel: hook up new gpio device in the soc chips
Michael Niewöhner
2020-12-30
1
-0
/
+1
*
soc/intel/alderlake: Update chipset.cb for TCSS and USB
Eric Lai
2020-12-29
1
-6
/
+92
*
soc/intel/alderlake: Align chipset.cb with pci_devs.h
Eric Lai
2020-12-04
1
-8
/
+9
*
soc/intel/alderlake: Add initial chipset.cb
Tim Wawrzynczak
2020-11-30
1
-0
/
+67