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path: root/src/soc/intel/baytrail/ramstage.c
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* device: Use pcidev_on_root()Kyösti Mälkki2019-01-061-1/+1
* src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-111-1/+1
* soc/intel/baytrail: Get rid of device_tElyes HAOUAS2018-05-241-1/+1
* baytrail: add C0 and D0 stepping decodeBen Gardner2015-11-211-2/+5
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-1/+1
* baytrail: add code for supporting 2x ddr refresh rateKane Chen2015-04-101-0/+13
* baytrail: Change all SoC headers to <soc/headername.h> systemJulius Werner2015-04-071-8/+8
* ACPI: Get S3 resume state from romstage_handoffKyösti Mälkki2015-03-101-20/+6
* baytrail/rambi: S3 support and other updatesKein Yuan2014-10-221-4/+4
* rambi/baytrail: ACPI, GPIO, audio, misc updatesShawn Nematbakhsh2014-09-181-2/+36
* baytrail: note S3 resume status earlierAaron Durbin2014-05-101-3/+3
* baytrail: initialize common SSC functionalityAaron Durbin2014-05-071-0/+2
* baytrail: Add BCLK and IACORE to pattrsDuncan Laurie2014-05-061-2/+19
* baytrail: add GNVS to cbmem and set acpi_slp_typeAaron Durbin2014-02-271-2/+34
* baytrail: add support to run reference code blobAaron Durbin2014-02-171-0/+3
* baytrail: allow downstream use of SSE instructionsAaron Durbin2014-02-131-0/+4
* baytrail: Add GPIO initial configuration infrastructure.Shawn Nematbakhsh2014-02-031-0/+8
* baytrail: introduce pattrsAaron Durbin2014-01-311-0/+107