coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	baytrail: add code for supporting 2x ddr refresh rate	Kane Chen	2015-04-10	1	-0/+13
*	baytrail: Change all SoC headers to <soc/headername.h> system	Julius Werner	2015-04-07	1	-8/+8
*	ACPI: Get S3 resume state from romstage_handoff	Kyösti Mälkki	2015-03-10	1	-20/+6
*	baytrail/rambi: S3 support and other updates	Kein Yuan	2014-10-22	1	-4/+4
*	rambi/baytrail: ACPI, GPIO, audio, misc updates	Shawn Nematbakhsh	2014-09-18	1	-2/+36
*	baytrail: note S3 resume status earlier	Aaron Durbin	2014-05-10	1	-3/+3
*	baytrail: initialize common SSC functionality	Aaron Durbin	2014-05-07	1	-0/+2
*	baytrail: Add BCLK and IACORE to pattrs	Duncan Laurie	2014-05-06	1	-2/+19
*	baytrail: add GNVS to cbmem and set acpi_slp_type	Aaron Durbin	2014-02-27	1	-2/+34
*	baytrail: add support to run reference code blob	Aaron Durbin	2014-02-17	1	-0/+3
*	baytrail: allow downstream use of SSE instructions	Aaron Durbin	2014-02-13	1	-0/+4
*	baytrail: Add GPIO initial configuration infrastructure.	Shawn Nematbakhsh	2014-02-03	1	-0/+8
*	baytrail: introduce pattrs	Aaron Durbin	2014-01-31	1	-0/+107