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* soc/intel/cse: Remove unused header fileKrishna Prasad Bhat2023-10-131-1/+0
| | | | | | | | | | | | Systemagent related functions are not used in this file. Remove the unused the header file. Change-Id: Ifbb04898e9dcebef96d8c73771e66e0d6fabc7fb Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78312 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cse: Add entries to eventlog on PSR backup eventsKrishna Prasad Bhat2023-10-041-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds eventlog entries for the below scenarios: 1. To indicate success or failure of PSR data back-up command 2. To indicate the loss of PSR data when CSE update is corrupted, and data clear command is issued to clear the data. 3. To indicate the loss of PSR data when CSE boot partition info response is corrupted and data back-up is not initiated. BRANCH=None BUG=b:273207144 TEST=Verify elog event added after PSR data backup command is sent cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent ... ELOG: Event(B9) added with size 10 at 2023-06-27 06:44:49 UTC Change-Id: I2459a2b941d28a87b6c78f75dbe8779d73328d7a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/cse: Check PSR bit before issuing PSR backup commandAnil Kumar2023-10-041-0/+32
| | | | | | | | | | | | | | | | | | Get PSR bit state using MKHI_FWCAPS_GET_FW_FEATURE_STATE HECI command Use this bit info to check if SKU supports PSR and consequently issue PSR_HECI_FW_DOWNGRADE_BACKUP command for PSR data backup during downgrade. BUG=b:273207144 TEST=build CB image and boot on google/rex board. Check for "PSR is supported in this SKU" message in coreboot logs to confirm that PSR bit is set in SKU Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/cse: Back up PSR data during CSE FW downgradeAnil Kumar2023-10-041-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During CSE FW downgrade we erase CSE data. This would result in Platform Service Record(PSR) data also to be erased. To avoid losing PSR data we need to make a backup before data clear. This patch sends PSR_HECI_FW_DOWNGRADE_BACKUP HECI command to CSE, informing the CSE to backup PSR data before a data clear operation during downgrade. CMOS memory is used to track the backup status. PENDING is the default state, it is updated to DONE once PSR_HECI_FW_DOWNGRADE_BACKUP HECI command is sent. PSR data can be backed up only post DRAM is initialized. The idea is to perform cse_fw_sync actions in ramstage when PSR is enabled on a platform. As part of the cse_fw_sync actions, when a firmware downgrade is requested the command to back-up data is sent. Once the backup has been done, trigger the firmware downgrade. BRANCH=None BUG=b:273207144 TEST=build CB image for google/rex board and check PSR backup command is being sent during a CSE FW downgrade. Also check PSR data is not lost/erased after a downgrade using intel PSR tool. Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74577 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cse: Implement APIs to access PSR backup status in CMOSKrishna Prasad Bhat2023-10-042-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data. Since firmware downgrade and PSR data backup flows involve global resets, there is a need to track the PSR data backup status across resets. So adding a CMOS variable for the same. This patch implements API to access PSR backup status stored in CMOS. The get API allows to retrieve the PSR backup status from CMOS memory. The update API allows to update the PSR backup status in CMOS. BRANCH=None BUG=b:273207144 TEST=Able to retrieve PSR backup status across resets. Change-Id: I270894e3e08dd50ca88e5402b59c211d7e693d14 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/cse: Add function to get cse_bp_info earlyKrishna Prasad Bhat2023-10-041-1/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data, and this command can be sent only in post-RAM stages. So the cse_fw_sync actions needs to be moved to ramstage. Sending cse_get_bp_info command in ramstage takes additional boot time of ~45-55ms on rex. To avoid the boot time penalty, this patch provides an API to get the cse_bp_info in early romstage. The response data is then migrated to cbmem once memory is initialized. The same data in cbmem can be utilized in ramstage to perform other cse_fw_sync actions. This patch also adds check to validate cse_bp_info in cbmem and avoids sending the command again if the data is valid. BUG=b:273207144 TEST=Verify the command works in early romstage, data is migrated to cbmem and valid data is available in ramstage on rex. Change-Id: Ib1e72c950ba0f4911924805f501ec1bd54b6ba3c Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78053 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cse: Select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE when PSR enabledKrishna Prasad Bhat2023-09-281-1/+5
| | | | | | | | | | | | | | | | | | | | | | | PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. The PSR data needs to be preserved across the firmware downgrade flow. CSE Lite SKU firmware supports command to backup PSR data, and this command can be sent only in post-RAM stages. So the cse_fw_sync actions needs to be moved to ramstage. This patch ensures SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE is selected when PSR is enabled. BUG=b:273207144 Change-Id: I7c9bf8b8606cf68ec798ff35129e92cd60bbb137 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78055 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cse: Move cse_store_rw_fw_version from cse_print_boot_partition_infoKrishna P Bhat D2023-09-231-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | cse_store_rw_fw_version() stores CSE RW firmware version in global variable or cbmem in romstage and ramstage respectively, based on the stage it is called in. The call to this function is from the cse_print_boot_partition_info() in cse_get_bp_info. In the subsequent patches, the idea is to send the cse_get_bp_info early in romstage and store in cbmem once memory is initialized. So when the cse_fw_sync is called in early ramstage, the stored cse_bp_info_rsp is used instead of sending the CSE get boot partition info command again. To de-link the call to cse_store_rw_fw_version from cse_get_bp_info and to ensure the CSE RW FW version is stored in all cases, moving the function to do_cse_fw_sync. BUG=b:273207144 Change-Id: I0add2c167c85cbddef2ecb4c019061a08562bbdf Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
* soc/intel/cse: Make cse_bp_info response globalKrishna Prasad Bhat2023-09-231-82/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. CSE Lite SKU firmware supports a command to backup PSR data before initiating a firmware downgrade. PSR data backup command works only after memory has been initialized. Moving only the downgrade would add complexity of splitting the cse_fw_sync across pre-RAM and post-RAM stages. So the idea is to move cse_fw_sync into ramstage when PSR is enabled. We are introducing a flow to get CSE boot partition info in early romstage and then same data will be stored in cbmem once DRAM is initialized. The CSE BP info data in cbmem will be utilized in early ramstage to perform cse firmware sync operations. This helps in avoiding re-sending the CSE get boot partition info command in ramstage. Having cse_bp_info_rsp as global helps in de-linking cse_get_bp_info from cse_fw_sync. Many functions take cse_bp_info as input parameter. Since cse_bp_info_rsp is global now, we can make use of global cse_bp_info and remove it as input parameter from those functions. BUG=b:273207144 TEST=Verify cse_bp_info_rsp holds value across the stage. Change-Id: I0ee050b49fcae574882378b94329c36a228e6815 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77070 Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
* Revert "soc/intel/common/block/cse/Kconfig: Remove unused symbols"Reka Norman2023-09-221-0/+38
| | | | | | | | | | | | | | | | This reverts commit 06cb756f0202d78d299b30728b6559f6107c43c3. Reason for revert: These Kconfigs are needed by boards which use the CSE stitching tools (i.e. select STITCH_ME_BIN). They're selected by some boards in the downstream ChromeOS repo. They're used in src/soc/intel/Makefile.inc (see the line with `$(CONFIG_CSE_$(2)_FILE)`). Change-Id: Ide6fc74b457439f06b7ef9b37f11d6c9ff226b80 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76719 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold bootDinesh Gehlot2023-09-151-45/+146
| | | | | | | | | | | | | | | | | | | | This patch addresses the increased boot time issue that occurs when ISH store is enabled, such as in the "rex4es_ec_ish" variant. During a cold reboot, the CBMEM memory resets and loses the stored firmware versions. This causes the firmware versions to be fetched again from the CSE, which increases the boot time by about 200 ms. This patch stores a backup of the firmware version in CMOS and updates the CBMEM memory during a cold reboot. BUG=b:280722061 Test=Verified the changes on rex board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75755 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmd/blk/cse: Implement APIs to access CMOS CSE FPT versionsDinesh Gehlot2023-09-154-0/+77
| | | | | | | | | | | | | | | | | This patch implements APIs to access the CSE FW partition versions in CMOS. The get API allows users to retrieve the current version from CMOS memory. The set API allows users to set the version in CMOS memory. BUG=b:280722061 TEST=APIs verified on rex board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* chromeos/cse_board_reset.c: Clear EC AP_IDLE flagDerek Huang2023-09-141-0/+8
| | | | | | | | | | | | | | | | | | | | | | When CSE jumps between RO and RW, it triggers global reset so the AP goes down to S5 and back to S0. For Chromebox, when AP goes down to S5 EC set AP_IDLE flag. This cause an issue to warm reset the Chromebox device when it is in recovery mode and powered by USB-C adapter. This patch allows AP to direct EC to clear AP_IDLE flag before trigger reset. BUG=b:296173534 BRANCH=firmware-dedede-136-6.B TEST=Chromebox DUT which is powered by USB-C adapter boots up after warm reset in recovery mode Change-Id: Ib0002c1b8313c6f25d2b8767c60639aed8a4f904 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77632 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
* {driver, soc/intel/cmn/cse}: Refactor ISH FW Version implementationSubrata Banik2023-08-181-4/+8
| | | | | | | | | | | | | | | | | | | | This patch uses the CSE firmware specific data to store Intel ISH firmware related information. Sending an ISH partition version information command on every boot cycle would impact the overall boot performance. This information is used by the auto-test framework to ensure the ISH firmware update is proper for in-field devices. BUG=b:285405031 TEST=Able to build and boot google/rex. Verified ISH FW version is getting displayed across warm resets without impacting the boot time. Change-Id: I0242c26dd90d834815799f54740d8147ff9d45b7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/intel/cmn/cse: Display CSE RW FW version by default for LITE SKUSubrata Banik2023-08-181-1/+1
| | | | | | | | | | | | | | | | | | | This patch selects SOC_INTEL_STORE_CSE_FW_VERSION config by default for CSE LITE SKU. It helps to dump the CSE RW firmware version which further consumed by auto-test infrastructure to ensure CSE RW firmware update is successful. BUG=b:285405031 TEST=Able to build and boot google/rex. Verified CSE RW FW version (for LITE SKU) is getting displayed without impacting the boot time. Change-Id: Iba5903c73c0a45b01e6473714e0d5f759c061825 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77175 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/cmn/cse: Refactor CSE RW FW Version implementationSubrata Banik2023-08-182-29/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a CSE firmware specific data in order to store Intel CSE and associated firmware related information which requires a sync between Pre-RAM and Post-RAM phase. This information will be used further to retrieve currently running CSE RW firmware instead of fetching the version information by sending a HECI cmd (which consumes 7ms-15ms depending upon the CSE operational state). Current implementation attempts to simply the CSE RW FW version store and retrieval operations as below * CSE sync in romstage (aka Pre-RAM) - Relying on .bss segment to store the CSE info data in absence of real physical memory and sync back into the CBMEM once available (after FSP-M exits). * CSE sync in ramstage (aka Post-RAM) - Directly stored the CSE RW version into the CBMEM (as CBMEM is online). BUG=b:285405031 TEST=Able to build and boot google/rex. Verified CSE RW FW version (for LITE SKU) is getting displayed without impacting the boot time. w/o this patch: 10:start of ramstage         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) w/ this patch: 10:start of ramstage                         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) Change-Id: Ia873af512851a682cf1fac0e128d842562a316ab Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77174 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* soc/intel/cse: Add config to enable PSR data backup for CSE Lite SKUKrishna Prasad Bhat2023-08-131-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Platform Service Record (PSR) provides on-platform persistent and tamper resistant ledgers and counters. Key events captured within the Intel PSR Event Ledger, e.g., Chassis Intrusion Detection, can be observed over the life cycle of the platform to help assess confidence. Counters for platform S0 operational use and power state transitions can be assessed to aid in the determination of general wear or correlations of other platform events when determining platform decommission plans (repurpose, resell, recycle). PSR data is created and stored in CSE data partition. In platforms that employ CSE Lite SKU firmware, a firmware downgrade involves clearing of CSE data partition which results in PSR data being lost. CSE Lite SKU firmware supports a command to backup PSR data before initiating a firmware downgrade. Add a config to support this PSR data backup flow. BRANCH=None BUG=b:273207144 Change-Id: Iad1ce2906177081c103ef4d4bcef78fa2c95026f Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* src/*/post_code.h: Change post code prefix to POSTCODEYuchen He2023-08-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. header="src/soc/amd/common/block/include/amdblocks/post_codes.h \ src/include/cpu/intel/post_codes.h \ src/soc/intel/common/block/include/intelblocks/post_codes.h" array=`grep -r "#define POST_" $header | \ tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2` for str in $array; do splitstr=`echo $str | cut -d '_' -f2-` grep -r $str src | cut -d ':' -f 1 | \ xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g" done Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/common: Return CB_ERR when cse_data_clear_request() failsKrishna Prasad Bhat2023-08-041-1/+1
| | | | | | | | | | | | | | | | | | | cse_prep_for_rw_update() should return CB_ERR when cse_data_clear_request fails. It was modified to CB_SUCCESS in this commit ad6d3128f87c ("soc/intel/common: Use enum cb_err values") BRANCH=None BUG=None TEST=Verify the system goes to recovery during downgrade when cse_data_clear_request() fails. Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* soc/intel/common/block/cse/Kconfig: Remove unused symbolsElyes Haouas2023-08-031-38/+0
| | | | | | | | Change-Id: I35742721e049102a3e153b857824073a5d257cc3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76693 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Makefile.inc: relocate get_fmap_value() here from soc/intel/common/block/cseMatt DeVillier2023-07-031-1/+0
| | | | | | | | | | | | | | Move this function to the root Makefile.inc since other Makefiles use the exact same function call. Will allow for deduplication in AMD SoC Makefiles in a follow-on commit. Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76167 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/cse: Retrieve CSE RW FW version conditionallySubrata Banik2023-06-233-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a newer config to store the CSE RW FW version into the CBMEM. Prior to that CSE RW FW version was fetched unconditionally and ended up increasing the boot time by 7ms to 20ms depending on the SoC arch (including CSE arch). The way to retrieve the CSE firmware version is by sending the HECI command to read the CSE Boot Partition (BP) info. The cost of sending HECI command to read the CSE FW version is between 7ms-20ms (depending on the SoC architecture) hence,ensure this feature is platform specific and only enabled for the platformthat would like to store the CSE version into the CBMEM. TEST=Build and boot google/rex to avoid getting CSE RW FW version to save 18ms of the boot time. w/o this patch:   10:start of ramstage                            722,215 (43)   17:starting LZ4 decompress (ignore for x86)     741,415 (19,200) w/ this patch:   10:start of ramstage                            722,257 (43)   17:starting LZ4 decompress (ignore for x86)     723,777 (1,520) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I94f9f0f99706724c7d7e05668390f3deb603bd32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
* cbfs: Allow controlling decompression of unverified filesJulius Werner2023-06-191-0/+1
| | | | | | | | | | | | | | | | | | This patch adds a new Kconfig that controls whether CBFS APIs for unverified areas will allow file decompression when CBFS verification is enabled. This should be disallowed by default because it exposes the attack surface of all supported decompression algorithms. Make allowances for one legacy use case with CONFIG_SOC_INTEL_CSE_LITE_ COMPRESS_ME_RW that should become obsolete with VBOOT_CBFS_INTEGRATION. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ieae420f51cbc01dae2ab265414219cc9c288087b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75457 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/cmn/cse: Read ISH FW version if avilable in CSE partitionSubrata Banik2023-06-151-2/+1
| | | | | | | | | | | | | | This patch reduces the redundant config check to understand if an ISH FW partition is available and to fetch the ISH FW version. The goal is to fetch the ISH FW version if the ISH FW belongs to the CSE firmware partition table. Change-Id: I689a71377e7aea0fa3bc1835f355708c33c2caea Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75811 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final`Dinesh Gehlot2023-06-151-1/+17
| | | | | | | | | | | | | | | | | | This patch calls get CSE RW version function from .final hook if the platform has required config (`SOC_INTEL_CSE_LITE_SKU`) selected. BUG=b:280722061 TEST=Able to build and boot google/rex. > cbmem -c | grep "CSE RW Firmware Version:" [DEBUG] CSE RW Firmware Version: 18.0.0.1682 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75749 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/cse: Always save CSE RW version to CBMEMSubrata Banik2023-06-151-5/+5
| | | | | | | | | | | | | | | | This patch renames `cse_store_rw_fw_version` function that store currently running CSE RW FW version inside CBMEM. Additionally, perform the CSE RW FW storing operation unconditionally. TEST=Able to build and boot google/marasov. Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* {driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version configSubrata Banik2023-06-152-10/+11
| | | | | | | | | | | | | | | | | | This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config is clear. Any platform would like to fetch the currently running ISH firmware version should select this configuration. TEST=Able to build and boot google/marasov. Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/common: Add RPP-S PCI IDsJeremy Soller2023-05-231-0/+4
| | | | | | | | | | | | | Add PCI IDs to support Raptor Point PCH. Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2) Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/blk.cse: Fix check condition in store_cse_rw_fw_version()Dinesh Gehlot2023-05-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The return value of cse_get_bp_info() is an enum integer, where zero means success and non-zero means failure. The function store_cse_rw_fw_version() calls the function cse_get_bp_info() and validates the return value as a boolean causing prematurely returns of the parent API even if cse_get_bp_info() is successful. This patch corrects this logical error by returning only if cse_get_bp_info() fails. TEST=Build and boot google/nivviks and verify that the ISH version info command is only being sent during cold boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ice278e5ac69ff2f2c9f1936b76d71ae9deb6f855 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74998 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* soc/intel/common: Fix long delay when ME is disabledSean Rhodes2023-05-111-3/+15
| | | | | | | | | | | | | | | | | | | | | | If the ME is disabled with the `me_state` CMOS setting, boot times are approximately 5 seconds longer: 942:before sending EOP to ME 1,240,773 (5,599) 943:after sending EOP to ME 6,263,951 (5,023,177) Total Time: 6,167,443 This is because the current code only checks if the ME is disabled for CSE LITE SKUs. With this patch, boot times are approximately 5 seconds quicker: Total Time: 1,143,932 Tested on `starbook/adl` and `starbook/tgl`. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/74435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwiseSubrata Banik2023-05-061-1/+1
| | | | | | | | | | | | | | | This patch makes CSE sync in romstage default enabled unless ramstage config (SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) chooses to override it. TEST=Able to build google/marasov with this change where CSE sync is performed early inside romstage. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW SyncAnil Kumar2023-05-011-2/+1
| | | | | | | | | | | | | | | | | | | The change 'commit Iac37aaa5ede5e1cd ("Add Kconfigs to indicate when CSE FW sync is performed")' adds support to choose CSE FW update to be performed in ROMSTAGE or RAMSTAGE. The patch also introduced a dependency on ME_RW firmware compression. This patch removes the dependency between CSE FW sync in RAMSTAGE and ME_RW firmware compression as these two are not related and should be decoupled to support CSE FW sync in RAMSTAGE without the requirement to compress ME_FW. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74796 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* intel/mtl: Add get_cse_ver_from_cbfs functionAshish Kumar Mishra2023-04-261-17/+29
| | | | | | | | | | | | | | | This patch implements helper function get_cse_ver_from_cbfs() to retrieve the CSE Lite version from CBFE RW's metadata and calls the helper function from cse_check_update_status() TEST=Verified CSE Lite version in coreboot boot log Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Change-Id: Ie1bf186adfc3f87826a7ce9b0167a6bbe6767299 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74755 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
* soc/intel/cmn/cse: Make `cse_get_fpt_partition_info()` function staticSubrata Banik2023-04-221-1/+2
| | | | | | | | | | | | | | | | | The patch makes `cse_get_fpt_partition_info()` AP local/static as all the references to this function are in local to the cse_lite.c file. BUG=b:273661726 TEST=Able to build and boot google/marasov with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie50453946c8abe55c29e9001263f0264a73c8fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/74388 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/cmn/cse: Store ISH firmware version into CBMEMSubrata Banik2023-04-211-2/+50
| | | | | | | | | | | | | | | | | | | | The patch stores the ISH in the CBMEM table. It verifies CSE has been updated by comparing previous and current CSE versions. If it has, the patch updates the previous CSE version with the current CSE version. It then updates the CBMEM table with the current ISH version. BUG=b:273661726 TEST=The current and old CSE and ISH versions are verified on the google/nissa during cold and warm reboots. Additionally, version updates are verified by a debug patch that purposely updated the stored cse version. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEMSubrata Banik2023-04-212-2/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch implements an API that stores the CSE firmware version in the CBMEM table. The API will be called from RAMSTAGE based on boot state machine BS_PRE_DEVICE/BS_ON_EXIT Additionally, renamed ramstage_cse_fw_sync() to ramstage_cse_misc_ops() in order to add more CSE related operations at ramstage. This patch also adds a configuration option, 'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage of firmware version information in CBMEM memory. This information can be used to identify the firmware version that is currently installed on the system. The option depends on the `DRIVERS_INTEL_ISH` config and platform should be flexible enough to opt out from enabling this feature. The cost of sending HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to read the CSE RW version on every cold reset (to cover the CSE update scenarios) and store into CBMEM to avoid the cost of resending the HECI command in all consecutive warm boots. Later boot stages can just read the CBMEM ID to retrieve the ISH version if required. Finally, ensure this feature is platform specific hence, getting enabled for the platform that would like to store the ISH version into the CBMEM and parse to perform some additional work. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() functionSubrata Banik2023-04-211-5/+9
| | | | | | | | | | | | | | | | | This patch refactors cse_fw_sync() function to include timestamp associated with the CSE sync operation.This effort will ensure the SoC code just makes a call into the cse_fw_sync() without bothering about adding timestamp entries. TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/intel/cmn/cse: Refactor ramstage_cse_fw_sync() functionSubrata Banik2023-04-211-3/+3
| | | | | | | | | | | | | | | This patch refactors sleep type check inside ramstage_cse_fw_sync() to avoid additional logic while performing cse_fw_sync() operation. TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7c7a91c81d51dbf6742e12c58a24b9f52fff5630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/intel/cmn/cse: Move API to get FW partition info into cse_lite.cSubrata Banik2023-04-152-57/+57
| | | | | | | | | | | | | | | | The patch moves API that gets the CSE FW partition information into CSE Lite specific file aka cse_lite.c because the consumer of this API is the cse_lite specific ChromeOS devices hence, it's meaningful to move the cse lite specific implementation inside cse_lite.c file. BUG=b:273661726 TEST=Able to build and boot google/marasov with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I49ffaec467f6fb24327de3b2882e37bf31eeb7cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/74382 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmd/block: Implement an API to get firmware partition detailsDinesh Gehlot2023-04-131-0/+57
| | | | | | | | | | | | | | | | This patch retrieves details of a specified firmware partition table. The information retrieved includes the current firmware version and other information about the firmware partition. The patch communicates with the ME using the HECI command to acquire this information. BUG=b:273661726 Test=Verified the changes for ISH partition on nissa board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* soc/intel/{adl, cmn}: Send CSE EOP Async CMD earlySubrata Banik2023-04-111-10/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch sends the CSE EOP command asynchronous implementation early as part of `soc_init_pre_device`. Without this patch the duration between asynchronous CSE EOP send and receive commands is not ample whichcauses idle delay while waiting for EOP response. The goal of the CSE async implementation is to avoid idle delay while capturing the response from CSE EOP cmd. This patch helps to create ample duration between CSE EOP command being sent and response being captured. TEST=Able to boot google/marasov EVT sku to ChromeOS and observed ~30ms of boot time savings (across warm and cold reset scenarios). Without this patch: 963:returning from FspMultiPhaseSiInit 907,326 (97,293) ... ... 115:finished elog init 967,343 (2,581) 942:before sending EOP to ME              967,821 (478) …  16:finished LZMA decompress (ignore for x86)    1,017,937 (12,135) 943:after sending EOP to ME                     1,067,799 (49,861) … … 1101:jumping to kernel                          1,144,587 (13,734) Total Time: 1,144,549 With this patch: 963:returning from FspMultiPhaseSiInit 918,291 (97,320) 942:before sending EOP to ME                    918,522 (230)   ... ... 16:finished LZMA decompress (ignore for x86) 1,029,476 (12,483)   943:after sending EOP to ME                     1,033,456 (3,980)   ... ...   1101:jumping to kernel                          1,111,410 (14,007) Total Time: 1,111,375 Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* soc/intel/cmn/cse: Handle EOP completion asynchronouslyJeremy Compostella2023-04-073-45/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot supports three instances of sending EOP: 1. At CSE `.final' device operation 2. Early as with Alder Lake in chip_operations.init if `SOC_INTEL_CSE_SEND_EOP_EARLY' is selected 3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if `SOC_INTEL_CSE_SEND_EOP_LATE' is selected Currently, Alder Lake uses #3 as it results in better and more stable boot time. However, what would deliver even better result is to not actively wait for CSE completion. This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig which split the action of sending EOP request and receiving EOP completion response from the CSE. This patch used in conjunction with #1 can significantly improves the overall boot time on a Raptor Lake design. For example `SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 1 | 1020.052 | 971.272 | | 2 | 1015.911 | 971.821 | | 3 | 1038.415 | 1021.841 | | 4 | 1020.657 | 993.751 | | 5 | 1065.128 | 1020.951 | | 6 | 1037.859 | 1023.326 | | 7 | 1042.010 | 984.412 | |----------+----------+-----------| | Mean | 1034.29 | 998.20 | | Variance | 4.76 % | 5.21 % | The improvement is not stable but comparing coreboot and FSP performance timestamps demonstrate that the slowness is caused by a lower memory frequency (SaGv point) at early boot which is not an issue addressed by this patch. We also observe some improvement on an Alder Lake design. For example, the same configuration on a kano board can deliver up to 10 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 0 | 1067.719 | 1050.106 | | 1 | 1058.263 | 1056.836 | | 2 | 1064.091 | 1056.709 | | 3 | 1068.614 | 1055.042 | | 4 | 1065.749 | 1056.732 | | 5 | 1069.838 | 1057.846 | | 6 | 1066.897 | 1053.548 | | 7 | 1060.850 | 1051.911 | |----------+----------+-----------| | Mean | 1065.25 | 1054.84 | The improvement is more limited on kano because a longer PCIe initialization delays EOP in the Late EOP configuration which make it faster to complete. CSME team confirms that: 1. End-Of-Post is a blocking command in the sense that BIOS is requested to wait for the command completion before loading the OS or second stage bootloader. 2. The BIOS is not required to actively wait for completion of the command and can perform other operations in the meantime as long as they do not involve HECI commands. On Raptor Lake, coreboot does not send any HECI command after End-Of-Post. FSP-s code review did not reveal any HECI command being sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or `END_OF_FIRMWARE' notifications. If any HECI send and receive command has been sent the extra code added in `cse_receive_eop()' should catch it. According to commit 387ec919d9f7 ("soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first boot after flashing of a Marasov board for instance) request coreboot to perform a global request out of AFTER_PCI_ENUM notification. Global request relies on a HECI command. Even though, we tested that it does not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent potential a global reset command to "conflict" with the EOP command. This patch also introduces a new code logic to detect if CSE is in the right state to handle the EOP command. Otherwise, it uses the prescribed method to make the CSE function disable. The typical scenario is the ChromeOS recovery boot where CSE stays in RO partition and therefore EOP command should be avoided. [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [INFO ] HECI: coreboot in recovery mode; found CSE in expected SOFT TEMP DISABLE state, skipping EOP [INFO ] Disabling Heci using PMC IPC [WARN ] HECI: CSE device 16.0 is hidden [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled BUG=b:276339544 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post sent soon after FSP-s and EOP message receive at `BS_PAYLOAD_BOOT'. Verify robustness by injecting a `GET_BOOT_STATE' HECI command with or without `heci_reset'. The implementation always successfully completed the EOP before moving to the payload. As expected, the boot time benefit of the asynchronous solution was under some injection scenario undermined by this unexpected HECI command. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I01a56bfe3f6c37ffb5e51a527d9fe74785441c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"Nick Vaccaro2023-04-053-108/+35
| | | | | | | | | | | | | | | | | | | | | This reverts commit e7a1204f26fe3628de99b4ab4e3f32916565b95c. This initial change was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74207 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Add support for CSE timestamp data versionsBora Guvendik2023-04-042-14/+18
| | | | | | | | | | | | | | | | | | CSE performance data timestamps are different for version 1 Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch moves the current ADL/RPL timestamp definitions to a separate header file. It marks current structure as version 1. BUG=b:259366109 TEST=Boot to OS, check ADL/RPL pre-cpu timestamps. Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
* soc/intel/cmn/cse: Handle EOP completion asynchronouslyJeremy Compostella2023-03-313-35/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | coreboot supports three instances of sending EOP: 1. At CSE `.final' device operation 2. Early as with Alder Lake in chip_operations.init if `SOC_INTEL_CSE_SEND_EOP_EARLY' is selected 3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if `SOC_INTEL_CSE_SEND_EOP_LATE' is selected Currently, Alder Lake uses #3 as it results in better and more stable boot time. However, what would deliver even better result is to not actively wait for CSE completion. This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig which split the action of sending EOP request and receiving EOP completion response from the CSE. This patch used in conjunction with #1 can significantly improves the overall boot time on a Raptor Lake design. For example `SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 1 | 1020.052 | 971.272 | | 2 | 1015.911 | 971.821 | | 3 | 1038.415 | 1021.841 | | 4 | 1020.657 | 993.751 | | 5 | 1065.128 | 1020.951 | | 6 | 1037.859 | 1023.326 | | 7 | 1042.010 | 984.412 | |----------+----------+-----------| | Mean | 1034.29 | 998.20 | | Variance | 4.76 % | 5.21 % | The improvement is not stable but comparing coreboot and FSP performance timestamps demonstrate that the slowness is caused by a lower memory frequency (SaGv point) at early boot which is not an issue addressed by this patch. We also observe some improvement on an Alder Lake design. For example, the same configuration on a kano board can deliver up to 10 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 0 | 1067.719 | 1050.106 | | 1 | 1058.263 | 1056.836 | | 2 | 1064.091 | 1056.709 | | 3 | 1068.614 | 1055.042 | | 4 | 1065.749 | 1056.732 | | 5 | 1069.838 | 1057.846 | | 6 | 1066.897 | 1053.548 | | 7 | 1060.850 | 1051.911 | |----------+----------+-----------| | Mean | 1065.25 | 1054.84 | The improvement is more limited on kano because a longer PCIe initialization delays EOP in the Late EOP configuration which make it faster to complete. CSME team confirms that: 1. End-Of-Post is a blocking command in the sense that BIOS is requested to wait for the command completion before loading the OS or second stage bootloader. 2. The BIOS is not required to actively wait for completion of the command and can perform other operations in the meantime as long as they do not involve HECI commands. On Raptor Lake, coreboot does not send any HECI command after End-Of-Post. FSP-s code review did not reveal any HECI command being sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or `END_OF_FIRMWARE' notifications. If any HECI send and receive command has been sent the extra code added in `cse_receive_eop()' should catch it. According to commit 387ec919d9f7 ("soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first boot after flashing of a Marasov board for instance) request coreboot to perform a global request out of AFTER_PCI_ENUM notification. Global request relies on a HECI command. Even though, we tested that it does not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent potential a global reset command to "conflict" with the EOP command. BUG=b:276339544 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post sent soon after FSP-s and EOP message receive at `BS_PAYLOAD_BOOT'. Verify robustness by injecting a `GET_BOOT_STATE' HECI command with or without `heci_reset'. The implementation always successfully completed the EOP before moving to the payload. As expected, the boot time benefit of the asynchronous solution was under some injection scenario undermined by this unexpected HECI command. Change-Id: Ib09dcf9140eb8a00807a09e2af711021df4b416f Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73619 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/cmn/cse: Make heci_(send|receive) public functionsJeremy Compostella2023-03-231-15/+2
| | | | | | | | | | | | | | | | | | | Having these two functions public allow "asynchronous" HECI command implementation. Typically, these function can be use to implement an asynchronous End-Of-Post. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Successful compilation for brya0 Change-Id: I7d029bb9af4b53f219018e459d17df9c1bd33fc1 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/cmn/block/cse: ME source code at common locationDinesh Gehlot2023-02-242-1/+120
| | | | | | | | | | | | | | | | | | This patch adds ME specific source code at common location in order to reduce maintenance efforts at SoC level and improve readability. The functionality and code are redundant for various SoC platforms and require more maintenance. BUG=b:260309647 Test=Build verified for brya and rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic6622662fd3b8bcc9d9ac8bd6ffa732f5d78801a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73133 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn: Support for ME spec versions for SoCs at common codeDinesh Gehlot2023-02-241-1/+1
| | | | | | | | | | | | | | | | | | | This patch includes ME specification datastructures for various ME versions. Including the ME specification in common code will help current and future SoC platforms to select the correct version based on the applicable configuration. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Build verified for brya and rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I83df41d7180d2df419849a0c01c728ff0fe75378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73129 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn: Include ME specification configuration at commonDinesh Gehlot2023-02-241-0/+59
| | | | | | | | | | | | | | | | | | This patch includes ME specification configuration for various versions, which will allow SoCs to get ME support by selecting the correct version. BUG=b:260309647 Test=Build verified for brya and rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I817d14e52b0d353bbb4316d6362fcb80cbec3cda Reviewed-on: https://review.coreboot.org/c/coreboot/+/73128 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* tree: Drop repeated wordsAlexander Goncharov2023-02-071-1/+1
| | | | | | | | | | | | | Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-15 02:15:32 +0000