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path: root/src/soc/intel/common/block/pcie
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/skylake: Assign device ops in chipset devicetreeNico Huber2022-09-151-58/+2
* soc/intel: Add Raptor Lake device IDsBora Guvendik2022-05-161-0/+3
* soc/intel/common: Include Meteor Lake device IDsWonkyu Kim2022-03-091-0/+12
* src: Make PCI ID define names shorterFelix Singer2022-03-071-303/+303
* intelblocks/pcie: Correct mapping between LCAP port and coreboot indexMAULIK V VAGHELA2022-02-251-6/+11
* soc/intel/common/block/pcie/rtd3: Fix bit checksAngel Pons2022-02-151-6/+6
* soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-NUsha P2022-02-111-7/+7
* treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner2022-02-071-1/+1
* soc/intel/common/block/pcie/rtd3: Add optional _OFF and _ON skip controlCliff Huang2022-02-072-0/+62
* soc/intel/common/block/pcie/rtd3: Add PM methods to the device.Cliff Huang2022-02-072-0/+100
* intel/common/block/pcie: Add NULL/count check in pcie_rp_update_devtreeMAULIK V VAGHELA2022-01-311-0/+3
* soc/intel/common: Include Alder Lake-N device IDsUsha P2022-01-251-0/+2
* soc/intel/common/block/pcie/rtd3: Fix PMC IPC method for CPU PCIe RPTim Wawrzynczak2022-01-241-1/+1
* soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPsTim Wawrzynczak2022-01-071-11/+29
* soc/intel/common/block/pcie/rtd3: Add ModPHY power gate support for RTD3Tim Wawrzynczak2021-12-131-5/+79
* soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDsTracy Wu2021-11-121-0/+3
* soc/intel/common: Add TGL-H PCI IDsJeremy Soller2021-08-191-0/+24
* soc/intel/common/pcie/rtd3: Update _S0W to use symbol instead of 4Tim Wawrzynczak2021-08-091-1/+1
* soc/intel: Rename 200-series PCH device IDsAngel Pons2021-04-281-24/+24
* soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRCRizwan Qureshi2021-04-211-1/+1
* acpi/acpigen.h: Add more intuitive AML package closing functionsJakub Czapiga2021-03-221-1/+0
* pciexp_device: Rewrite LTR configurationNico Huber2021-03-151-6/+4
* device: Give `pci_ops.set_L1_ss_latency` a proper nameNico Huber2021-03-121-2/+2
* soc/intel/commmon: Include Alder Lake device IDsVarshit Pandya2021-01-221-0/+10
* soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguousFurquan Shaikh2021-01-182-6/+8
* soc/intel/common/pcie: Add helper function for getting mask of enabled portsFurquan Shaikh2021-01-122-0/+43
* soc/intel/common: Add PCIe Runtime D3 driver for ACPIDuncan Laurie2020-11-206-0/+363
* soc/intel/common: Include Alder Lake device IDsSubrata Banik2020-08-051-0/+40
* src: Never set ISA Enable on PCI bridgesAngel Pons2020-07-281-3/+2
* soc/intel/common/block/pcie: Select ASPM on mainboard basisChristian Walter2020-07-121-2/+10
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-112-2/+0
* soc/intel/common: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-062-26/+4
* soc: Remove copyright noticesPatrick Georgi2020-03-182-2/+0
* soc/intel/common: Update Jasper Lake Device IDsMeera Ravindranath2020-02-251-8/+8
* soc/intel/common: Add Elkhartlake Device IDsTan, Lean Sheng2020-01-221-0/+7
* soc/intel/common: Add PCI device IDs for CMP-HGaggery Tsai2019-12-131-0/+24
* soc/intel/common: Add Jasperlake Device IDsrkanabar2019-12-101-0/+8
* soc/intel: Implement PCIe RP devicetree update based on LCAPNico Huber2019-11-162-0/+178
* soc/intel/common: Include Tigerlake device IDsRavi Sarawadi2019-11-051-0/+16
* intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROLKyösti Mälkki2019-10-011-1/+2
* soc/intel/skylake: Add Lewisburg family PCH supportMaxim Polyakov2019-09-061-0/+40
* device/pciexp_device: Convert LTR non-snoop/snoop value into common macroSubrata Banik2019-03-271-6/+2
* {northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()Subrata Banik2019-03-211-10/+1
* Fix 'unsigned int' to bare use of 'unsigned'Subrata Banik2019-03-191-1/+1
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-1/+1
* soc/intel/common: Include cometlake PCH IDsRonak Kanabar2019-02-261-0/+16
* soc/intel/{common, skylake}: Make ASPM enabling as common PCH featureSubrata Banik2018-11-191-0/+4
* soc/intel/common: Include Icelake device IDsAamir Bohra2018-11-071-0/+16
* soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh2018-10-171-1/+25
* soc/intel/common/block: Don't use device_t in ramstageElyes HAOUAS2018-09-181-1/+1
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