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path: root/src/soc/intel/xeon_sp/include
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* soc/intel: Unify the definition of TCO registersMarek Maslanka2024-01-301-13/+1
* soc/intel/xeon_sp/chip_common: Improve the domain IDPatrick Rudolph2024-01-241-1/+11
* soc/intel/xeon_sp: Add IIO resources via SSDTArthur Heymans2024-01-221-1/+1
* soc/intel/xeon_sp: Scan and allocate resources on all stacksArthur Heymans2024-01-221-1/+0
* soc/intel/xeon_sp: Redesign resource allocationArthur Heymans2024-01-152-3/+8
* soc/intel/xeon_sp: Add missing HDA devicePatrick Rudolph2023-09-151-0/+2
* soc/intel/xeon_sp: use VGA_MMIO_* defines from arch/vga.hFelix Held2023-07-201-4/+0
* soc/intel/xeon_sp: Introduce soc_cpu_is_enabledPatrick Rudolph2023-07-181-0/+1
* soc/intel/xeon_sp: Don't sort struct device cpus for numaArthur Heymans2023-04-141-1/+0
* soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP supportTim Chu2023-03-251-0/+4
* soc/intel/xeon_sp: Report platform cpu infoNaresh Solanki2023-03-231-1/+1
* soc/intel/xeon_sp: Fix PCH IOAPIC IDPatrick Rudolph2023-03-231-3/+0
* soc/intel/xeon_sp/uncore.c: Add CXL memory into memory mapJonathan Zhang2023-03-221-0/+65
* soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handlingTim Chu2023-03-221-0/+1
* soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage codeJonathan Zhang2023-03-191-0/+4
* soc/intel/xeon_sp: add MSR definitions for SPR-SPDavid Hendricks2023-03-191-2/+8
* soc/intel/xeon_sp: Split SKX/CPX MSRs into separate headersJonathan Zhang2023-03-191-16/+3
* soc/intel/xeon_sp: Add P2SB definition for SPR-SPJonathan Zhang2023-03-191-4/+8
* soc/intel/xeon_sp: rework lock_pam0123() to accomodate hidden SAD deviceJonathan Zhang2023-03-091-0/+2
* soc/intel/xeon_sp: use get_socket_ubox_busno() to hide soc specificsJonathan Zhang2023-03-091-1/+0
* soc/intel/xeon_sp: Add PM definition for SPR-SPDavid Hendricks2023-03-071-7/+1
* soc/intel/xeon_sp/finalize.c: Set BIOS_DONE MSR as applicableTim Chu2023-02-191-0/+1
* soc/intel/xeon_sp: move PCH specific code into lbg directoryJonathan Zhang2023-02-172-0/+10
* soc/intel/xeon_sp/include/soc/pmc.h: move to lbg directoryJonathan Zhang2023-01-291-47/+0
* Revert "soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handling"Elyes Haouas2023-01-231-1/+0
* soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handlingTim Chu2023-01-231-0/+1
* soc/intel/*/include/soc/gpio.h: Add "IWYU pragma: export" commentElyes Haouas2023-01-201-1/+1
* soc/intel/xeon_sp: Move codes to support new PCHTim Chu2022-12-224-689/+1
* sb,soc/intel: Address TCO SECOND_TO_STS name collisionKyösti Mälkki2022-11-281-1/+1
* soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitionsJonathan Zhang2022-11-081-0/+14
* soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-MJohnny Lin2022-11-041-0/+2
* soc/intel/xeon_sp: Remove unused madt setup functionArthur Heymans2022-10-281-1/+0
* soc/intel/xeon_sp: Define macro TOTAL_PADSEric Lai2022-06-171-0/+2
* *.h: Fix up typos in guardingArthur Heymans2022-05-111-1/+1
* soc/intel: Move `pmc_clear_pmcon_sts()` into IA common codeSubrata Banik2022-03-291-3/+0
* arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held2022-02-251-3/+0
* soc/intel/xeon_sp: Add function to clear PMCON status bitsSubrata Banik2022-02-152-0/+4
* soc/intel/common/cse: Rework heci_disable functionSubrata Banik2022-02-021-0/+1
* soc/intel/xeon_sp: Refactor `get_threads_per_package()`Angel Pons2021-11-051-1/+0
* soc/intel/xeon_sp: disable PM ACPI timer if chosenMichael Niewöhner2021-11-031-0/+2
* soc/intel: drop P_BLK supportMichael Niewöhner2021-10-131-9/+0
* soc/intel/xeon_sp: correct wrong gpio register base offsetsMichael Niewöhner2021-09-231-4/+4
* soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registersMichael Niewöhner2021-09-231-0/+2
* src/intel/xeon_sp: add hardware error support (HEST)Rocky Phagura2021-06-041-0/+40
* soc/intel/xeon_sp: Drop unused functions and prototypesAngel Pons2021-04-211-6/+0
* soc/intel/xeon_sp: Set SATA REGLOCKsMarc Jones2021-04-181-0/+10
* soc/intel/xeon_sp: Set MSR locksMarc Jones2021-04-181-0/+3
* soc/intel/xeon_sp: Prepare for CBnT BPM generationArthur Heymans2021-03-301-2/+2
* soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.hSubrata Banik2021-03-271-0/+6
* soc/intel/xeon_sp: Move PCH PCI device definesMarc Jones2021-03-261-0/+54
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