summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
...
* soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMMSubrata Banik2021-09-301-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Pushing EOP msg post FSP notify helps to save ~30ms+ boot time across various warm reboots. This patch ensures late sending EOP msg when function disabling of CSE is no longer a requirement. BUG=b:200644229 TEST=Able to save ~30ms+ of boot time Without this code change EOP sending timestamp as below: 943:after sending EOP to ME 1,248,328(61,954)) With this code change EOP sending timestamp as below: 943:after sending EOP to ME 1,231,660 (2,754) Change-Id: I2b78a1c07803aacfb34dce9e94b2a05a2491aabc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Perform `soc_finalize` at entry of BS_PAYLOAD_BOOTSubrata Banik2021-09-301-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | This patch ensures soc_finalize() is getting called at the entry of BS_PAYLOAD_BOOT boot state instead of BS_PAYLOAD_LOAD, BS_ON_EXIT. The purpose of this change is to accommodate more time to push out sending CSE EOP messages at post. BUG=b:200644229 TEST=coreboot serial log suggests soc_finalize() is getting called as part of the BS_PAYLOAD_BOOT entry. Finalizing chipset. apm_control: Finalizing SMM. APMC done. BS: BS_PAYLOAD_BOOT entry times (exec / console): 21 / 15 ms Change-Id: I8632eca057255d7f4a38b64fd17c1f3d84123051 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
* soc/intel/common/../cse: Perform D0I3 bit reset/set prior sending EOPSubrata Banik2021-09-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to coreboot sending EOP messages during post, it's important to ensure that CSE is not in Idle state. In case CSE is in Dev Idle state (which means D0I3 bit is set), reset this bit before sending EOP command. This patch ensures coreboot has provision to send CSE EOP messages even after the FSP Notify phase without any delays waiting for the device to respond or timeout. BUG=b:200644229 TEST=Able to send CSE EOP message even after FSP Notify phase. Attempting CSE EOP msg sending post FSP notify without this code change causes `timeout` issue as below: BS: BS_PAYLOAD_LOAD exit times (exec / console): 171 / 0 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post HECI: timed out reading answer! HECI: Failed to receive! HECI: receive Failed HECI: EOP send/receive fail ERROR: Failed to send EOP to CSE, 2 cse: CSE status registers: HFSTS1: 0x90000255, HFSTS2: 0xf10516 HFSTS3: 0x20 VB2:vb2api_fail() Need recovery, reason: 0x31 / 0xc Saving nvdata board_reset() called! full_reset() called! Attempting CSE EOP msg sending post FSP notify with this code change is `successful` as below: BS: BS_PAYLOAD_LOAD exit times (exec / console): 170 / 0 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot Change-Id: Iae1bc52e94b08f97004424ea0c147d6da8aca6e2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common/../cse: Create APIs for CSE device state transitionSubrata Banik2021-09-302-0/+83
| | | | | | | | | | | | | | | | | This patch ensures APIs that are responsible for CSE device state transition between active to idle and vice-versa are available publically for other modules/boot stages to consume. BUG=b:200644229 TEST=Able to build and boot ADLRVP-P. Change-Id: Ia480877822d343f2b4c9bf87b246812186d49ea3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/intel/adlrvp: Update Rcomp target value for DDR4 RVP SKUSubrata Banik2021-09-301-2/+2
| | | | | | | | | | | | | | Update to recommended Rcomp drive strength value for DDR4 as per MRC team's input. Additionally, add space around the `targets` array. Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507d99a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/variants/gimble: Correct SSD power sequenceMark Hsieh2021-09-302-1/+14
| | | | | | | | | | | | | | | M.2 spec describes PERST# should be sequenced after power enable. BUG=b:201512872 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie164ddb29f947e190fa87b31165e3c84b07926e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58034 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Guard acpi_fill_ssdt assignment with HAVE_ACPI_TABLESTim Wawrzynczak2021-09-291-2/+4
| | | | | | | | Change-Id: I3677b4e545599d00a4ba16464836834febc2d1a5 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58024 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Drop unnecessary `select REG_SCRIPT`Angel Pons2021-09-297-7/+0
| | | | | | | | | | | | | These platforms no longer use reg-script. Drop unneeded select. Change-Id: I8fc4dc29d25dffbf9ed1947d0ff013b2fae0faaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common/block/smbus: Drop reg-script usageAngel Pons2021-09-291-14/+11
| | | | | | | | | | | | | | Using reg-script just to read-modify-write some registers makes no sense. Replace reg-script usage with regular register operations. Change-Id: I87d1278360a231cbe5b5f825ad9a448e59e63ea2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/skylake: Drop reg-script usageAngel Pons2021-09-292-33/+21
| | | | | | | | | | | | | | Using reg-script just to read-modify-write some registers makes no sense. Replace reg-script usage with regular register operations. Change-Id: Ib3c83131c30fd02c579b910cfad6843eb28ba8f1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacksMichael Niewöhner2021-09-295-20/+20
| | | | | | | | | | | | | The current names of the PMC init/enable callbacks are very confusing. Rename them. Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* google/trogdor: Always initialize eDP bridge I2C QUP firmwareJulius Werner2021-09-291-2/+4
| | | | | | | | | | | | | | | | | | | | In CB:52662 when MIPI display support was added, we accidentally changed the code flow for eDP displays such that i2c_init() will no longer be called when display_init_required() is false. This is a problem because on this platform, i2c_init() does not just prepare the I2C controller for firmware use, it also loads firmware to the controller that makes it behave like an I2C device in the first place -- a step that the kernel cannot later do on its own if the firmware didn't already do it. Skipping this initialization means the I2C controller becomes unusable to the kernel. This patch fixes the issue by making the i2c_init() unconditional again. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie4546c31d87d91113eeef7dc7a18599a87e6d6eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58026 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Rename GNVS struct member to match ASLAngel Pons2021-09-293-4/+4
| | | | | | | | | | Rename the `ecps` GNVS struct member to `epcs` to match the name in ASL. Change-Id: I1f6b97309eea75e7dbb4e5e664660df05ec0845e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* herobrine: Initialize SAR sensor QUPShelley Chen2021-09-291-0/+2
| | | | | | | | | | | | | | | Initializing SAR sensor (QUP2, address 0x988000) BUG=b:198456205 BRANCH=None TEST=Boot into kernel and make sure no i2c errors for 0x988000 in dmesg Change-Id: I75b0e9173d4c49b5e7308158a678964d6637b225 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/herobrine: Change preprocessor to C codeShelley Chen2021-09-291-9/+15
| | | | | | | | | | | | BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B Change-Id: I10f8a9682200b883474dc385331c5dae84cbdb08 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* herobrine: Add fingerprint power sequencingShelley Chen2021-09-295-0/+36
| | | | | | | | | | | | | | | | | | For Herobrine variants that include a finger print sensor, we will need to power sequence it. We are using the same FP sensor as trogdor, so we will follow the timings used for trogdor from CL:2695676. BUG=b:198474942 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B Change-Id: Ica6eafc47cf1b95eeb8d94c6e0a8c88519665e3f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58021 Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/guybrush/var/nipperkin: Add ALC5682I and MAX98360 supportPatrick Huang2021-09-292-2/+17
| | | | | | | | | | | | | Add ID "10029836" for machine driver, "RTL5682" for ALC5682I and "MX98357A" for MAX98360. BUG=b:198716348 TEST=Build nipperkin, codec is functional with new machine driver. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: Iab9d11adb7cd08effa2a9b6a627832bd89cb3cb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/boten: Add fw_config probe for ALC5682-VD & VSStanley Wu2021-09-291-1/+25
| | | | | | | | | | | | | | | | | | | ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. Define SSFC bit 9-11 in coreboot for codec within ec. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:193694180 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Iba91b51cbbe7adc502372c9a026867de61d8035d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/mancomb: Delete board supportKarthikeyan Ramasubramanian2021-09-2923-1195/+0
| | | | | | | | | | | | | | | Mancomb mainboard has been cancelled. Hence delete the board support. BUG=b:190404616 TEST=None Cq-Depend: chromium:3188634 Change-Id: I3ce02efb1fa5ea488447099abe08da6051fb6fc6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* arch/x86,cpu/x86: Disable the %gs and %fs segmentsRaul E Rangel2021-09-296-6/+12
| | | | | | | | | | | | | | | | | | | | | The %fs and %gs segment are typically used to implement thread local storage or cpu local storage. We don't currently use these in coreboot, so there is no reason to map them. By setting the segment index to 0, it disables the segment. If an instruction tries to read from one of these segments an exception will be raised. The end goal is to make cpu_info() use the %gs segment. This will remove the stack alignment requirements and fix smm_do_relocation. BUG=b:194391185, b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaa376e562acc6bd1dfffb7a23bdec82aa474c1d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/alderlake: Add GFx Device ID 0x46c3Selma Bensaid2021-09-293-0/+3
| | | | | | | | | | | | This CL adds support for new ADL-M graphics Device ID 0x46c3. TEST=boot to OS Change-Id: Ib55fb501f96fe9bcc328202511bbfe84a3122285 Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/intel/adlrvp, mb/google/brya: Add ADLP 242 PLx configurationsTracy Wu2021-09-292-0/+2
| | | | | | | | | | | | | | Add ADLP 242 sku PLx related settings, which follow the settings of ADLP 282 sku (both are 15w). BUG=b:201253904 TEST=USE='fw_debug' emerge-brya intel-adlfsp coreboot chromeos-bootimage Change-Id: If9b60893ab3e2c4a88e7d2cf45223c5fbce6f847 Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* soc/intel/alderlake: Add ADLP 242 power configurationsTracy Wu2021-09-294-0/+14
| | | | | | | | | | | | | | Add ADLP 242 sku power related settings, which follow the settings of ADLP 282 sku (both are 15w). BUG=b:201253904 TEST=Build and check fsp log to confirm the settings are set properly. Change-Id: I829dd690c22d167a507b1910106da06b275cec09 Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/brya: Update PCH power cycle related durationsTim Wawrzynczak2021-09-291-0/+6
| | | | | | | | | | | | | | | | | | | | | The voltage rail discharge times have been measured, so therefore the boot time on a cold boot when the CSE must go through a global reset and thus a trip to S5 can be optimized. Select the lowest applicable value for each PchPmSlp UPD that can be used with these measurements. This is programmed in the baseboard because the measured discharge times leave (what should be) plenty of margin for variants to also not violate any power sequencing guidelines from the PDG. BUG=b:184799383 TEST=verified time in S5 during a global reset is ~1s instead of 4s Change-Id: Ia373c47b3967d68ddac21707c6eb4565d9d6519e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/alderlake: Add support for power cycle and SLP signal durationTim Wawrzynczak2021-09-292-0/+80
| | | | | | | | | | | | | | The UPDs for PM power cycle duration and SLP_* signal durations are all identical to Tiger Lake, so add similar support, but use enums instead of comments to represent the durations symbolically. BUG=b:184799383 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4a531f042658894bcbc6a76eff453c06e90d66b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57891 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede: Remove drawcia_legacy board supportKarthikeyan Ramasubramanian2021-09-292-11/+0
| | | | | | | | | | | | | | Support for drawcia_legacy board is cancelled. Hence remove the board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I76cd3e388439f5aee94a17fe35ae210f449cfbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/58000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
* mb/google/dedede: Remove Boten_Legacy board supportKarthikeyan Ramasubramanian2021-09-292-8/+0
| | | | | | | | | | | | | | Support for Boten_legacy board is cancelled. Hence remove the board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If26dc869ff95dff70c0f83a13f6f727aa5992dbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/57999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
* mb/google/dedede: Remove wheelie variant board supportKarthikeyan Ramasubramanian2021-09-298-81/+0
| | | | | | | | | | | | | | Wheelie variant board has been cancelled. Remove wheelie variant board support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3ad5bc1c987feb55183a663937794781c7301a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
* mb/google/dedede: Remove cappy variant supportKarthikeyan Ramasubramanian2021-09-298-82/+0
| | | | | | | | | | | | | Cappy variant is cancelled. Hence delete the cappy variant support. BUG=b:192256341 TEST=None Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: If43188a3e6bf4f4449c7e2d08be7609efe58dca1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
* {sb,soc}/intel: Drop unused globalnvs.asl methodsAngel Pons2021-09-297-235/+0
| | | | | | | | | | These methods are never used in the code. Drop them. Change-Id: If5568b494f821d2647ada5ae845bcd015708520e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* {sb,soc}/intel: Drop PRMx from GNVSAngel Pons2021-09-2918-108/+108
| | | | | | | | | | These fields are never used in the code. Drop them. Change-Id: Icd07f2d704c19126bf6df4d740c21d5a1342061b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* {sb,soc}/intel: Drop LCKF from GNVSAngel Pons2021-09-2918-18/+18
| | | | | | | | | | This field is never used in the code. Drop it. Change-Id: I88207ec369ab83823ef2f3fc40f68a0980ce9663 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/mediatek/mt8195: initialize DFDRex-BC Chen2021-09-293-0/+25
| | | | | | | | | | | | | | | | | DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. BUG=b:192429713 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507c99b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57980 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/mediatek/mt8195: Remove unused codeRyan Chuang2021-09-2913-13577/+6
| | | | | | | | | | | | | | | Remove unused drivers and some fast calibration implementations to align with the latest MTK memory reference code. TEST=boot to kernel Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I2e6be2e16c139e48c65352fe2eabf16bf9cd550a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57978 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/purism/librem_skl: Clean up dsdt.aslFelix Singer2021-09-281-16/+7
| | | | | | | | | | | | | Move includes using library paths to the top and remove unnecessary comments. Also, get rid of that unnecessary _SB scope. Use an absolute path for the PCI0 device instead. Change-Id: I2c4fb1933eda2eb75bfe9181f13e189ec66cadf9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/brya/variants/taeko: add NVMe GPIOs to early_gpio_tableKevin Chang2021-09-281-2/+9
| | | | | | | | | | | | | | | NVMe needs extra time to run boot process, enable power and deassert reset for NVMe earlier in the boot flow that taeko can successfully boot into OS with non-serial coreboot. BUG=b:199969366 & b:200711149 TEST=Build FW and test with non-serial FW reboot 20 times pass. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I032c5b90fb2148c4075d6ead3e4161c0cc659b20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/var/magolor: Add custom Wifi SAR for magmaTyler Wang2021-09-281-0/+4
| | | | | | | | | | | | | | | | | | Add wifi sar for magma. Due to fw-config cannot distinguish between magolor and magma. Using sku_id to decide to load magma custom wifi sar. BUG=b:192423859 TEST= emerge-dedede coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iac15e958e61be6e3c136fb9be18b4695823ad1c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* arch/x86: Make sure compiler knows we're stopping in hlt()Martin Roth2021-09-281-2/+3
| | | | | | | | | | | | Currently, static analyzers don't recognize that hlt() doesn't return, so they show errors like uninitialized variables assuming that it does return. This takes care of that problem. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia2325700b10fe1f89d749edfe5aee72b47d02f2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/dedede/var/galtic: Update PL1 min and max for Galith/GallopFrankChu2021-09-281-2/+2
| | | | | | | | | | | | | | Update PL1 min and max values to 6 W for Galith/Gallop systems. BUG=b:201010771 BRANCH=None TEST=Build and verify on Galith/Gallop system Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I0dfda3c2c830a2ce203668431f396859e782aa3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2374_01Ronak Kanabar2021-09-282-8/+8
| | | | | | | | | | | | | | | | | | | The headers added are generated as per FSP v2374_01. Previous FSP version was v2347_00. Changes Include: - Offset change in FspmUpd.h and FspsUpd.h BUG=b:201239436 BRANCH=None TEST=Build and boot brya Cq-Depend: chrome-internal:4150766 Change-Id: I097e854bcb4033bdaf2498fb97b255e87d3dd70f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57920 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/primus: modify HID to MX98360A for next build phaseMalik_Hsu2021-09-281-1/+1
| | | | | | | | | | | | | | | | For the next build phase, modify the HID of the speaker amp to MX98360A. BUG=b:199098681 BRANCH=none TEST=build coreboot without error Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0c318464fca7d35bbffd7ea0f5694b83acedff0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/baytrail: Always handle MRC as ELF fileAngel Pons2021-09-281-3/+6
| | | | | | | | | | | | | | | | | The current MRC binaries for Bay Trail are always ELF files. Always adjust the position in CBFS using the ELF header regardless of file names. Without adjusting the position, the system hangs right after calling into MRC. TEST: MRC position in CBFS does not change for bostentech/gbyt4. Change-Id: I74e1246a5fac3f3649be9842ff13c2fc70f72a20 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57989 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/kracko: refactor DPTF section for overridesRobert Chen2021-09-281-0/+56
| | | | | | | | | | | | | | Refactor DPTF section of code under the kracko overridetree. This makes kracko override dptf section of dedede/baseboard, because the DPTF tool's CRT, PSV and TSR3 settings are different than expected. BUG=b:187482019 BRANCH=dedede TEST=Built and tested on dedede system Change-Id: Iacc543f961a7f4652ee8583920b1794f916c7ec9 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/qualcomm/sc7280: Enable QUP drivers to use lz4 compressionShelley Chen2021-09-271-3/+3
| | | | | | | | | | | | BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B Change-Id: I3ec557bdf2286c3f60902d5ac018b536fe99afa3 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57896 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/baytrail: Drop invalid `VGA_BIOS_FILE` defaultAngel Pons2021-09-271-5/+0
| | | | | | | | | | | | This file does not exist in the coreboot tree. One should place this file in the `site-local` subdirectory and specify the paths by means of `site-local/Kconfig`. Change-Id: I86ac2a6176947f12194bec6b63bedd7db79820a0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* ec/purism: Remove copied code from system76Arthur Heymans2021-09-272-63/+2
| | | | | | | | | | This code is identical except for some renaming. Change-Id: I93795a6087ce0daca27c0d5038a1febd6ca9c775 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* arch/x86,cpu/x86: Move cpu_info initialization instructions into macroRaul E Rangel2021-09-273-14/+14
| | | | | | | | | | | | | | This will help reduce duplication and make it easier to add new members to the cpu_info struct. BUG=b:194391185, b:179699789 TEST=Compare assembly of romstage and ramstage before and after Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I31f264f4bb8b605fa3cb3bfff0d9bf79224072aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/57859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/cezanne/early_fch: move mb_set_up_early_espi into if blockFelix Held2021-09-271-2/+3
| | | | | | | | | | | | | mb_set_up_early_espi should only be called when SOC_AMD_COMMON_BLOCK_USE_ESPI is selected. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic8ad724a2a79c1995fbe9d97f11a0f69eed9435c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/amd/cezanne: Enable CCP DMAKarthikeyan Ramasubramanian2021-09-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Enable CCP DMA use in PSP verstage. This helps to reduce the boot time. BUG=b:194990811 TEST=Build and boot to OS in Guybrush. Observed a 35 - 40 ms improvement in the boot time. Before CCP DMA: 508:finished loading body 898,286 (287,576) Total Time: 2,146,182 After CCP DMA: 508:finished loading body 853,627 (240,061) Total Time: 2,110,117 Cq-Depend: chrome-internal:4116566 Change-Id: I6e4f081622a2ec78763adf56548204efc1bccf39 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/psp_verstage: Introduce boot device driverKarthikeyan Ramasubramanian2021-09-275-16/+102
| | | | | | | | | | | | | | | PSP verstage can access the boot device either in Programmed I/O mode or DMA mode. Introduce a boot device driver and use the appropriate mode based on the SoC support. BUG=b:194990811 TEST=Build and boot to OS in Guybrush. Change-Id: I8ca5290156199548916852e48f4e11de7cb886fb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57563 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 09:54:19 +0000