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* coreboot: Add support for include-what-you-useMartin Roth2022-10-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | The tool "include-what-you-use" analyzes each file's headers and makes recommendations for header files to add and remove. There are additional scripts as part of the package that will make these changes directly based on the recommendations, but due to the way coreboot compiles code in/out base on Kconfig options, this isn't really safe for the project to use. It is a good starting point though. To use, set the IWYU kconfig option, then build with the command: make -k Because this doesn't actually build any files, the -k option is needed or make will stop after looking at the first file. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I084813f21a3c26cac1e4e134bf8a83eb8637ff63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers/generic/cbfs-uuid: Add driver to include UUID from CBFSMichał Żygowski2022-10-113-0/+30
| | | | | | | | | | | | | | | When system_uuid CBFS file is present and contains the UUID in a string format, the driver will parse it and convert to binary format to populate the SMBIOS type 1 UUID field. TEST=Add UUID file and boot MSI PRO Z690-A DDR4 WIFI and check with dmidecode if the UUID is populated correctly. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I22f22f4e8742716283d2fcaba4894c06cef3a4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/64639 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Enable PD SyncSubrata Banik2022-10-111-1/+0
| | | | | | | | | | | | | | | This patch enables PD Sync for Rex. BUG=b:248775521 TEST=Able to boot Google/Rex with PD sync enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I749b5dea481c7546579e97f923f143dd17f831d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67819 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* brya: add new zydron variantDavid Wu2022-10-1013-1/+887
| | | | | | | | | | | | | | | Add a new zydron variant, which is a variant of brya's skolas baseboard. currently copy the variant file from kano. BUG=b:250787251 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I49a41678568daef80b7cd1e3ed60ce4763034f9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68130 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/i945/raminit.c: Fix formatted printElyes Haouas2022-10-101-1/+1
| | | | | | | | Change-Id: I7122988a1c88175a2e72c11bb95bfa434ce48ff2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68104 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/birman: Add framework for morgana crb birmanMartin Roth2022-10-1017-0/+832
| | | | | | | | | | | | birman is the reference board for the morgana SoC. It needs to be updated to match the actual board design as well. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I4b16854c954949217a76c3d4f04ddc4001f64337 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68196 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common: Remove buildtime error for unknown cpuMartin Roth2022-10-102-3/+7
| | | | | | | | | | | | | | | | | | | This is not critical functionality and doesn't need a build-time error. Having it as a build time error causes a chicken & egg issue where the chipset needs to be added before it can be added to this file, but the header file fails the build because the chipset is unknown. It's not practical to exclude these files from the new platform builds because the PSP functionality is thoroughly embedded into the coreboot structure. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ib02bbe1f9ffb343e1ff7c2bfdc45e7edffe7aaed Reviewed-on: https://review.coreboot.org/c/coreboot/+/68245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/amd/morgana: Add initial commit for new SoCMartin Roth2022-10-1059-0/+5728
| | | | | | | | | | | | | | This is an initial framework for the Morgana SoC. TODOs have been added to the files for both customization and commonization. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: If92e129db10d41595e1dc18a7c1dfe99d57790cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68195 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/mendocino/psp_verstage: Remove TODO commentKarthikeyan Ramasubramanian2022-10-081-2/+0
| | | | | | | | | | | | | | | PSP verstage has been successfully enabled and this makefile looks good. Hence removing a TODO comment. BUG=b:239090306 TEST=Build Skyrim BIOS image. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic3cd55171fd1e4d74fac72f0b0b92dc80e533b5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* mb/google/skyrim: Create frostflow variantChao Gui2022-10-084-0/+14
| | | | | | | | | | | | | | | | | | | Create the frostflow variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:240970782 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_FROSTFLOW Signed-off-by: Chao Gui <chaogui@google.com> Change-Id: I937e6562094968824e73bfa20390b3ec8b24dfa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/prodrive/hermes: Write reset cause regs to EEPROMAngel Pons2022-10-083-2/+41
| | | | | | | | | | Write the value for reset cause registers to the EEPROM for debugging. Change-Id: I827f38731fd868aac72103957e01aac8263f1cd3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67483 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/prodrive/hermes: Add part numbers to SMBIOSAngel Pons2022-10-083-5/+31
| | | | | | | | | | | | | Adjust the EEPROM layout to account for two new fields: board part number and product part number. In addition, put them in a Type 11 SMBIOS table (OEM Strings). Also, rename a macro to better reflect its purpose. Change-Id: I26c17ab37859c3306fe72c3f0cdc1d3787b48157 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67759 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/fsp: Add Morgana FSP vendorcodeMartin Roth2022-10-086-0/+816
| | | | | | | | | | | | | | Initial commit of the FSP-specific code for the Morgana SoC. This is just an initial framework and still needs to be updated to match the Morgana FSP. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ic53c59404f96c73c55eb2648113c5ced26d6e20c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* vc/amd/fsp: Make common directoryMartin Roth2022-10-088-0/+556
| | | | | | | | | | | | | | | The common directory is for files that shouldn't change, or shouldn't change much between platforms. These will be removed from other directories and used in upcoming commits. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I37ed98a67b066598fdebcc5b034e64dc639fda7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9750 for lisbonKevin Chiu2022-10-081-0/+1
| | | | | | | | | | | | | Enable DRIVERS_GENESYSLOGIC_GL9750 for lisbon BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I74cd634700b2de16ae471e0a738b67a14fd82a50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68168 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/starlabs/merlin: Add EC related files for Alder Lake boardsSean Rhodes2022-10-073-0/+459
| | | | | | | | | | | | Add EC memory layout and Q events for Intel Alder Lake based boards, the "StarBook Mk VI" and "StarFighter Mk I", which both use the ITE 5570E. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8cea386ba91d076084002738fe7041834deea311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/prodrive/hermes: Factor out serial reading logicAngel Pons2022-10-073-12/+15
| | | | | | | | | | | | | | | Add the `eeprom_read_serial()` function to read serials from the EEPROM. Note that there's only one buffer now: this means only one serial can be accessed at the same time, and the buffer needs to be cleared so that it does not contain old data from other serials. Given that the serials are copied one at a time into SMBIOS tables, having one shared buffer is not a problem. Change-Id: I5c9781e4e599043be756514cfd6dd86dedcf580c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67275 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/prodrive/hermes: Prevent SGPIO cross-powering 5V railAngel Pons2022-10-071-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCH's SGPIO pads are connected to a buffer chip that is powered from the always-on +3V3_AUX rail. For some cursed reason, when the SGPIO pads stay configured as SGPIO when a Poseidon system shuts down, voltage from the +3V3_AUX-powered buffer chip will leak into the +5V rail through the SATA backplane. Just pulling the SGPIO pads low before the system powers off stops the +5V rail from being cross-powered. This issue has only been observed in S5, but it's very likely other sleep states are affected as well. Thus, always pull the SGPIO pins low before entering ACPI S3 or deeper because the power supply will turn off in these states as well. TEST=Obtain a Poseidon system, verify that the +5V rail is cross-powered after going to S5. We measured 0.17V on our system, but voltages as high as 0.6V were measured on other systems. Verify that unplugging the SGPIO cable going to the SATA backplane results in the +5V rail voltage dropping to 0V, which indicates that the voltage leakage is exclusively coming from the SGPIO and SATA backplane. Finally, make sure that the +5V rail voltage drops to 0V after going into ACPI S5 with this patch applied and the SGPIO cable connected. Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/apollolake: Add UFS InterruptSean Rhodes2022-10-071-0/+3
| | | | | | | | | | | According to Intel document number 336561, GLK has UFS (0x1d), so add the PCI interrupt. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67680 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: Remove SD Card interrupt for GLKSean Rhodes2022-10-071-0/+2
| | | | | | | | | | | According to Intel document number 336561, G, SD Card (0x1b) does not exist on GLK, so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67679 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/siemens/mc_ehl2: Use preset driver strength for SD-CardMario Scheithauer2022-10-071-0/+8
| | | | | | | | | | | The intention of predefining driver strength is to avoid that the OS SD-Card driver changes this setting. Change-Id: I02fdac94462da1cd77f8dc972faf16f28d94c946 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* soc/intel/ehl: Set Ethernet controller to D0 power stateMario Scheithauer2022-10-071-0/+9
| | | | | | | | | | | | | | | | | | | To be able to change the MAC addresses, it is necessary that the controllers are in D0 power state. As of FSP MR3, Intel has set the controllers to D3 power state at the end of FSP-S TSN GbE initialization. This patch sets the state back to D0 before the programming of the MAC addresses. Test: - Build coreboot with FSP MR4 for mc_ehl2 mainboard - Boot into Linux and check MAC addr via 'ip a' Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHzLeo Chou2022-10-071-4/+4
| | | | | | | | | | | | | | | Change the TPM I2C freqeuncy to 1 MHz for pujjo. BUG=b:249953707 TEST=On pujjo, all timing requirements in the spec are met. Frequencies: pujjo - 987.80 kHz Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: If99b5022a9b67e9c63c440a1e398d56bb2c467e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/nissa/var/yaviks: Config I2C frequencyWisley Chen2022-10-071-1/+25
| | | | | | | | | | | | | | | | | | | Update parameters for all I2C devices. After applied this patch, the measured the I2C frequency meets spec BUG=b:249953708 TEST=FW_NAME=yaviks emerge-nissa coreboot flash and measure the all I2C devices 1. I2C0 (TPM): 980.6 Khz 2. I2C1 (TouchScreen); 392.6 Khz 3. I2C3 （Audio): 394.9 Khz 4. I2C5 (Touchpad): 391.6 Khz Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I33c2891f17bc3c572bbfcbf30bbbdef9eb850ce7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* soc/amd/{CZN,MDN,PCO}: Fix building with only single RW regionMatt DeVillier2022-10-076-8/+26
| | | | | | | | | | | | | | | | | | | apu/amdfw_a was only getting added to CBFS when VBOOT_SLOTS_RW_AB was selected, but needs to be added in the RW_A only case as well (VBOOT_SLOTS_RW_A). Since VBOOT_SLOTS_RW_AB selects VBOOT_SLOTS_RW_A, we can guard amdfw_a and _b separately and both will be added in the RW_AB case. TEST=build google/zork with VBOOT_SLOTS_RW_A or VBOOT_SLOTS_RW_AB selected, ensure amdfw_a and amdfw_b are added to correct CBFS regions as appropriate. Change-Id: Ic8048e869d7449eeb1ac10bfec4a5646b848d6a8 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68126 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfwMatt DeVillier2022-10-072-2/+2
| | | | | | | | | | | | | | | apu/amdfw should be restricted to the RO region only when building with VBOOT + any RW region (RW_A or RW_A + RW_B); it is not tied to ChromeOS in any way. Fix guarding to match newer AMD platforms (eg, CZN/MDN). TEST=build google/zork without CHROMEOS, with VBOOT_SLOTS_RW_A Change-Id: I32d7fa7a4b3d41107cfdba96128a4a75f7066c6f Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68125 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/alderlake: Support Raptor Lake VR Fast VMODEJeremy Compostella2022-10-072-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RaptorLake introduces the support of the Voltage Regulator Fast Vmode feature. When enabled, it makes the SoC throttle when the current exceeds the I_TRIP threshold. This threshold should be between Iccmax.app and Iccmax and take into account the specification of the Voltage Regulator of the system. This change provides a mean to: 1. Enable the feature via the `vr_config->enable_fast_vmode'. If no I_TRIP value is supplied FSPs picks an adapted I_TRIP value for the current SoC assuming a Voltage Regulator error accuracy of 6.5%. 2. Set the I_TRIP threshold via the `vr_config->fast_vmode_i_trip' field. These new fields are considered independent from the other `vr_config' fields so that the board configuration does not have to unnecessarily supply other VR settings to enable Fast VMode. Information about the Fast VMode Feature can be found in the following Intel documents: - 627270 ADL and RPL Processor Family Core and Uncore BIOS Specification - 724220 RaptorLake Platform Fast V-Mode - 686872 RaptorLake Lake U P H Platform BUG=b:243120082 BRANCH=firmware-brya-14505.B TEST=Read I_TRIP from the Pcode and verify consistency with a few `enable_fast_vmode' and `fast_vmode_i_trip' settings. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/66917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/skyrim: Override SPI flash bus speedKarthikeyan Ramasubramanian2022-10-073-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz starting the board version where required schematics update is done. BUG=b:245949155 TEST=Build and boot to OS in Skyrim with 100 MHz SPI bus speed. Perform warm and cold reboot cycles for 100 iterations each. Observe that the boot time improved by ~115 ms compared to 66 MHz SPI flash bus speed. At 66 MHz: 508:finished loading body 538,319 (83,806) 11:start of bootblock 1,196,809 (624,777) 14:finished loading romstage 1,236,905 (39,163) 970:loading FSP-M 1,237,056 (37) 15:starting LZMA decompress (ignore for x86) 1,237,073 (17) 16:finished LZMA decompress (ignore for x86) 1,358,937 (121,864) 8:starting to load ramstage 2,010,304 (0) 15:starting LZMA decompress (ignore for x86) 2,010,312 (8) 16:finished LZMA decompress (ignore for x86) 2,067,181 (56,869) 971:loading FSP-S 2,078,232 (7,999) 17:starting LZ4 decompress (ignore for x86) 2,078,253 (21) 18:finished LZ4 decompress (ignore for x86) 2,084,297 (6,044) 90:starting to load payload 2,316,933 (5) 15:starting LZMA decompress (ignore for x86) 2,316,947 (14) 16:finished LZMA decompress (ignore for x86) 2,339,819 (22,872) Total Time: 2,464,338 At 100 MHz: 508:finished loading body 515,118 (59,364) 11:start of bootblock 1,115,043 (566,110) 14:finished loading romstage 1,146,713 (29,697) 970:loading FSP-M 1,146,865 (38) 15:starting LZMA decompress (ignore for x86) 1,146,881 (16) 16:finished LZMA decompress (ignore for x86) 1,249,351 (102,470) 8:starting to load ramstage 1,900,568 (1) 15:starting LZMA decompress (ignore for x86) 1,900,576 (8) 16:finished LZMA decompress (ignore for x86) 1,956,337 (55,761) 971:loading FSP-S 1,967,357 (7,930) 17:starting LZ4 decompress (ignore for x86) 1,967,377 (20) 18:finished LZ4 decompress (ignore for x86) 1,972,925 (5,548) 90:starting to load payload 2,205,300 (6) 15:starting LZMA decompress (ignore for x86) 2,205,313 (13) 16:finished LZMA decompress (ignore for x86) 2,227,087 (21,774) Total Time: 2,349,804 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5e8db22151fbc2db1f9e81b3644338348160736d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* smbios: Add API to generate SMBIOS type 28 Temperature ProbeErik van den Bogaert2022-10-062-0/+81
| | | | | | | | | | | Based on DMTF SMBIOS Specification 3.5.0 Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com> Change-Id: I710124ca88dac9edb68aab98cf5950aa16c695d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67926 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: use predicate to check if pci device is on n-th busFabio Aiuto2022-10-067-7/+7
| | | | | | | | | | | | | use function to check if pci device is on a particular bus number. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I4a3e96381c29056de71953ea2c39cd540f3df191 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68103 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: use predicates to check for enabled pci devicesFabio Aiuto2022-10-0610-11/+11
| | | | | | | | | | | | | use functions to check for pci devices instead of open-coded solution. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device_util.c: add predicates for pci devicesFabio Aiuto2022-10-062-0/+18
| | | | | | | | | | | | | add functions to check whether a device is enabled pci device or a pci device on a specific bus number. TEST: compile and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I3257c8404017372f6cdd9f6cf9453502447343a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68101 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/mithrax: adjust I2C5 times for TPJohn Su2022-10-061-1/+6
| | | | | | | | | | | | | | | | | | | | This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5 to follow I2C specification. I2C_TCHPAD_SCL high period time is from 0.53 us to 0.6952 us. I2C_TCHPAD_SDA hold time is from 0.13 us to 0.4623 us. BUG=b:249031186 BRANCH=brya TEST=EE check OK with test FW and TP function is normal. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I5977f0dbba8924cc8a1c72c36358d6ba6f2de940 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67920 Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
* mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization errorLeo Chou2022-10-061-0/+45
| | | | | | | | | | | | | Configure eMMC DLL tuning values for Pujjo board. BUG=b:241854926 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ic36c817fa546741e394668297ca43db3a45ee105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68095 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/t440p: Enable PCI 00:01.1 bridge for dGPUNico Huber2022-10-061-2/+2
| | | | | | | | | | | | | | | | | An optional dGPU can be connected to the second PEG bridge: -[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller +-01.0-[01]-- +-01.1-[02]----00.0 NVIDIA Corporation GK208M [GeForce GT 730M] It's possible that the 01.0 bridge is never populated, but we have to leave it on anyway so 01.1 can be enumerated. Change-Id: Ieab7a7bf3b31b4ee9d9f12b5d827d866c87356e1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/kontron/bsl6: Set board type to mobile for memory configNico Huber2022-10-061-0/+2
| | | | | | | | | | | Given the embedded nature, the Halo SKU, SO-DIMMs and 1 DIMM per channel, `mobile` seems to come closest. Change-Id: Ia27f1e4dec0a0d06be3d8c08bfe82becd41a2149 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/nissa/var/pujjo: Disable stylus GPIO pins based on fw_configLeo Chou2022-10-061-0/+12
| | | | | | | | | | | | BUG=b:250470706 TEST=Boot to OS on pujjo and check that stylus GPIO are configured based on fw_config. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I4218748cb06426a918d89f688599c652062ac78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68075 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake/acpi: Add PCIEXBAR to MCHCSean Rhodes2022-10-061-2/+6
| | | | | | | | | | | | The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/skyrim: Fix SMMSTORE size, alignmentMatt DeVillier2022-10-061-1/+1
| | | | | | | | | | | | SMMSTOREv2 requires 64k min size, 64k alignment. TEST=build skyrim with SMMSTOREv2 enabled Change-Id: I3501b6036df9ee1049a92e26a7b72e53b4604f60 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/guybrush: Fix SMMSTORE size, alignmentMatt DeVillier2022-10-061-1/+1
| | | | | | | | | | | | SMMSTOREv2 requires 64k min size, 64k alignment. TEST=build guybrush with SMMSTOREv2 enabled Change-Id: I78cb873a5634c659067367260cc7063fbd60d77a Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/meteorlake: Make use of is_devfn_enabled() functionSridhar Siricilla2022-10-063-12/+6
| | | | | | | | | | | | | | The patch uses is_devfn_enabled() function to enable the TBT PCIe ports through FSP-M and FSP-S UPDs. Also, removes unused tbt_pcie_port_disable array member from soc_intel_meteorlake_config struct. TEST=Build coreboot for Google/Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie55e196bd8f682864b8f74dbe253f345d7184753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* mb/starlabs/lite/glkr: Enable configuring Fast Charging on the Lite Mk IVSean Rhodes2022-10-063-0/+6
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I714867d455c4e0d01d6cb1cb9dc64669fb41100c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ec/starlabs/merlin: Add support for enabling fast chargeSean Rhodes2022-10-0612-0/+50
| | | | | | | | | | | | | | | The Lite Mk IV's can enable fast charging, with support up to 100W via USB-C PD 3.0. The default for this is disabled, as it can reduce battery life span. This patch adds the option to enable fast charging, by writing 0x01 to 0x18 in the EC space. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie01eb59d3f41b242190973fd9c58b1494320c12a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/lite: Add variant specific cmos.layout and cmos.defaultSean Rhodes2022-10-063-0/+126
| | | | | | | | | | | Add variant specific cmos files, which avoid options like "FastCharge" existing in platforms that don't support such options. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04264cf72d47ef719acfd144d8bf9acb0ceccc11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/starlabs/starbook: Add variant specific cmos.layout and cmos.defaultSean Rhodes2022-10-065-6/+137
| | | | | | | | | | | | | | | Add variant specific cmos files, which avoid options like "Thunderbolt" existing in platforms that don't support such options. This change also removes entries that were never used, including: * smi_handler * usb_always_on Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I359e5c5bbf29eb474f2d3bc42a8e80afc0a5d38a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/intel/common/gpio.c: Clean up includesElyes Haouas2022-10-061-3/+2
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Iba746431496b30daba098716337b688314eac283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* sb/intel/i82801gx/bootblock.c: Clean up includesElyes Haouas2022-10-061-1/+2
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I61d4a188dc9526b71277c05dd317255fc9727414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* sb/intel/i82801gx/early_init.c: Include common/rcba.hElyes Haouas2022-10-061-1/+3
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I5d9bc4ae942ba171a5d3ef4f77da69398fbac692 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* lib/prog_loaders.c: Clean up includesElyes Haouas2022-10-061-2/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I00e9636fa49c402f38119ba0bfc85c8c193fec12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* lib/prog_ops.c: Add <types.h>Elyes Haouas2022-10-061-0/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ibacf704d362eecea3f7216ffcb02c2ef6f9a6d8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 02:31:35 +0000