| Commit message (Collapse) | Author | Age | Files | Lines |
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Some LPC debug boards hard strap SIO address to be at
0x164e/0x164d vs 0x4e/0x4d. Add support for configurable
SIO address to support these cards.
BUG=b:159933344
TEST=boot with LPC debug card, verify serial output
Change-Id: I103c61f21f13970dfa3b9a788b29964e478fb84c
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add H5ANAG6NCJR-XNC.
BUG=b:165461530
BRANCH=volteer
TEST=emerge-volteer coreboot
Change-Id: I827158ce0abe764f1e3b5de46abf50dc148a6ff0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Save for the IO_APIC2_ADDR definition, they are equivalent.
Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47408
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only two definitions are actually used somewhere, the rest is unused.
Change-Id: Iec52d0d47fce6a1ec5455b670824b995a7a34a4c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47407
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Hook up the mainboard_ops driver and configure the GPIOs using .init,
since mainboard_silicon_init_params() is meant for the configuration of
the FSP, not the GPIOs.
Change-Id: I82f1eaf6693d9b117fb211776047058cdc787288
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Id73a7385f7701920efebaa3e293ac50a6ba93272
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47849
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace hard-coded IDs with defines introduced in CB:47807.
Used documents:
- 328904-003
- 329003-003
Built lenovo/t440p with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I910ab356dd8728c316018989bfb2689d4c67c2dc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47808
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Used documents:
- 328904-003
- 329003-003
Change-Id: I95790cda6f7c42a9de57bf5e92eb829ee1807dbe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47807
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This option only applies to boards using the Lenovo H8 EC code.
Change-Id: I3b16a61a0aa9f51a4061b1b5e58fc276e7383415
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47150
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only Sandy Bridge MRC stores scrambler seeds in CMOS. Non-Sandybridge
boards ended up with these entries because of copy-paste programming.
Change-Id: I5a5bda6ea4e63ba03a4219bb2a6aa546bb6ecd7a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47149
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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update the DPTF parameters received from the thermal team.
BUG=b:167523658
TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SMI handler was not installed for Xeon_sp platforms. This enables SMM
relocation and SMI handling.
TESTED:
- SMRR are correctly set
- The save state revision is correct (0x00030101)
- SMI's are properly generated and handled
- SMM MSR save state are not supported, so relocate SMM on all cores
in series
- Verified on OCP/Deltalake mainboard.
NOTE:
- Code for accessing a CPU save state is not working for SMMLOADERV2,
so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS
pointer are not supported.
- This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS
is broken and needs to be fixed separately. It is unknown if TCO is
supported. This might require a cleanup in the future.
Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TCO is configured by FSP. This mostly makes it possible to report TCO
events in SMM if enabled.
Change-Id: I4f81c7888e45ed01ee68b1d6e6a9986a4d735467
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47764
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The soc code was already there but it was never linked.
Change-Id: I75ee08dab524bc40f1630612f93cbd42025b6d4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47763
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds three settings for the new sd readers.
The new assigned values are:
1. RTS5227S: 3
2. L9750: 4
3. SD_OZ711LV2LN: 5
BUG=b:173676531
BRANCH=volteer
TEST=abuild -t google/volteer
Change-Id: I595695f99d3298f146fcdb7c2b942ce007ae9327
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Allows advertising support for a 1ch array DMIC in the NHLT table.
Boards use the NHLT if a microphone is connected to the DSP.
Tested on an Acer Aspire VN7-572G (Skylake-U) on Windows 10.
A custom ALSA topology will be required for Linux.
Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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According to the NHLT specification[1], PDM_DEV is defined as "1" on
Kabylake based platforms. coreboot currently sets it to "0" on
all platforms. Add an entry to the enum and use it to define
NHLT_PDM_DEV for Kabylake.
"Device Type" will resume from "2" on all platforms, but entries are
currently reserved.
Tested on an Acer Aspire VN7-572G (Skylake-U), which has a 1ch array
DMIC, on Windows 10.
1. https://01.org/sites/default/files/595976_intel_sst_nhlt.pdf
Change-Id: Ifbc67228c9e7af7db5154d597ca8d67860cfd2ed
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45010
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow the example of newer AMD code for Stoneyridge and Picasso.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Following the example of CB:7630 done for family16kb boards
(git commit 3ff4f85ccd9fdb7cd4885a10f025b5ab297a445f).
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ic48c7475ceadb60f825ca9e3c3427c8a7525a266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0".
correct rx_vref_tune -> tx_vref_tune
BUG=None
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Code was copy-pasted from older chips and has no effect on Lynxpoint.
Change-Id: I2c789ba48f175b3c9c9643118fc2209c94f24c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I93e09fc9801f6d32cade351bac0cba82f671acfe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: siemens-bot
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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TEST=Boot with an i3-9100F and see no vr_config errors.
Change-Id: Ic62ef038ad11d147a38804f694d3e056611b96db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47445
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on Intel Harcuvar CRB, SMMSTORE is now working.
Change-Id: I996c7bf3b510a8f0a9d1bb7d945ce777b646448e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Split up gpio.h into two seperate compilation units, gpio.c and
gpio_early.c, containing the complete configuration and a minimal
configuration used in early stages.
Tested on clevo/l140cu and it still boots.
Change-Id: I5b056e8faac0c426a37501dbc175373c22dde339
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Get rid of cnl_configure_pads() since it is a hack for the FSP. Instead,
hook up to the mainboard_ops driver and configure the GPIOs using .init.
Tested on clevo/l140cu and it still boots.
Change-Id: I75dd15ab6d2b3b72b3ad0398df87b349fd00bc3c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ifca49c656f259b08fb8ab47fe36e93c146f25266
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I50be3d9b829f624cbe460060c40482047f39774c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Move hda_verb.c from the variant's Makefile to the mainboard's Makefile,
because every variant needs one.
Change-Id: Ia94813f68620abcff48de4fdb117466c91f6863c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47820
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Time has shown that using spaces never converges into proper alignment.
Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Most of these comments have been copy-pasted or serve no purpose other
than to eventually turn into misleading info. While the description of
the first 120 bits of CMOS could be useful, it should instead be added
to the documentation for the CMOS option infrastructure, or /dev/null.
Moreover, trim down newlines to no more than two consecutive newlines.
Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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UART0_RX: C8 -> H10
UART0_TX: C9 -> H11
GPIO PIN Mode: NF1 -> NF2
Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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List of changes:
1. Configure CTRLCLK and CTRLDATA for HDMI
2. Enable Ddc and HPD for Port-B
3. Disable dual eDP configuration for Port-A and B
TEST=Able to see depthcharge pre-boot screens over HDMI-B port.
Change-Id: I7509b981f35fc60a7885b2b07067cb0d35ec625f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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According to the latest Alderlake Platform FSP Integration Guide, the
minimum amount of stack needed for FSP-M is 512KiB. Change
DCACHE_RAM_SIZE and DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB
previously determined empirically).
TEST=Able to pass FSP-M MRC training on LPDDR5 SKU without any hang.
Change-Id: Ic831ca9110a15fdb48ad31a7db396740811bf0f2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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UART bars
BAR address used during early initilization of GPSI 2 is overlapping with UART bar.
//For GSPI2 this is the address calculated
GSPI_BUS_BASE(0xFE030000,2)=0xFE032000
GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)
//overlaps with
CONSOLE_UART_BASE_ADDRESS -> 0xfe032000
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3249a91df8a2e319aff6303ef9400e74163afe93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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UART bars
BAR address used during early initilization of GPSI 2 is overlapping with UART bar.
//For GSPI2 this is the address calculated
GSPI_BUS_BASE(0xFE030000,2)=0xFE032000
GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)
//overlaps with
CONSOLE_UART_BASE_ADDRESS -> 0xfe032000
Change-Id: Id9f2140a6dd21c2cb8d75823cc83cced0c660179
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Implements the monotonic timer using the am335x dmtimer peripheral.
Change-Id: I4736b6d3b6e26370be9e8f369fc02285ad519223
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44383
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enables the MMU primarily to allow the unaligned word reads that the
FMAP code requires. Without enabling this, the chip gets data access
exceptions.
Enabling the MMU also gives some advantages in allowing the icache and
dcache to be enabled, so is probably worth doing regardless.
Change-Id: Ic571570cc44b0696ea61cc76e3bce7167a3256cf
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Override SMBIOS type 4 cpu voltage. For Delta Lake, 1.6V is expected.
Tested=Execute "dmidecode -t 4" to check if cpu voltage is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I0ecbec8fb3dc79b8c3f3581d6193aade01bcd68e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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Introduce a weak function to let the platform code provide the processor
voltage in 100mV units.
Implement the function on Intel platforms using the MSR_PERF_STATUS msr.
On other platforms the processor voltage still reads as unknown.
Tested on Intel CFL. The CPU voltage is correctly advertised.
Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Based on USB DB report.
BRANCH=puff
BUG=b:163561808
TEST=build and measure by EE team.
Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
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These files are not used by any platform, so remove them.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I75651d2cc53fc5a3cb3233686ad66881d129312d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Remove the following devices
- Goodix Touchscreen
- SAR0 Proximity Sensor
BUG=b:173480406
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I6b56ca136533b53ff7e003a665be67fbe12c1ade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47690
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Subitem for VENDORCODE_ELTAN_VBOOT and VENDORCODE_ELTAN_MBOOT are
always displayed.
Add dependency and display these items when feature is enabled only.
Tested on Facebook FBG1701.
Change-Id: I51e47efddbcf51d87439bec33b85432da56fa4c6
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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As preparation to a full PPI implementation move the acpi code out
of the pc80/tpm/tis driver into the generic tpm driver folder.
This doesn't change any functionality.
Change-Id: I7818d0344d4a08926195bd4804565502717c48fa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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VENDORCODE_ELTAN items are only used when USE_VENDORCODE_ELTAN is enabled.
Add dependency of USE_VENDORCODE_ELTAN.
Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The CPX FSP-T does not respect the FSP2.x spec and uses registers where
coreboot has its initial timestamp stored.
If the initial timestamp is later than some other timestamps this
messes up the timestamps 'cbmem -t' reports as it thinks they are a
result from a timestamp overflow (reporting that it took 100k years to
boot).
TEST: The ocp/deltalake boots within the span of a lifetime.
Change-Id: I4ba15decec22cd473e63149ec399d82c5e3fd214
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This CL add droid lte sku 37 38 39 40 to load wifi_sar-droid.hex.
BUG=none
BRANCH=octopus
TEST=emerge-octopus coreboot
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I55dda85b8f3e664d97834b712a2c6a48d1434010
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47697
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If9d1e28ac50b8ca227b2c09dbbfdd3c9b60aca6a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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