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* UefiCpuPkg: Apply uncrustify changesMichael Kubacki2021-12-071-4/+18
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiCpuPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Delete CPU_FEATURE_[BEFORE|AFTER]Ray Ni2020-02-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1366 Commit b3c71b472dff2c02f0cc38d7a1959cfb2ba8420d supported MSR setting in different scopes. It added below macro: CPU_FEATURE_THREAD_BEFORE CPU_FEATURE_THREAD_AFTER CPU_FEATURE_CORE_BEFORE CPU_FEATURE_CORE_AFTER CPU_FEATURE_PACKAGE_BEFORE CPU_FEATURE_PACKAGE_AFTER And it re-interpreted CPU_FEATURE_BEFORE as CPU_FEATURE_THREAD_BEFORE and CPU_FEATURE_AFTER as CPU_FEATURE_THREAD_AFTER. This patch retires CPU_FEATURE_BEFORE and CPU_FEATURE_AFTER completely. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Remove XD enable/disable logicRay Ni2019-11-131-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2329 XD (ExecutionDisable) feature, when turned on, allows page table entry BIT63 set to 1 indicating the memory pointed by the page table is disallowed to execute. DxeIpl::CreateIdentityMappingPageTables() enables the XD when CPU supports it. Later DxeCore modifies the page table to set the BIT63 to protect the stack/heap to disallow code execution in stack/heap. UefiCpuPkg/CpuCommonFeaturesLib enables/disables the XD feature according to PcdCpuFeaturesSetting. When XD is disabled, GP fault is generated immediately because some page entries have BIT63 set. To fix this issue, this patch removes the XD feature logic from UefiCpuPkg/CpuCommonFeaturesLib so the XD feature is only taken care of by DxeIpl. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.Dong, Eric2019-08-211-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 Below code is current implementation: if (MsrRegister[ProcessorNumber].Bits.Lock == 0) { CPU_REGISTER_TABLE_WRITE_FIELD ( ProcessorNumber, Msr, MSR_IA32_FEATURE_CONTROL, MSR_IA32_FEATURE_CONTROL_REGISTER, Bits.Lock, 1 ); } 1. In first normal boot, the Bits.Lock is 0, 1 will be added into the register table and then will set to the MSR. 2. Trig warm reboot, MSR value preserves. After normal boot phase, the Bits.Lock is 1, so it will not be added into the register table during the warm reboot phase. 3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is not added in register table, so it's still 0 after resume. This is not an expect behavior. The expect value is the value should always 1 after booting or resuming from S3. The root cause for this issue is 1. driver bases on current value to insert the "set value action" to the register table. 2. Some MSRs may reserve their value during warm reboot. The solution for this issue is using new added macros for the MSRs which preserve value during warm reboot. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg CpuCommonFeaturesLib: Enhance Ppin codeStar Zeng2019-07-161-1/+1
| | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1961 Enhance Ppin code to enable and unlock for TRUE State, and disable and lock for FALSE State. Note: enable and lock could not be set both. According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP, and writing 1 to LockOut is permitted only if Enable_PPIN is clear. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg CpuCommFeaturesLib: Reduce to set MSR_IA32_CLOCK_MODULATIONStar Zeng2019-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1810 This patch covers two problems. 1. Current code gets CPUID_THERMAL_POWER_MANAGEMENT in ClockModulationInitialize() and uses its ECMD bit for all processors. But ClockModulationInitialize() is only executed by BSP, that means the bit is just for BSP. It may have no functionality issue as all processors may have same bit value in a great possibility. But for good practice, the code should get CPUID_THERMAL_POWER_MANAGEMENT in ClockModulationSupport (executed by all processors), and then use them in ClockModulationInitialize() for all processors. We can see that Aesni.c (and others) have used this good practice. 2. Current code uses 3 CPU_REGISTER_TABLE_WRITE_FIELD for MSR_IA32_CLOCK_MODULATION in ClockModulationInitialize(), they can be reduced to 1 CPU_REGISTER_TABLE_WRITE64 by getting MSR_IA32_CLOCK_MODULATION for all processors in ClockModulationSupport() and then update fields for register table write in ClockModulationInitialize(). We may argue that there may be more times of MSR_IA32_CLOCK_MODULATION getting. But actually the times of MSR_IA32_CLOCK_MODULATION getting could be also reduced. The reason is in ProgramProcessorRegister() of CpuFeaturesInitialize.c, AsmMsrBitFieldWrite64 (AsmReadMsr64 + AsmWriteMsr64) will be used for CPU_REGISTER_TABLE_WRITE_FIELD, and AsmWriteMsr64 will be used for CPU_REGISTER_TABLE_WRITE64. The times of MSR accessing could be reduced with this patch. Without the patch: 3 CPU_REGISTER_TABLE_WRITE_FIELD (in ClockModulationInitialize) ==> 3 AsmMsrBitFieldWrite64 ==> 3 AsmReadMsr64 + 3 AsmWriteMsr64 With the patch: 1 AsmReadMsr64 (in ClockModulationSupport) + 1 CPU_REGISTER_TABLE_WRITE64 (in ClockModulationInitialize) ==> 1 AsmWriteMsr64 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg CpuCommFeaturesLib: Fix ASSERT if LMCE is supportedStar Zeng2019-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1829 There will be ASSERT if LMCE is supported as below. DXE_ASSERT!: [CpuFeaturesDxe] XXX\UefiCpuPkg\Library\CpuCommonFeaturesLib\MachineCheck.c (342): ConfigData != ((void *) 0) The code should get Config Data and FeatureControlGetConfigData could be used. This issue is there since the code was added at the commit below. Revision: 3d6275c1137c9633ce24e31522b71105367bd6a0 Date: 2017/8/4 8:46:41 UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature. The commits below are also related to move the code. Revision: 023387144299741d727521b425ef443438aecc1f Date: 2017/9/1 10:12:38 UefiCpuPkg/Lmce.c Remove useless file. Revision: 306a5bcc6b0170d28b0db10bd359817bb4b1db9f Date: 2017/8/17 11:40:38 UefiCpuPkg/CpuCommonFeaturesLib: Merge machine check code to same file. So, the code may not be tested at all on a platform that supports LMCE. BTW: A typo in LmceInitialize is also fixed. The typo is introduced by the commit below. Revision: d28daaddb3e732468e930a809d3d3943a5de9558 Date: 2018/10/17 9:24:05 UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-091-7/+1
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Enable Processor Trace feature.Eric Dong2017-08-041-0/+11
| | | | | | | | Cc: Jeff Fan <jeff.fan@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature.Eric Dong2017-08-041-0/+12
| | | | | | | Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg CpuCommonFeaturesLib: Enable Ppin feature.Eric Dong2017-07-201-0/+11
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg CpuCommonFeaturesLib: Fix smx/vmx enable logic error.Eric Dong2017-07-121-16/+3
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed: Jeff Fan <jeff.fan@intel.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Support X2APIC enableJeff Fan2017-05-271-1/+1
| | | | | | | | | | | | | | | Current X2APIC is enabled in MpInitLib (used by CpuMpPei and CpuDxe) to follow SDM suggestion. That means we only enable X2APIC if we found there are any initial CPU ID value >= 255. This patch is to provide one chance for platform to enable X2APIC even there is no any initial CPU ID value >= 255. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuFeatures: Change files format to DOSJeff Fan2017-04-051-227/+227
| | | | | | Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg: Add NULL CPU Common Features Library instanceJeff Fan2017-03-221-0/+227
This NULL CPU common Features Library instance will register some CPU features defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR). Add PCD PcdCpuClockModulationDutyCycle and PcdIsPowerOnReset consumed by NULL CPU Common Features Library instance. v2: 1. Using MSR_IA32_EFER to enable/disable NX feature instead of using MSR_IA32_MISC_ENABLE. 2. Fix bug that SMX and VMX feature is swapped. v3: 1. Add AesniGetConfigData() to get current register state. v5: Move MSR reading from AesniGetConfigData() to AesniSupport(). Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
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