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* Introduce an `include` directory for header filesThomas Heijligen2022-04-291-220/+0
| | | | | | | | | | | | Move all header files to the new `include` directory. Adapt include directives and build systems to the new directory. Change-Id: Iaddd6bbfa0624b166d422f665877f096983bf4cf Signed-off-by: Felix Singer <felix.singer@secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi25_statusreg: delete spi_read_status_register()Nikolai Artemiev2022-04-051-2/+0
| | | | | | | | | | | | | | | | | | | | | | | Delete the spi_read_status_register() function because the generic spi_read_register() function can be used instead. This patch also converts all call sites over to spi_read_register(). A side effect is that error codes are now properly propagated and checked. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=Tested with a W25Q128.W flash on a kasumi (AMD) dut. Read SR1/SR2 with --wp-status and activated various WP ranges that toggled bits in both SR1 and SR2. Change-Id: I146b4b5439872e66c5d33e156451a729d248c7da Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/59529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* flashchips,writeprotect_ranges: add range decoding functionNikolai Artemiev2022-03-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow chips to specify functions that map status register bits to protection ranges. These are used to enumerate available ranges and determine the protection state of chips. The patch also adds a range decoding function for the example chips. Many other chips can also be handled by it, though some will require different functions (e.g. MX25L6406 and related chips). Another approach that has been tried in cros flashrom is maintaining tables of range data, but it quickly becomes error prone and hard to validate. Using a function to interpret the ranges allows compact encoding with most chips and is flexible enough to allow chips with less predictable ranges to be handled as well. BUG=b:195381327,b:153800563 BRANCH=none TEST=dumped range tables, checked against datasheets Change-Id: Id163ed80938a946a502ed116e48e8236e36eb203 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi25_statusreg: make register read/write functions genericNikolai Artemiev2022-02-281-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new spi_{read,write}_register() functions that take the source/destination register as an argument. Currently they can only access SR1, support for other registers will be added in another patch. Since we're refactoring things, this commit also makes spi_read_register() return an error code, making it possible to identify error conditions that spi_read_status_register() concealed. This also removes the initial 100ms delay between writing a register and the first attempt to check the chip's status. An initial delay was added to avoid needing to read the status register multiple times, but that is unlikely to cause problems on modern flash chips. BUG=b:195381327,b:153800563 BRANCH=none TEST=flashrom -{r,w,E} TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series Change-Id: I0a3951bbf993f2d8d830143b29d3ce16cc6901d7 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/58475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* chipdrivers.h: Trivial fix style of write_28sf040() signatureEdward O'Callaghan2020-12-201-1/+1
| | | | | | | | | | | | This is correct on the Chromium side so fix the missing space here. Change-Id: I9dd27a4d8a1b87ce96b2a3f8cbe80f40c79b0354 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* s25f.c: implement probing and block erasers for SpansionNikolai Artemiev2020-12-031-0/+5
| | | | | | | | | | | | | | | | | | | | | | This adds support for Spansion 25Fxxxxx chips. These chips require their own probing logic because the first 6 bytes returned by RDID must be examined to identify the chip. New erase functions are required as the chips support multiple sector layouts, and the default layout must be changed to be able to erase the entire flash. Adapted from cros flashrom at `9c4c9a56b6a0370b383df9c75d71b3bd469e672d`. BUG=b:153800073 TEST=builds Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: I2d23f9c36ce8b2959807fbeee7f60e02444e3763 Reviewed-on: https://review.coreboot.org/c/flashrom/+/46140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* support variable-size SPI chip for dummy programmerNamyoon Woo2020-09-071-0/+3
| | | | | | | | | | | | | | | | | | | This is designed for firmware updater to pack firmware image preserving some specific partitions in any size. BUG=none TEST=ran the command line below: $ flashrom -p dummy:image=${TMP_FILE},size=16777216, \ emulate=VARIABLE_SIZE -w ${IMG} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=auto, \ emulate=VARIABLE_SIZE -w ${IMG} -V -f Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Iff266e151459561b126ecfd1c47420b385be1db2 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Revert "flashchips: port S25FS(128S) chip from chromiumos"Nico Huber2020-05-011-7/+1
| | | | | | | | | | | | | | | | | | | | | This reverts commit a3519561bd0fb44153bb376322b799000657576f. Breaks support for most SPI flash chips. It's too big and too invasive to be reviewed as a single commit. The changes to `spi_poll_wip():spi25.c` were not noticed in the original review that were from the similarly named function and file `s25f_poll_status():s25f.c` in the downstream Chromium fork. V.2: Rebase and rephrase commit msg to reflect how the issue slipped in. Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* const'ify flashctx to align signatures with cros flashromEdward O'Callaghan2020-04-301-2/+2
| | | | | | | | | | | | | | | | The ChromiumOS flashrom fork has since const'ify flashctx in a few places. This aligns the function signatures to match with downstream to ease forward porting patches out of downstream back into mainline flashrom. This patch is minimum viable alignment and so feedback is welcome. Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: port S25FS(128S) chip from chromiumossibradzic2020-04-221-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This may seem too big just to support yet another flash chip, but in reality it brings support for whole new family of S25FS Spansion/Cypress flash chips. These chips require handling of some special status registers for erasing or writing, with very specific timing checks in place. For example, WIP status bit will remain being set to 1 if erase or programming errors occur, and in that case chip 'software reset' has to be performed otherwise the chip will remain unresponsive to all further commands. Also, special CR3NV register (Configuration Register 3 Nonvolatile) status bits needs to be read and set by using RDAR (ReaD Any Register) and WRAR (WRite Any Register) OP commands, and these states are needed to determine which type of reset feature is enabled at the time (legacy or S25FS type) in the first place, determine whether Uniform or Hybrid sector architecture is used at the time, or set programming buffer address wrap point (256 or 512 bytes). Furthermore, S25FS chip status register has to be restored to its original state (hence that ugly CHIP_RESTORE_CALLBACK) following erasing or writing, failing to do so may result in host being unable to access data on the chip at all. Finally, although this brings support for the whole family of chips, I only have one such chip to do the actual testing, S25FS128S (Small Sectors), which I had fully tested on ch341a and FT4232H programmers, with confirmed working probe, read, erase and write. Full summary of changes are here: flashchips: add new flashchip sctructure property: .reset add chip definitions: S25FS128S Large Sectors S25FS128S Small Sectors flash: add macro (chip_restore_func_data call-back): CHIP_RESTORE_CALLBACK flashrom: add struct: chip_restore_func_data add call-back function: register_chip_restore spi: add OP codes: CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST add register bit function definitions: CR3NV_ADDR, CR3NV_20H_NV add timers: T_W, T_RPH, T_SE spi25: refactor (based on chromiumos implementation) function: spi_poll_wip port these functions from chromiumos: probe_spi_big_spansion s25fs_software_reset s25f_legacy_software_reset s25fs_block_erase_d8 spi25_statusreg: port these functions from chromiumos: spi_restore_status s25fs_read_cr s25fs_write_cr s25fs_restore_cr3nv Most of the ported functions are originally from s25f.c found at https://chromium.googlesource.com/chromiumos/third_party/flashrom with exception of spi_restore_status which is defined in spi25_statusreg.c. The rest of macros and OP codes are defined in same files as in this commit. Change-Id: If659290874a4b9db6e71256bdef382d31b288e72 Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Add support for M95M02-A125Konstantin Grudnev2019-10-041-0/+4
| | | | | | | | | | | | Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64 Signed-off-by: Konstantin Grudnev <grudnevkv@gmail.com> Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b Reviewed-on: https://review.coreboot.org/c/flashrom/+/34496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* dediprog: Implement 4BA EAR mode for protocol v1Nico Huber2019-06-041-0/+1
| | | | | | | | | | | | | | With an SF100 and protocol version 1, using the extended address register of the flash chip seems safe. Make use of that and remove the broken 4BA modes flag. Tested with SF100 V:5.1.9 and W25Q256FV. Change-Id: If926cf3cbbebf88231116c4d65bafc19d23646f6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/32016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Add SST26VF016B(A), SST26VF032B(A), SST26VF064B(A)Wei Hu2018-05-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch seems to have originally been from https://patchwork.coreboot.org/patch/4126/ . The most recent version seems to be in OpenEmbedded (commit 503a572) which added support for 16Mbit and 32Mbit variants. The OpenEmbedded patch also makes changes to linux_spi.c to add some debug prints which are omitted in this version. From the original commit message: Differences between SST26 and SST25: 1. The WREN instruction must be executed prior to WRSR [Section 5.31]. There is no EWSR. 2. Block protection bits are no longer in the status register. There is a dedicated 144-bit register [Table 5-6]. The device is write-protected by default. A Global Block-Protection Unlock command unlocks the entire memory [Section 4.1]. Change-Id: Ib019bed8ce955049703eb3376c32a83ef607c219 Signed-off-by: Wei Hu <wei@aristanetworks.com> Signed-off-by: David Hendricks <david.hendricks@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Reviewed-on: https://review.coreboot.org/25962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-5/+0
| | | | | | | | Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add support for the ENE Embedded Debug Interface EDI and KB9012 ECPaul Kocialkowski2018-02-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | The ENE Embedded Debug Interface (EDI) is a SPI-based interface for accessing the memory of ENE embedded controllers. The ENE KB9012 EC is an embedded controller found on various laptops such as the Lenovo G505s. It features a 8051 microcontroller and has 128 KiB of internal storage for program data. EDI can be accessed on the KB9012 through pins 59-62 (CS-CLK-MOSI-MISO) when flash direct access is not in use. Some firmwares disable EDI at runtime so it might be necessary to ground pin 42 to reset the 8051 microcontroller before accessing the KB9012 via EDI. The example of flashing KB9012 at Lenovo G505S laptop could be found here: http://dangerousprototypes.com/docs/Flashing_KB9012_with_Bus_Pirate Change-Id: Ib8b2eb2feeef5c337d725d15ebf994a299897854 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/23259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* spi25: Revise decision when to enter/exit 4BA modeNico Huber2018-01-021-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of arbitrarily deciding whether to enter 4BA mode in the flash chip's declaration, advertise that entering 4BA mode is supported and only enter it if the SPI master supports 4-byte addresses. If not, exit 4BA mode (the chip might be in 4BA mode after reset). If we can't assure the state of 4BA mode, we bail out to simplify the code (we'd have to ensure that we don't run any instructions that can usually be switched to 4BA mode otherwise). Two new feature flags are introduced: * FEATURE_4BA_ENTER: Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN. * FEATURE_4BA_ENTER_WREN Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN. FEATURE_4BA_SUPPORT is dropped, it's completely implicit now. Also, draw the with/without WREN distinction into the enter/exit functions to reduce code redundancy. Change-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22422 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* spi25: Merge remainder of spi4ba inNico Huber2017-12-281-24/+8
| | | | | | | | Change-Id: If581e24347e45cbb27002ea99ffd70e334c110cf Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22388 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Use common code for nbyte read/write and block eraseNico Huber2017-12-281-2/+0
| | | | | | | | | | | | | | | | | | Introduce spi_prepare_address() and spi_write_cmd() and use them in nbyte_program, nbyte_read and block-erase procedures. The former abstracts over the address part of a SPI command to make it exten- sible for 4-byte adressing. spi_write_cmd() implements a WREN + write operation with address and optionally up to 256 bytes of data. It provides a common path to reduce overall redundancy. Also, reduce the polling delay in spi_block_erase_c4() from 500s to 500ms as the comment suggests. Change-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* 4BA: Add spi_exit_4ba function to switch SPI flash to 3-byte addressingEd Swierk2017-10-151-0/+2
| | | | | | | | Change-Id: I553e7fb5028f35e14a3a81b3fa8903c1b321a223 Signed-off-by: Ed Swierk <eswierk@skyportsystems.com> Reviewed-on: https://review.coreboot.org/20509 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 4BA: Support for new direct-4BA instructions + W25Q256.V updateBoris Baykov2017-10-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Large flash chips usually support special instructions to work with 4-bytes address directly from 3-bytes addressing mode and without do switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program) and 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these instructions are supported by all large flash chips. Some chips support 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends on the manufacturer of the chip. This patch provides code to use direct 4-bytes addressing instructions. This code should work but it tested partially only. My W25Q256FV has support for 4BA_Read (13h), but doesn't have support 4BA_Program (12h) and 4BA_Erase instructions. So, direct 4BA program and erase should be tested after. Patched files ------------- chipdrivers.h + added functions declarations for spi4ba.c flash.h + feature definitions added flashchips.c + modified definition of Winbond W25Q256BV/W25Q256FV chips flashrom.c + modified switch to 4-bytes addressing for direct-4BA instructions spi4ba.h + definitions for 4-bytes addressing JEDEC commands + functions declarations from spi4ba.c (same as in chipdrivers.h, just to see) spi4ba.c + functions for read/write/erase directly with 4-bytes address (from any mode) Change-Id: Ib51bcc5de7826b30ad697fcbb9a5152bde2c2ac9 Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014 [clg: ported from https://www.flashrom.org/pipermail/flashrom/2015-January/013198.html ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-on: https://review.coreboot.org/20508 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* 4BA: Support for 4-bytes addressing via Extended Address RegisterBoris Baykov2017-10-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some flash chips data with addresses more than 24-bit field can address may be accessed by using Extended Address Register. The register has 1-byte size and stores high byte of 32-bit address. Then flash can be read from 3-bytes addressing mode with writing high byte of address to this Register. By using this way we have access to full memory of a chip. Some chips may support this method only. This patch provides code use Extended Address Register. Patched files ------------- chipdrivers.h + added functions declarations for spi4ba.c flash.h + feature definitions added flashrom.c + modified switch to 4-bytes addressing to support extended address register spi4ba.h + definitions for 4-bytes addressing JEDEC commands + functions declarations from spi4ba.c (same as in chipdrivers.h, just to see) spi4ba.c + functions for write Extended Address Register + functions for read/write/erase with Extended Address Register Change-Id: I09a8aa11de2ca14901f142c67c83c4fa0def4e27 Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014 [clg: ported from https://www.flashrom.org/pipermail/flashrom/2015-January/013200.html ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-on: https://review.coreboot.org/20507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* 4BA: Basic support for 4-bytes addressing mode extensionsBoris Baykov2017-10-141-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If flash chip is switched to 4-bytes addressing mode then all read/erase/program instructions will be switched from 3-bytes mode to 4-bytes mode. Then well known instructions like 03h (Read), 02h (Program) and 20h,52h,D8h (Erase) will become one byte longer and accept 4-bytes address instead of 3-bytes. This patch provides support for well known instructions in 4-bytes addressing mode. Also here is the code to enter 4-bytes addressing mode by execute the instruction B7h (Enter 4-bytes mode). Patched files ------------- chipdrivers.h + added functions declarations for spi4ba.c flash.h + feature definitions added Makefile + added spi4ba.c Added files ----------- spi4ba.h + definitions for 4-bytes addressing JEDEC commands + functions declarations from spi4ba.c (same as in chipdrivers.h, just to see) spi4ba.c + functions for enter 4-bytes addressing mode + functions for read/write/erase in 4-bytes addressing mode Change-Id: Ie72e2a89cd75fb4d09f48e81c4c1d927c317b7a7 Signed-off-by: Boris Baykov <dev@borisbaykov.com>, Russia, Jan 2014 [clg: ported from https://www.flashrom.org/pipermail/flashrom/2015-January/013199.html ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-on: https://review.coreboot.org/20513 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for SST SST25WF020A, SST25WF040B, SST25WF080BBen Gardner2015-11-221-0/+1
| | | | | | | | | | | | | | | | Apart from the strange ID (using Sanyo's vendor ID 0x62) the main difference from the plain SST25WF series is that they lack op codes 0xAD (AAI Word program) and 0x52 (32K erase). The smallest version does not support dual I/O operations either. SST25WF080B was tested under Linux with spidev. Corresponding to flashrom svn r1901. Tested-by: Ben Gardner <bgardner@wabtec.com> Signed-off-by: Ben Gardner <bgardner@wabtec.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Fix handling of write protection at register space address +2Stefan Tauner2014-12-201-1/+0
| | | | | | | | | | | | | | | Since r1833 we added the offset of the virtual register in several functions, which produced segfaults. This patch renames a few parameters and reorganizes/fixes various parts of the changelock_regspace2_block() function - hence the rather big diff. Thanks to Roman Lebedev for reporting this issue and testing numerous revisions of this patch. Corresponding to flashrom svn r1859. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Unify non-shifted and shifted JEDEC accessCarl-Daniel Hailfinger2014-08-081-6/+0
| | | | | | | | | | | | | | | | | | Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit) for 8-bit mode. Some programmers can access them in 16-bit mode, but on all flashrom-supported programmers so far, we access them in 8-bit mode. This means we have to shift the addresses but apart from the addresses we can share the code. This patch makes this possible by checking the chip's FEATURE_ADDR_SHIFTED flag in common JEDEC functions and applying the right addresses respectively. Corresponding to flashrom svn r1840. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add a bunch of new/tested stuff and various small changes 21Stefan Tauner2014-08-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASUS F2A85-M Reported by various corebooters - ASUS M2N-MX SE Plus Reported by Antonio - ASUS P5LD2 Reported by François Revol - Lenovo ThinkPad T530 Reported and partially authored by Edward O'Callaghan - MSI MS-7502 (Medion MD8833) Reported by naq on IRC - Shuttle AB61 Reported by olofolleola4 - ZOTAC IONITX-F-E Reported by Bernardo Kuri Flash chips: - Atmel AT45DB021D to PREW (+PREW) Reported by The Raven - Atmel AT25F4096 to PREW (+PREW) Reported by 공준혁 - GigaDevice GD25Q16(B) to PREW (+PREW) Reported by luxflow@live.com using a GD25Q16BSIG - Catalyst CAT28F512 Mark erase and write as known bad (not implemented) Miscellaneous: - Various spelling corrections by Daniele Forsi. - Added and refined a bunch of chips originally investigated by Carl-Daniel. - Marked the ARM-USB-OCD-H programmer as tested (reported by Ruud Schramp). - Tiny other stuff. Corresponding to flashrom svn r1839. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for a bunch of 29GL parallel flash chipsStefan Tauner2014-08-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | 29GL chips use a new 3-Byte device ID probing function at addresses 0x01, 0x0E, 0x0F. Flash chip families supported by this method include... - EON EN29GL - Gigadevice GD29GL (if they really exist) - ISSI (PMC) IS29GL - Macronix MX29GL (+MX68GL1G0F) - Spansion S29GL (+S70GL02G) - Winbond W29GL This patch adds respective flash chip definitions for chips up to 16 MB from Eon, ISSI, Macronix and Winbond. Bigger chips as well as those from Gigadevice and Spansion are left out. Corresponding to flashrom svn r1835. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Refactor unlocking of many chips with locking at register space address +2Carl-Daniel Hailfinger2014-08-031-10/+9
| | | | | | | | | | | This includes PMC Pm49*, SST 49LF00*, ST M50* and Winbond W39* families. The erase and write test status bits of all affected chips have been reset. Corresponding to flashrom svn r1833. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Sanyo LE25FW106Stefan Tauner2014-06-041-0/+1
| | | | | | | | | | | Also, add spi_disable_blockprotect_bp1_srwd(). Originally written and tested by The Raven <originalraven@hotmail.com>. Corresponding to flashrom svn r1818. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Combine block_erase*_en29lv640b and block_erase*_m29f400bt respectivelyStefan Tauner2014-06-011-4/+2
| | | | | | | | | | | | | | | This patch combines two identical block and chip erase functions respectively: - Merge block_erase_m29f400bt and block_erase_en29lv640b into erase_block_shifted_jedec. - Merge block_erase_chip_m29f400bt and block_erase_chip_en29lv640b into erase_chip_block_shifted_jedec. Leave their implementations in en29lv640b.c for now. Corresponding to flashrom svn r1808. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* jedec.c: constify a bit moreStefan Tauner2014-05-291-4/+2
| | | | | | | | | | Also, include chipdrivers.h to find conflicting types between exported declarations and actual implementations. Corresponding to flashrom svn r1805. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Rename some spi_prettyprint_status_register_* functionsStefan Tauner2014-05-271-4/+4
| | | | | | | | | | | | Spi_prettyprint_status_register_default_bpX -> spi_prettyprint_status_register_bpX_srwd Why was the default in there anyway? :) Corresponding to flashrom svn r1802. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for ESMT F25L32PAStefan Tauner2014-05-271-0/+1
| | | | | | | Corresponding to flashrom svn r1801. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add 'const' keyword to chip write and other function prototypesMark Marshall2014-05-091-13/+13
| | | | | | | | | | Corresponding to flashrom svn r1789. Inspired by and mostly based on a patch Signed-off-by: Mark Marshall <mark.marshall@omicron.at> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Cleanup ST M50 driverStefan Tauner2013-09-121-3/+4
| | | | | | | | | | | | | | | There are two locking strategies used by this umbrella family, one uniform and one that matches the sector layout of the chip. Refactor the functions involved and rename the overly complicated file to just stm50.c and the functions accordingly. This fixes unlocking of some of the non-uniform chips and gets rid of the abuse of page_size. Corresponding to flashrom svn r1736. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for AT45CS1282Stefan Tauner2013-08-271-0/+1
| | | | | | | | | | | This one is even more strange than the AT45DB chips. Like the AT45DB321C it does not support any power-of-2 page sizes. There is only one asymmetrical eraser and that uses two opcodes. Corresponding to flashrom svn r1725. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for AT45DB321CStefan Tauner2013-08-271-0/+1
| | | | | | | | | | It seems like this model is one-of-a-kind... it shares some properties with the older versions of the AT45DB series as well as with new ones. Corresponding to flashrom svn r1724. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Atmel AT45DB* chipsAidan Thornton2013-08-271-0/+12
| | | | | | | | Corresponding to flashrom svn r1723. Signed-off-by: Aidan Thornton <makosoft@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for remaining Numonyx (Micron) N25Q chipsNikolay Nikolaev2013-06-281-0/+3
| | | | | | | | | | | | | | | | | | | | Add... - N25Q128..3E - N25Q128..1E - N25Q256..1E (defunct due to addressing) - N25Q256..3E (defunct due to addressing) - N25Q512..1E (defunct due to addressing) - N25Q512..3E (defunct due to addressing) - N25Q00A..3G (defunct due to addressing) Also, refine existing family members. Corresponding to flashrom svn r1693. Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Reviewed-by: Steven Zakulec <spzakulec@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Spansion S25FL...S chipsNikolay Nikolaev2013-06-281-2/+2
| | | | | | | | | | | | | | | Add... - S25FL128S - S25FL256S uniform version (defunct due to addressing) - S25FL512S uniform version (defunct due to addressing) Merge Intel S33 status register functions with this one's. Corresponding to flashrom svn r1692. Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Eon EN25S seriesNikolay Nikolaev2013-06-281-0/+1
| | | | | | | | | | | | | | | | | | Add... - EN25S10 - EN25S20 - EN25S40 - EN25S80 - EN25S16 - EN25S32 - EN25S64 Corresponding to flashrom svn r1687. Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Reviewed-by: Steven Zakulec <spzakulec@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Introduce spi_block_erase_db()Nikolay Nikolaev2013-06-281-0/+1
| | | | | | | | | | | | Used for page erase on some chips (e.g. Numonyx M45PE and Sanyo LF25FW series). Corresponding to flashrom svn r1682. Signed-off-by: Nikolay Nikolaev <evrinoma@gmail.com> Reviewed-by: Steven Zakulec <spzakulec@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Introduce additional SPI status register helpersStefan Tauner2013-06-281-1/+5
| | | | | | | | | | | | | | | | | | - spi_prettyprint_status_register_default_welwip(): It just prettyprints the plain hex value and the welwip bits. - spi_prettyprint_status_register_default_bp4(): Prints the hex value, welwip, bp0-5 and srwd bits. - spi_disable_blockprotect_bp2_srwd(), - spi_disable_blockprotect_bp3_srwd() and spi_disable_blockprotect_bp4_srwd(): Three new common block unprotection functions for the frequent cases where there is a status register lock bit at bit #7 and some block protection bits at bits #2-#4, #2-#5 and #2-#6 respectively. Corresponding to flashrom svn r1681. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Fix unlocking function for most Atmel AT2[56]D* chipsStefan Tauner2013-06-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | I broke unlocking them correctly in r1635 while refactoring (NB: the commit log including the overly selfconfident statement about the "bug in spi_disable_blockprotect_at25df()"). Affected chips have per sector protection bits and the write protection bits in the status register do indicate if none, some or all sectors are protected. It is possible to globally (un)lock all sectors at once but in a way that was not anticipated when refactoring the spi25 unlocking functions into spi_disable_blockprotect_generic(). To globally unprotect not only the protection bits (2 and 3) have 0 to be written to them but also bits 4 and 5 which normally would not be touched by spi_disable_blockprotect_generic(). Some of the chips also support a permanent lockdown with fuses which we do not handle yet. To fix this without copying the whole method I introduce another mask parameter to spi_disable_blockprotect_generic() namely unprotect_mask. See verbose comments inline for details. Also, prettyprint the status register after trying to disable the block protection fails. Corresponding to flashrom svn r1679. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Chi Zhang <zhangchi866@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Update spi_get_erasefn_from_opcode()Stefan Tauner2013-05-011-3/+3
| | | | | | | | | | We forgot to add a few SPI erase functions to the helper function that is used for SFDP. Also, sort the declarations in the header. Corresponding to flashrom svn r1672. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Refine PMC Pm25LV seriesStefan Tauner2013-04-191-0/+1
| | | | | | | | | | | | | | | | | | | - Add missing bits and resort chips - Refine Pm25LV512(A) and Pm25LV010 Due to manufacturer ID continuation this one needs a new probing function: probe_spi_res3() which should be refactored in the future. The datasheet describes a very weird order of ID bytes: Vendor byte, model byte, vendor continuation byte. Let's pretend we did not read that or the datasheet is bogus (although the datasheet of the successor series describes the same but luckily additionally to RDID). - Add Pm25LV010A This was tested by Chi Zhang: http://paste.flashrom.org/view.php?id=1573 Corresponding to flashrom svn r1670. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Atmel's AT25F series of SPI flash chipsStefan Tauner2012-12-291-0/+7
| | | | | | | | | | | | | | | | | | This adds support for the following chips: - AT25F512, AT25F512A, AT25F512B - AT25F1024, AT25F1024A - AT25F2048 - AT25F4096 Besides the definitions of the the chips in flashchips.c this includes - a dedicated probing method (probe_spi_at25f) - pretty printing methods (spi_prettyprint_status_register_at25f*), and - unlocking methods (spi_disable_blockprotect_at25f*) Corresponding to flashrom svn r1637. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Intel S33 series flash chipsStefan Tauner2012-12-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This includes: Bottom boot block: * 16Mb/2MB: QB25F160S33B8, QB25F016S33B8, QH25F160S33B8, QH25F016S33B8 * 32Mb/4MB: QB25F320S33B8, QH25F320S33B8 * 64Mb/8MB: QB25F640S33B8, QH25F640S33B8 Top boot block: * 16Mb/2MB: QB25F160S33T8, QB25F016S33T8, QH25F160S33T8, QH25F016S33T8 * 32Mb/4MB: QB25F320S33T8, QH25F320S33T8 * 64Mb/8MB: QB25F640S33T8, QH25F640S33T8 At least some seem to be marketed by other vendors (too?) but also with Intel's vendor ID. Besides a 0xC7 chip erase and a 0xD8 uniform 64kB block erase they support also erasing the top/bottom 8 8kB blocks with opcode 0x40. But since this command fails for all addresses outside those ranges, it is not easily implemented with flashrom's current code base and hence left out. Corresponding to flashrom svn r1636. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Improve SPI status register pretty printingStefan Tauner2012-12-291-24/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move all functions related to SPI status registers to a new file spi25_statusreg.c. This includes the generic as well as the SST-specific functions from spi25.c and the chip-specific functions from a25.c and at25.c. - introduce helper functions * spi_prettyprint_status_register_hex() * spi_prettyprint_status_register_bpl() * spi_prettyprint_status_register_plain() Use the latter on every compatible flash chip that has no better printlock function set and get rid of the implicit pretty printing in the SPI probing functions. - remove * spi_prettyprint_status_register_common() * spi_prettyprint_status_register_amic_a25lq032() because it can be fully substituted with spi_prettyprint_status_register_amic_a25l032(). * spi_prettyprint_status_register() (old switch, no longer needed) - promote and export * spi_prettyprint_status_register_amic_a25l05p() as spi_prettyprint_status_register_default_bp1(). * spi_prettyprint_status_register_amic_a25l40p() as spi_prettyprint_status_register_default_bp2(). * spi_prettyprint_status_register_st_m25p() as spi_prettyprint_status_register_default_bp3(). - add #define TEST_BAD_REW and use it for a number of Atmel chips which had only TEST_BAD_READ set even though they dont have erasers or a write function set. Corresponding to flashrom svn r1634. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for Winbond W39F010/W39L010/W39L020Kyösti Mälkki2012-10-281-0/+3
| | | | | | | | | | | | | | | | W39F010 is a 128kB parallel 5V flash chip, 16k bootblocks. W39L010 is a 128kB parallel 3.3V flash chip, 8k bootblocks. W39L020 is a 256kB parallel 3.3V flash chip, 64k/16k bootblocks. The W39F010 code was tested with a satasii programmer. The first write attempt after an erase returned with verify failure, but the second write attempt was succesful: http://paste.flashrom.org/view.php?id=1418 Corresponding to flashrom svn r1620. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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