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path: root/drivers/clk/renesas
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* clk: renesas: r8a7795: Add 3DGE and ZG supportGeert Uytterhoeven2023-07-271-0/+2
* clk: renesas: emev2: Remove obsolete clkdev registrationGeert Uytterhoeven2023-07-271-3/+0
* clk: renesas: r9a07g043: Add MTU3a clock and reset entryBiju Das2023-07-251-0/+3
* clk: renesas: rzg2l: Simplify .determine_rate()Christophe JAILLET2023-07-111-7/+1
* clk: renesas: r9a09g011: Add CSI related clocksFabrizio Castro2023-07-101-0/+15
* clk: renesas: r8a774b1: Add 3DGE and ZG supportAdam Ford2023-07-101-0/+2
* clk: renesas: r8a774e1: Add 3DGE and ZG supportAdam Ford2023-07-101-0/+2
* clk: renesas: r8a774a1: Add 3DGE and ZG supportAdam Ford2023-07-101-0/+2
* clk: renesas: rcar-gen3: Add support for ZG clockAdam Ford2023-07-102-4/+32
*-. Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-sam...Stephen Boyd2023-06-266-49/+27
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| | * clk: renesas: r9a06g032: Add a determine_rate hookMaxime Ripard2023-06-081-0/+1
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| * clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven2023-06-051-11/+5
| * clk: renesas: mstp: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven2023-06-051-11/+7
| * clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()Geert Uytterhoeven2023-06-051-20/+11
| * clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register writeBiju Das2023-05-232-7/+2
| * clk: renesas: r8a779a0: Add PWM clockWolfram Sang2023-05-081-0/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2023-04-297-204/+591
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| * clk: renesas: r8a77980: Add I2C5 clockNikita Yushchenko2023-03-301-0/+1
| * clk: renesas: Convert to platform remove callback returning voidUwe Kleine-König2023-03-161-4/+2
| * clk: renesas: r9a06g032: Improve clock tablesRalph Siemsen2023-03-101-153/+407
| * clk: renesas: r9a06g032: Document structsRalph Siemsen2023-03-101-1/+49
| * clk: renesas: r9a06g032: Drop unused fieldsRalph Siemsen2023-03-101-5/+10
| * clk: renesas: r9a06g032: Improve readabilityRalph Siemsen2023-03-101-41/+80
| * clk: renesas: r8a77980: Add Z2 clockGeert Uytterhoeven2023-03-101-0/+1
| * clk: renesas: r8a77970: Add Z2 clockGeert Uytterhoeven2023-03-101-0/+1
| * clk: renesas: r8a77995: Fix VIN parent clockGeert Uytterhoeven2023-03-061-1/+1
| * clk: renesas: r8a77980: Add VIN clocksNiklas Söderlund2023-03-061-0/+16
| * clk: renesas: r8a779g0: Add VIN clocksNiklas Söderlund2023-03-061-0/+16
| * clk: renesas: r8a779g0: Add ISPCS clocksNiklas Söderlund2023-03-061-0/+2
| * clk: renesas: r8a779g0: Add CSI-2 clocksNiklas Söderlund2023-03-061-0/+3
| * clk: renesas: r8a779g0: Add thermal clockGeert Uytterhoeven2023-03-061-0/+1
| * clk: renesas: r8a779g0: Add Audio clocksKuninori Morimoto2023-03-061-0/+2
| * clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4HTakeshi Kihara2023-03-061-4/+4
* | clk: renesas: remove MODULE_LICENSE in non-modulesNick Alcock2023-04-132-2/+0
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* clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*Wolfram Sang2023-02-105-173/+13
* clk: renesas: r8a779g0: Add CAN-FD clocksGeert Uytterhoeven2023-01-261-0/+2
* clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMACKuninori Morimoto2023-01-261-2/+2
* clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMACKuninori Morimoto2023-01-261-2/+2
* clk: renesas: r8a779g0: Add custom clock for PLL2Geert Uytterhoeven2023-01-243-7/+164
* clk: renesas: cpg-mssr: Remove superfluous check in resume codeGeert Uytterhoeven2023-01-231-3/+2
* clk: renesas: r9a06g032: Handle h2mode setting based on USBF presenceHerve Codina2023-01-231-0/+28
* clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failedAlexey Khoroshilov2023-01-121-1/+2
* clk: renesas: r9a07g044: Add clock and reset entries for CRULad Prabhakar2023-01-121-1/+25
* clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entriesPhil Edworthy2022-12-271-0/+20
* clk: renesas: r9a09g011: Add USB clock and reset entriesBiju Das2022-12-271-0/+21
* clk: renesas: r9a09g011: Add TIM clock and reset entriesBiju Das2022-12-271-0/+22
* clk: renesas: r8a779g0: Add display related clocksTomi Valkeinen2022-12-261-0/+9
* clk: renesas: rcar-gen4: Restore PLL enum sort orderGeert Uytterhoeven2022-12-261-1/+1
* clk: renesas: r8a779g0: Fix OSC predividersGeert Uytterhoeven2022-12-261-4/+4
* clk: renesas: r9a09g011: Add PWM clock and reset entriesBiju Das2022-12-261-0/+10
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-15 22:09:49 +0000