| Commit message (Collapse) | Author | Age | Files | Lines |
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On guybrush, keyboard presses are signaled by the EC via eSPI virtual
wire. The interrupt is shared with others and should be active low.
From 74bce48f1d4 ("mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity"):
> The default state for the IRQ lines when the eSPI controller comes
> out of reset is high. This is because the IRQ lines are shared with
> the other IRQ sources using AND gates. This means that in order to
> not cause any spurious interrupts or miss any interrupts, the
> IO-APIC must use a low polarity trigger.
Setting `vw_irq_polarity` in the device tree provides an option to
invert interrupts from the eSPI controller, but the register is
initialized from verstage which is baked into RO.
As a workaround, the necessary interrupts on the EC have been
reconfigured to be active low, and we can modify the IO-APIC
accordingly.
EC related CL here: https://crrev.com/c/4891663
BUG=b:218874489
TEST=-`emerge-guybrush chromeos-ec coreboot chromeos-bootimage`
-Flash new RW fw and verify keyboard is functional
-`suspend_stress_test -c 1` and verify i8042 irq is removed as a
wake source
-`echo mem > /sys/power/state`. Press key and verify system wake
from i8042.
Cq-Depend: chromium:4891663
Change-Id: I7d093d94a666263684645ef724e945069c68c806
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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No Windows driver exists or is needed, so hide to prevent an unknown
device from being listed in Windows Device Manager.
TEST=build/boot Win11 on dewatt, verify unknown device for the ACP
machine driver no longer present.
Change-Id: I44d25fd2ea75593383cbb14f2324d4376b399de7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Allows ACPI SSDT generator to hide the device from Windows via _STA
Change-Id: I22b3ccc2c89a3f7ababd0eaf4e35604880aa0ce7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Set bluetooth enable_delay_ms to 200ms. 200ms is the lowest common
denominator between the two BT chipsets.
BUG=b:233369179,b:236289478
BRANCH=guybrush
TEST=Connect to headset, suspend and reboot, headset still functions
Change-Id: Id4c23de37351d28d02aaa797fa19ff49e9dfa76c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65180
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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The default state for the IRQ lines when the eSPI controller comes out
of reset is high. This is because the IRQ lines are shared with the
other IRQ sources using AND gates. This means that in order to not cause
any spurious interrupts or miss any interrupts, the IO-APIC must use a
low polarity trigger.
On zork/guybrush/skyrim the eSPI IRQs are currently working as follows:
* On power on/resume the eSPI controller drives IRQ 1 high.
* eSPI controller gets configured to not invert IRQ 1.
* OS configures IO-APIC IRQ 1 as Edge/High.
* EC writes to HIKDO (Keyboard Data Out) which causes the EC to set IRQ1
high.
* eSPI controller receives IRQ 1 high, doesn't invert it, and leaves IRQ
1 as high. This results in missing the first interrupt.
* When the x86 reads from HIKDO, the EC deasserts IRQ1. This causes the
eSPI controller to set IRQ1 to low. We are now primed to catch the
next edge high interrupt. This is generally not a problem since the
linux driver will probe the 8042 with interrupts off.
On S3/S0i3 resume since the eSPI controller comes out of reset driving
the IRQ lines high, we trigger a spurious IRQ since the IO-APIC is
configured to trigger on edge high. This results in the 8042 controller
getting incorrectly marked as a wake trigger.
By configuring the IO-APIC to use low polarity interrupts, we no longer
lose the first interrupt. This also means we can use a level interrupt
to match what the EC actually asserts.
We use the `Interrupt` keyword instead of the `IRQ` keyword in the ACPI
because the linux kernel will ignore the level/polarity parameters
for the `IRQ` keyword and default to `edge/high. `Interrupt` doesn't
have this problem.
The PIC is not currently configured anywhere and it defaults to an
edge/high trigger. We could add some code to configure the PICs trigger
register, but I don't think we need the functionality right now.
For zork and guybrush, this change is a no-op. eSPI is configured in
verstage which is located in RO, and we have already locked RO for
these devices. We will need to figure out how to properly set the
`vw_irq_polarity` for these devices.
BUG=b:218874489, b:160595155, b:184752352, b:157984427, b:238818104
TEST=On zork, guybrush and skyrim
$ suspend_stress_test --post_resume_command 'cat /sys/devices/platform/i8042/serio0/wakeup/wakeup35/active_count'
Verify keyboard works as expected and no interrupt storms are observed.
On morphius I verified keyboard and mouse work on windows as well.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4608a7684e34ebb389e0e55ceba7e7441939afe7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The generic wifi driver currently contains a lot of intel specific
functionality that results in it not working properly on AMD platforms.
This commit updates the base device tree to use the generic PCIe driver
instead.
BUG=none
TEST=Ran on nipperkin device, dumped SSDT and checked wakeup sources
Change-Id: Iafbc68c1ae33ccc260889f0b39fc5fe8a59d7aca
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65990
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
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+----------------+
C0 | | C1
A0 | MLB DB | A1
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+----------------+
BUG=b:232298307
TEST=None
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ic9c45aebaf02a16b755f4731e1e3b46cd5dec829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Use the existing definitions from FspUsb.h instead of magic values for
the ComboPhyStaticConfig settings in the mainboard's devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2707d017909b7516e5d8711c8f4e2914165ed10d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set the BT USB device to use GPIO for the power status. This causes an
ACPI `_STA()` function to be generated that returns the power status of
the BT USB device, rather than always returning `0x1`. This `_STA()`
function can be used during boot to skip enabling the device (and
performing the associated sleep) if the device is already powered on.
BRANCH=None
BUG=b:225022810
TEST=Dump SSDT table for guybrush
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I72f6b28671efddfbef53f328d904a05f73f39efa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The `reset` gpio is currently being consumed by the btusb kernel driver.
The functionality was added in https://crrev.com/c/3342774. The goal of
the patch was to reset the BT device when command timeouts occur. This
works, but it doesn't support the case where the BT device is having
problems with USB enumeration. In that case the device can't enumerate
so the driver can't help resetting the device.
If we instead switch to using an ACPI power resource, the kernel can
control the BT device's power. This is beneficial when the device is
having USB communication problems since the kernel will try and power
cycle the device.
We don't lose the ability to reset the device on command timeouts
either since `btusb_qca_cmd_timeout` will enqueue a USB port reset if
there is no `reset` GPIO. So win / win.
This results in the following power resource:
PowerResource (PR02, 0x00, 0x0000)
{
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x01)
}
Method (_ON, 0, Serialized) // _ON_: Power On
{
\_SB.CTXS (0x84)
Sleep (0x01F4)
}
Method (_OFF, 0, Serialized) // _OFF: Power Off
{
\_SB.STXS (0x84)
Sleep (0x0A)
}
}
I switched the device tree entry from using reset_gpio to enable_gpio
because the acpi_device_add_power_res method asserts the reset in the
_ON method unconditionally. This results in a small glitch on the line.
By using the enable_gpio we get the correct behavior.
I don't have a datasheet right now, so I just picked some values for the
reset timing. The kernel driver was using 200ms. We can revisit the
numbers when we get a datasheet.
BUG=b:218295688
TEST=Suspend stress test on nipperkin with 600+ cycles. Verify power
resource is created on the kernel. This should allow the kernel to
power cycle the device via usb_acpi_set_power_state.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib1eff86db76929f76432cd6f765880c892e7a786
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO for future improvements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Set TPM power_managed_mode to TPM_KERNEL_POWER_MANAGED. This will cause
the TPM kernel driver to send a shutdown command before s0i3 entry. This
change depends on S0i3 verstage running and reinitializing the TPM.
BUG=b:200578885
BRANCH=None
TEST=TPM shutdown sent during s0i3 entry on guybrush
Change-Id: I206022cc2a29690186206966c5d45bd55c303248
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update guybrush STT (Skin Temperature Tracking) configuration settings
to values provided by power team after tuning.
BUG=b:203123658
Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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GSC_SOC_INT_L gpio is used by Google Security Chip (GSC) to interrupt
SoC when the SoC is in S0 state. Hence use GPIO_85 which is in S0 domain
and save the GPIO_3 in S5 domain for other use-cases. This move applies
to all board except:
* Guybrush
* Nipperkin board version 1
Update the GPIO configuration, device tree configuration accordingly.
BUG=b:202992077
TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure that the SoC
<-> TPM communication is working fine.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I019f10f2f457ab81bcff77ce8ca609b2b40cb2ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The USB descriptions are flipped. Fix by inverting the USB descriptions
in devicetree.
BUG=None
TEST=Build
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I4b33f4de137536c5f3592380da15f6b3a3633bf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57538
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a short documenting comment to each usb entry in devicetree so it is
clear which function each usb port maps to.
BUG=None
TEST=Build
BRANCH=None
Change-Id: I14cbb6af021bb27c89aa82456722f21aa09617be
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56725
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Setting the usb_phy version and length in the soc code instead of devicetree.
That way the devicetree code does not have to reapeat it for different
AMD Cezanne based systems.
Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The AMD Cezanne FSP expects a usb phy config structure ID of 0xd 0x6.
If the ID does not match, the FSP USB will not set up the phy.
Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.
Cq-Depend: chrome-internal:4087511
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I4fdb5af1cbc3c70cc113ef6f0fd9332e1a27f142
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Guybrush based boards must usa a dedicated eSPI alert#.
Must be open drain to prevent power leaks.
Keep guybrush reference board in-band since alert# may not be connected.
BUG=b:198409370
TEST=Build guybrush and nipperkin, boot guybrush
BRANCH=None
Change-Id: I4b23bfc6a1167aebfde5acd524fda043b63163dc
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable Skin Temperature Tracking with initial configuration settings.
BUG=b:190732595
TEST=Confirm that AGT tool can successfully complete data collection
Change-Id: I37b5da1b56586ef75ad17f6766cd00ddac87aa5a
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55434
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources.
In guybrush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device.
BUG=b:186384256
BRANCH=none
TEST=Verify the config setting can update to the GPPCLKCONTROL registers.
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56895
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tune the USB phy settings to update TXVREFTUNE0/COMPDISTUNE0 to
higher value for USB port 5 (Type-A).
BUG=b:194053549
TEST= Pass USB 2.0 SI Eye diagram measurement.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Id1ede34bdbee0c1f9f7d10fc7ffbc9648af31e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56925
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It appears the pspp_policy enum is not the same as the FSP definition
currently being used. This means that the incorrect PSPP value setting
would get read by FSP. For Zork programs this meant we actually were
setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE.
This change adds DXIO_PSPP_DISABLED as the first enum value to properly
match the FSP definition and adjusts non AMD Customer Reference Boards
that reference the enum to still send the same value even though it has
now change definitions. If we actually want DXIO_PSPP_POWERSAVE for
those boards that can be adjusted in a future change.
BUG=b:193495634
TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi
with other server on local network.
Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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This change only enables the IOMMU device. We still require the IVRS
table to take advantage of the IOMMU. This will happen when the picasso
IVRS code is moved into common.
BUG=b:190515051
TEST=lspci shows IOMMU device
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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To avoid from using same the name AMDI5682 as Zork, changing to use
AMDI1019. The corresponding kernel change is on CL:2929864
BUG=b:189297564
TEST=Audio works with the corresponding kernel change.
Cq-Depend: chromium:2929864
Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com>
Change-Id: Ie89302f3b6cd3edb8253b909fde4722c2ea1e102
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55508
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to enable ACP DMIC hardware runtime detection, indicate that
ACP DMIC is present.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method
is populated in the ACP device.
Change-Id: I9a53d158ed08a6b46c29bcb8fe3a2a0d108bd6cd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55030
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will tell the kernel to ignore PCI ASPM when suspending the device
and instead place the device into D3. We don't actually have a pin to
control power to the NVMe so we leave it in D3Hot. I'm not sure if
`PCI_RST#` is working correctly on S0i3 suspend/resume. If it's not
acting as expected we can add the reset GPIO and have the OS do it.
BUG=b:184617186
TEST=Run suspend_stress_test on guybrush for 10 cycles
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I29539ac120a9f1b7c1bfeaca745cfc82acfa461a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54967
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some of the I2C buses are required to operate at different voltage level
compared to other I2C buses eg. I2C bus to Google Security Chip (GSC)
should be at 1.8V level. By default, all the I2C buses are initialized
to operate at 3.3 V. Add support to configure I2C pad RX select through
devicetree and update the concerned devicetree.
BUG=b:188538373
TEST=Build and boot to OS in Guybrush. Ensure that the communication
with GSC is fine. Build Majolica mainboard.
Change-Id: I595a64736fdac0274abffb68c5e521302275b845
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This fixes the following error from the Linux kernel:
ccp 0000:03:00.2: ioremap failed
ccp 0000:03:00.2: initialization failed
ccp: probe of 0000:03:00.2 failed with error -12
BUG=b:186575712,b:189202985
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5cbc620001d3c21c538b62ab2811b6e07269feb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54962
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:188793754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I262c4c3ae90d8d12fdfe71a3620739070a444a55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54931
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All relevant USB phy settings can now be controlled via devicetree.
The given values are the AMD default ones.
For proper tuning procedure and values contact AMD.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ie8d08bde54f8c0cb8202ba111b9c7a9bd33fa03e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The time constant values were taken from the zork thermal.asl.
BUG=b:186166365
TEST=Boot guybrush to OS and verify logs look correct
thermal-0294 thermal_trips_update : Found critical threshold [3641]
thermal-0321 thermal_trips_update : No hot threshold
thermal-0200 thermal_get_temperatur: Temperature is 3060 dK
thermal-0219 thermal_get_polling_fr: Polling frequency is 100 dS
thermal-0200 thermal_get_temperatur: Temperature is 3060 dK
thermal LNXTHERM:00: registered as thermal_zone0
ACPI: Thermal Zone [TM00] (33 C)
thermal-0200 thermal_get_temperatur: Temperature is 3070 dK
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaeed75bdaa16b117d0fa7144ede98db1388f74f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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In order to support wake on WLAN events, configure the wake resource.
BUG=b:186011392
TEST=Build and boot to OS in guybrush. Ensure that WiFi power resource
is added to SSDT.
Device (\_SB.PCI0.GP20.WF00)
{
Name (_UID, 0x38B82CBC) // _UID: Unique ID
Name (_DDN, "WIFI Device") // _DDN: DOS Device Name
Name (_ADR, 0x0000000000000000) // _ADR: Address
}
Scope (\_SB.PCI0.GP20.WF00)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x08,
0x03
})
}
Change-Id: Ic238d9606aea20c058e9b47093693f10b14e6288
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Enable Display Controller Engine Audio endpoint to enable HDMI audio.
BUG=b:186479763
TEST=Build and boot to OS in guybrush.
Change-Id: I5e35440e8e70ee125d37c7ac30c9219ec69c7c6e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Using the push-pull alert was causing leakages when in S0i3. This is
because the EC drives ALERT#, so when the AP enters S0i3, the extra
current leaks into the SoC and ends up turning on the power regulators.
By using in-band ALERT#, the EC no longer drives this pin high, thus
fixing the leak. We could also have used an open drain alert, but the
rise time is less than ideal.
BUG=b:187122344, b:186135022
TEST=Measure S0i3 power on guybrush and validate it's no longer high.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Some designs might wish to use an open drain eSPI ALERT#. This change
adds an enum that allows setting the eSPI alert mode.
BUG=b:187122344, b:186135022
TEST=Boot guybrush using all 3 alert modes
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Configure Audio Co-processor(ACP) to operate in I2S TDM mode. Also fix
the scope in which ACP is defined in the devicetree.
BUG=b:182960979
TEST=Build and boot to OS in Guybrush. Ensure that the ACPD device is
enabled in the appropriate scope in SSDT.
Change-Id: Ic90fd82e5c34a9feb9a80c4538a45e7c2fb91add
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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All guybrush boards should have system_configuration set to 2, so
put this in the main devicetree.
BUG=b:185209734
TEST=Build & Boot guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: chris wang <Chris.Wang@amd.com>
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BUG=b:185939089
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.
Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change eSPI bus frequency to 33Mhz.
BUG=b:184356693, b:185514521
TEST=Boot guybrush, observe no eSPI bus errors
Change-Id: Ie2c1b256531f5c7354600e35e9e5191567197feb
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52402
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable AMD I2S machine driver and configure the devicetree with HID
information so that the machine driver ACPI objects can be passed to the
kernel.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for
machine driver is populated.
Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add uart controller to chipset.cb and leave it off by default.
Turn uart0 on for console for mainboards.
BUG=none
TEST=builds and boot into OS
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Guybrush doesn't have a PS/2 mouse.
BUG=none
TEST=boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I87e51d23b69cfd6ad7bb88b364714d679e92728f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52145
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 52e61945588bc327844acc4658426861d63ad189.
Reason for revert: Graphics actually works now. I should have abandoned this CL.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I83aac3a2c616bb434706f23e36549760bc764080
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This is locking up the OS. For now this will unblock booting.
BUG=b:183971103
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id2b96eedf38c9038169407418c6d36f13299fb62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Configure the BT disable GPIO to logic low in order to enable Bluetooth.
Add USB ACPI configuration for BT device.
BUG=b:182201890
TEST=Build and boot to OS.
Change-Id: I647c301e2db6d4a7c5c8cb31cbc47a44cba5e734
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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It looks like we are having SI issues on eSPI at 33 MHz. Switching to 16
MHz makes everything a lot more stable.
BUG=b:183524609
TEST=Boot to OS and run `ectool version` 1000 times and see no problems.
Before with 33 MHz there was an error every few cycles.
declare -i i=0; while ectool version; do i+=1; echo "$i"; sleep .11; done; echo "Finished: $i"
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ab515629703a157c1d1ac6adcf5cf379e80f8ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Configure H1 I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for H1 device and enable the required
config items.
BUG=b:180528902
TEST=Build Guybrush mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I040a5e6101bab0c7425d7b6cc6fbed3b479a5a44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add I2C peripheral reset configuration required during early init.
Enabled I2C generic and HID drivers. I2C GPIOs are configured as
required in CB:50091.
BUG=b:180531661
TEST=Build guybrush mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I67690fbd25639879a730260aaca4cddb5e47bbc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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