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* nb/intel/haswell: Add 9-series PCH IDsAngel Pons2023-02-091-0/+5
* mb/*: Replace SNB PCI devices with references from chipset.cbArthur Heymans2023-02-041-0/+33
* nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hwBill XIE2023-02-022-4/+8
* treewide: Remove duplicated include <device/pci.h>Elyes Haouas2023-02-013-3/+0
* nb/intel/gm45: Add remaining raminit code to support DDR2Nico Huber2023-01-263-54/+156
* nb/intel/gm45: Split DDR2 I/O init outNico Huber2023-01-261-11/+125
* nb/intel/gm45: Split DDR2 JEDEC init outNico Huber2023-01-262-30/+87
* nb/intel/gm45: Wedge DDR2 SPD support inNico Huber2023-01-262-19/+181
* nb/amd/pi/Kconfig: Remove unused CONSOLE_VGA_MULTIElyes Haouas2023-01-211-4/+0
* nb/intel/haswell: Specify supported memory typeElyes Haouas2023-01-051-0/+5
* spd.h: Move enum ddr3_module_type to ddr3.hElyes Haouas2023-01-042-3/+3
* nb/intel/*/Kconfig: Remove dummy NORTHBRIDGE_SPECIFIC_OPTIONSElyes Haouas2023-01-046-32/+10
* nb/intel/ironlake: Specify supported memory typeElyes Haouas2023-01-041-0/+5
* nb/intel/e7505: Specify supported memory typeElyes Haouas2023-01-021-0/+5
* nb/intel/i440bx: Specify supported memory typeElyes Haouas2023-01-021-0/+5
* tree/acpi: Replace constant "Zero" with actual numberFelix Singer2022-12-271-1/+1
* nb/intel/ironlake/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas2022-12-261-1/+1
* nb/intel/sandybridge/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas2022-12-261-1/+1
* nb/intel/haswell/acpi: Replace Index(a, b) with ASL 2.0 syntaxElyes Haouas2022-12-261-1/+1
* nb/intel/sandybridge/raminit_common.h: Add needed <device/dram/ddr3.h>Elyes Haouas2022-12-221-0/+1
* nb/intel/haswell: Add native raminit scaffoldingAngel Pons2022-12-164-6/+320
* sb/intel/lynxpoint: Add native PCH initAngel Pons2022-12-161-2/+1
* sb/intel/lynxpoint: Add native thermal initAngel Pons2022-12-161-0/+1
* sb/intel/lynxpoint: Add native USB initAngel Pons2022-12-161-0/+3
* haswell/lynxpoint: Add native early ME initAngel Pons2022-12-161-1/+16
* haswell/lynxpoint: Add native DMI initAngel Pons2022-12-167-0/+407
* nb/intel/sandybridge/sandybridge.h: Remove unnecessary guardElyes Haouas2022-12-151-5/+2
* nb/intel/haswell: Introduce option to not use MRC.binAngel Pons2022-12-124-1/+37
* treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas2022-12-101-1/+1
* nb/intel/pineview: Use read32p()Elyes Haouas2022-12-061-2/+2
* nb/intel/haswell: Use {read,write}32p()Elyes Haouas2022-12-062-5/+5
* nb/intel/x4x: Use read32p()Elyes Haouas2022-12-061-1/+1
* nb/intel/e7505: Use read32p()Elyes Haouas2022-12-061-1/+1
* nb/intel/sandybridge: Use read{8,32}p()Elyes Haouas2022-12-061-2/+2
* nb/intel/sandybridge: Use write32p()Elyes Haouas2022-12-062-9/+9
* cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans2022-12-054-0/+21
* nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clockElyes Haouas2022-12-021-1/+2
* nb/intel/pineview: Remove unused 'gpu_lvds_use_spread_spectrum_clock'Elyes Haouas2022-12-021-1/+0
* nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans2022-12-011-12/+2
* nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans2022-12-011-12/+2
* nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans2022-12-011-13/+2
* cpu/intel/model_206ax: Remove fake lapic deviceArthur Heymans2022-12-012-12/+6
* cpu/intel/sandybridge: Use enum for ACPI C statesArthur Heymans2022-12-011-3/+3
* nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetreeArthur Heymans2022-11-302-13/+4
* nb/intel/sandybridge: Add a chipset devicetreeArthur Heymans2022-11-302-0/+21
* nb/intel/e7505: Hook up PCI domain and CPU ops to devicetreeKyösti Mälkki2022-11-301-13/+2
* aopen/dxplplusu: Support SMM_ASEG and SMM_TSEGKyösti Mälkki2022-11-285-18/+98
* cpu/intel/haswell: Move chip_ops to cpu clusterArthur Heymans2022-11-251-1/+1
* src/northbridge: Remove unnecessary space after castsElyes Haouas2022-11-2212-47/+47
* cbmem_top_chipset: Change the return value to uintptr_tElyes Haouas2022-11-189-23/+22
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