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* soc: Add SPDX license headers to Kconfig filesMartin Roth2024-02-181-0/+2
| | | | | | | | | | Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: Move PSP_VERSTAGE_MAP_ENTIRE_SPIROM configKarthikeyan Ramasubramanian2023-11-281-1/+0
| | | | | | | | | | | | | | | Select PSP_VERSTAGE_MAP_ENTIRE_SPIROM in Cezanne Kconfig instead of common Kconfig. BUG=None TEST=Build BIOS image and boot to OS in dewatt. Change-Id: I476971700824fed06d17000001afc075105fa1ee Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79306 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/psp_verstage: Make SPI ROM mapping configurableKarthikeyan Ramasubramanian2023-11-281-0/+8
| | | | | | | | | | | | | | | | | | | | | Earlier entire SPI ROM was mapped to memory. With limited TLB resources in PSP, this approach hit the limit on systems using 32 MiB SPI ROM. Therefore regions in SPI ROM were mapped on need basis. This works well on Picasso, Mendocino and Phoenix SoCs. But unfortunately this causes boot hangs in Cezanne SoC. Add a configuration to map the entire SPI ROM and enable it in Cezanne SoC. For other SoCs, keep the configuration disabled so that only the required SPI ROM region is mapped. BUG=b:309690716 TEST=Build and boot to OS in both Dewatt and Skyrim. Change-Id: I166ac7b50b367c067e1a743fc94686e69dd07844 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/psp_verstage: Add PSP_VERSTACK_STACK_IS_MAPPED configKarthikeyan Ramasubramanian2023-10-201-0/+8
| | | | | | | | | | | | | | | | | | | | Crypto Engine in PSP prefers the buffer from Static RAM (SRAM). Hence if a buffer comes from within SRAM address range, then it is passed directly to Crypto Engine. Otherwise a bounce bufer from the stack is used. But on SoCs like Picasso where PSP Verstage stack is mapped to a virtual address space this check fails causing a bounce buffer to be used and hence a stack overflow. Fix this issue by assuming that the buffer comes from the SRAM always in such SoCs and pass the buffer directly to crypto engine. BUG=b:259649666 TEST=Build and boot to OS in Dalboz with unsigned PSP verstage. Change-Id: I2161c8f0720c770efa5c05aece9584c3cbe7712a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/amd/common: Add a config to keep signed AMD/PSP FW separatelyKarthikeyan Ramasubramanian2022-10-021-0/+6
| | | | | | | | | | | | | | | | | | | | Enabling this config will put signed amd firmwares into SIGNED_AMDFW_[AB] region which is outside FW_MAIN_[AB]. Vboot only verifies FW_MAIN_[AB] so these regions will not be verified by vboot, instead the PSP will verify them. As a result we have less to load and verify from SPI rom which means faster boot time. BUG=b:206909680 TEST=Build Skyrim with modified fmap and Kconfig. Change-Id: If4fd3cff11a38d82afb8c5ce379f1d1b5b9adfbf Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59867 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/psp_verstage: Fix update_boot_regionKarthikeyan Ramasubramanian2022-07-201-0/+8
| | | | | | | | | | | | | | | | | | | | | | | On SoCs where PSP use A/B recovery layout, PSP expects PSP L2 directory address relative to the start of the SPI ROM. Unfortunately there is nothing in the EFS2 header to help identify such SoCs. Hence add a config item to statically identify such SoCs. Also when PSP uses A/B recovery layout, BIOS L2 directory is an entry in the PSP L2 directory. Hence the address of BIOS L2 directory is not part of EFS2 header. Thankfully PSP is able to identify the BIOS L2 directory itself and does not expect PSP verstage to pass the address. Modify PSP verstage to handle these updates. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that PSP verstage returned the PSP L2 directory as expected. Change-Id: I2f856a62055c80b8e2db91c983832611a5f0389c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/{cezanne,common}: Add PSP_S0I3_RESUME_VERSTAGE Kconfig optionRob Barnes2021-12-141-2/+9
| | | | | | | | | | | | | | | | | Add PSP_S0I3_RESUME_VERSTAGE Kconfig option. When enabled, verstage will be run in PSP during S0i3 resume. Setting softfuse bit 40 enables this in PSP. BUG=b:200578885, b:202397678 BRANCH=None TEST=Verstage runs during s0i3 resume on Nipperkin Change-Id: I2c185f787c1e77bd09f6cbbb1f47deb665ed0c79 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/psp_verstage: Init TPM on S0i3 resumeRob Barnes2021-11-221-0/+9
| | | | | | | | | | | | | | | | | | Add option to initialize the TPM in PSP verstage during s0i3 resume. This is needed if the TPM is reset in s0i3. FSDL is handling restoring everything else, so only the minimum TPM initialization is done. Move aoac and i2c init before psp_verstrage_s0i3_resume becasue i2c needs to be ready before attempting to restore tpm. BUG=b:200578885,b:197965075 TEST=Multiple cycles of S0i3 suspend resume. ~66ms of additional delay. BRANCH=None Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/common/psp_verstage: Introduce boot device driverKarthikeyan Ramasubramanian2021-09-271-0/+7
PSP verstage can access the boot device either in Programmed I/O mode or DMA mode. Introduce a boot device driver and use the appropriate mode based on the SoC support. BUG=b:194990811 TEST=Build and boot to OS in Guybrush. Change-Id: I8ca5290156199548916852e48f4e11de7cb886fb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57563 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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