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* vendor: mediatek: Add mediatek mt8192 dram initialization codeXi Chen2021-03-0852-0/+85564
| | | | | | | | | | | | | | | | | | This is the DRAM initialization code from the reference implementation released by Mediatek for MT8192. The DRAM calibration code can be taken as a standalone library, used by different boot loaders for initializing DRAM and following a different coding style (coreboot was using Linux Kernel coding style), so we have to put it in vendor code folder. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/google/kukui: Add Micron 4GB discrete LPDDR4X DDR supportJessy Jiang2021-03-083-0/+29
| | | | | | | | | | | | | | Support 4G+128G MT29VZZZAD9GQFSM-046 W.9S9 discrete DDR bootup. BUG=b:162292216 BRANCH=kukui TEST=Boots correctly on Kukui. Signed-off-by: Jessy Jiang <jiangchao5@huaqin.corp-partner.google.com> Change-Id: I5657a007154bc52c6f0f27e1de6e3294a5e74ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* nb/intel/haswell: Indent PCI ops with tabsAngel Pons2021-03-071-5/+5
| | | | | | | | Change-Id: Ia338ce1a36aa0a14017201c1fc16f84915f55c07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb/intel/lynxpoint/me.c: Reorder functionsAngel Pons2021-03-071-115/+113
| | | | | | | | | | | | Rearrange the code to ease comparing against Broadwell. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3143f07ed845e0c6b1444817029a437db3b959e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb/intel/lynxpoint: Finalize ME in ramstageAngel Pons2021-03-074-47/+15
| | | | | | | | | | | | Performing ME finalization in SMM does not seem to be required. Tested on Asrock B85M Pro4, ME still gets finalized successfully. Change-Id: I9fde40a54f3fb8da2fba46c531443fdd2e067077 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb/intel/lynxpoint/me.c: Use res2mmio()Angel Pons2021-03-071-1/+1
| | | | | | | | | | | Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I87fa1ffb353135cc361ac6be30a4fc69e7f8ed47 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* sb/intel/lynxpoint: Retype `mei_base_address` pointerAngel Pons2021-03-071-9/+9
| | | | | | | | | | Also introduce uintptr_t cast and use PCI_BASE_ADDRESS_MEM_ATTR_MASK. Change-Id: I32fdcc6b1ffde1b0701218a3bd0a61ab827081b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb/intel/common/pciehp: Replace HP dummy device with common codeArthur Heymans2021-03-077-54/+24
| | | | | | | | | | | | | | | | | Use the common PCIEXP_HOTPLUG code to generate a dummy device for PCIe ports supporting hotplug. This allows to have control over how much resources are allocated to hotplug ports. Tested on thinkpad X220: now hotplugging a dGPU via the expresscard slot sometimes works. Change-Id: I3eec5214c9d200ef97d1ccfdc00e8ea0ee7cfbc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph
* mb/google/brya: Move GPE configuration to baseboard/devicetree.cbFurquan Shaikh2021-03-062-4/+5
| | | | | | | | | | | | | | | | This change moves GPE configuration from brya0/overridetree.cb to baseboard/devicetree.cb since all variants will end up using the same configuration. TEST=Verified using "abuild -p none -t google/brya -b brya0 --timeless" that coreboot.rom generated with and without this change is the same. Change-Id: Ie31bf2bf8a91da82fca77c78fb0a735a2645de55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Fix MAINBOARD_PART_NUMBERFurquan Shaikh2021-03-061-1/+1
| | | | | | | | | | | | | | This change updates MAINBOARD_PART_NUMBER string to use uppercase for first character. This matches what all others boards do. BUG=b:180456030 Change-Id: I10eaeef5ec662a5718b787a3f0e3705cf70d751d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51297 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: move APOB NV cache to common codeFelix Held2021-03-068-16/+24
| | | | | | | | | | | | Also rename mrc_cache to apob_cache. BUG=b:181766974 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4877b05443452c7409006c1656e9d574e93150a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/adl, mb/google/brya: Add IPU to devicetreeTim Wawrzynczak2021-03-053-0/+3
| | | | | | | | | | BUG=b:181843816 Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya: Add IPU ASL to DSDTTim Wawrzynczak2021-03-051-0/+1
| | | | | | | | | | BUG=b:181843816 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I74246cd0d2f866022604ec3e8a8d523c273cdef4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/brya: brya0: Add ACPI support for Type-C portsTim Wawrzynczak2021-03-053-1/+26
| | | | | | | | | | BUG=b:181160586, b:181843816 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51258 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer: Configure tcss port information for early tcss initBrandon Breitenstein2021-03-052-0/+59
| | | | | | | | | | | | | | | | | | | Implement the mainboard_tcss_get_port_info weak function so that the TCSS muxes can be properly configured to ensure mapping is correct in mux. This ensures that any devices that are connected during boot are not improperly configured by the Kernel. BUG=b:180426950 BRANCH=firmare-volteer-13672.B TEST= Verified that the SOC code that initialized TCSS muxes to disconnect mode is executing properly for all TCSS ports and verified that USB3 devices are no longer downgrading to USB2 speed if connected during boot. Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during bootBrandon Breitenstein2021-03-055-53/+118
| | | | | | | | | | | | | | | | | | | TCSS muxes being left uninitialized during boot is causing some USB3 devices to downgrade to USB2 speed. To properly configure the Type C ports the muxes should be set to disconnected state during boot so that the port mapping of USB2/3 devices is properly setup prior to Kernel initializing devices. BUG=b:180426950 BRANCH=firmware-volteer-13672.B TEST= Connected USB3 storage device and rebooted the system multiple times to verify that devices were no longer downgrading to USB2 speed. Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* drivers/intel/gma/gma.ads: Uniformize casingAngel Pons2021-03-051-1/+1
| | | | | | | | | | Use lowercase `port` in both the spec and the body. Change-Id: I3d1e2abe03eedcaf57716af444a3e3b8a61b60d4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb/ti/pcixx12: Remove NOOP chip driverArthur Heymans2021-03-052-14/+1
| | | | | | | | Change-Id: I46bc854239e723a1685279f634e635b72e7b3af9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb/intel/lynxpoint: Refactor `usb_xhci_port_count_usb3`Angel Pons2021-03-051-9/+10
| | | | | | | | | | Change the function parameters to avoid preprocessor usage. Change-Id: Iec43e057ed2a629e702e0f484ff7f19fe8a0311b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/broadwell/pch: Rename USB filesAngel Pons2021-03-053-3/+3
| | | | | | | | | | | Done to ease diffing against Lynxpoint. Change-Id: Ib4280b26799eab6d4a2bb41a14a76695caa31e86 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* soc/intel/broadwell/pch: Use Lynx Point smbus.cAngel Pons2021-03-056-79/+3
| | | | | | | | | | | | Continue unifying Lynx Point and Wildcat Point (PCH for Broadwell) code. Define the WPT-LP SMBus PCI device ID, add it to smbus.c of Lynx Point, and drop all now-unnecessary SMBus code from Broadwell. Change-Id: I864d7c2dd47895a3c559e2f1219425cda9fd0c17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* security/tpm/tss/vendor/cr50: Introduce vendor sub-command to reset ECKarthikeyan Ramasubramanian2021-03-053-0/+42
| | | | | | | | | | | | | | | Add marshaling and unmarshaling support for cr50 vendor sub-command to reset EC and a interface function to exchange the same. BUG=b:181051734 TEST=Build and boot to OS in drawlat. Ensure that when the command is issued, EC reset is triggered. Change-Id: I46063678511d27fea5eabbd12fc3af0b1df68143 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/dedede/var/blipper: Generate SPD ID for supported memory partsZanxi Chen2021-03-053-13/+8
| | | | | | | | | | | | | | | | | | Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE BUG=None TEST=Build the blipper board. Change-Id: Ia7e4c1d5c06013c1902816d6dcafb5a8a0386bb3 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/intel/apollolake: Add `GPE0_STS_BIT` macroAngel Pons2021-03-052-1/+7
| | | | | | | | | | | | | | The datasheet indicates that this bit is reserved. However, subsequent patches need to use this macro in common code, or else builds fail. To iron out this difference, mask out the bit in `soc_get_smi_status`, so that common code always sees it as zero. Finally, add an entry for the bit in `smi_sts_bits` for debugging usage, noting that it is reserved. Change-Id: Ib4408e016ba29cf8f7b125c95bfa668136b9eb93 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/common/block/cpu: Use tab instead of spaceSubrata Banik2021-03-051-3/+3
| | | | | | | | | | | | Convert the lines starts with whitespace with tab as applicable. Change-Id: Ife7b27360661cbfd2c90e2b643ed31225ded228c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51250 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork/var/vilboz: Update telemetry settingsJohn Su2021-03-051-4/+4
| | | | | | | | | | | | | | | | | | | | | | | Update telemetry settings for vilboz. VDD Slope : 26939 -> 27225 VDD Offset: 125 -> 187 SOC Slope : 20001 -> 26559 SOC Offset: 168 -> 89 BUG=b:177162553 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Iaf7c5083c4c5affec5ae0b5583efb5237e10d0ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/51165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* mb/google/volteer: Fix FPMCU pwr/rst gpio handlingNick Vaccaro2021-03-0533-36/+395
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. No gpio control in bootblock 2. Power on and then deassert reset at the end of ramstage gpio 3. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #3 and wrapping around to #2. This change affects the following volteer variants that include an FPMCU: 1. Drobit 2. Eldrid 3. Elemi 4. Halvor 5. Malefor 6. Terrador 7. Trondo 8. Voema 9. Volteer2 10. Voxel BUG=b:178094376 TEST=none Change-Id: Ib51815349cea299907c10d6c56c27bd239e499e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and socBrandon Breitenstein2021-03-053-14/+26
| | | | | | | | | | | | | | | | | The original implementation of early tcss resulted in calling to mainboard then back to soc then back to mainboard to properly configure the muxes. This patch addresses that issue and instead just gets all the mux information from mainboard and does all config in the soc code. BUG=none BRANCH=firmware-volteer-13672.B TEST=Verified functionality is not effected and early TCSS still functions Change-Id: Idd50b0ffe1d56dffc3698e07c6e4bc4540d45e73 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/tigerlake: Fix NULL being passed for response bufferFurquan Shaikh2021-03-051-18/+14
| | | | | | | | | | | | | | | | | | | | | `pmc_send_ipc_cmd()` expects the caller to pass in a pointer to a valid request and response buffer. However, early_tcss driver was passing in a NULL pointer for response buffer which would result in invalid access by `pmc_send_ipc_cmd()`. Currently, the response buffer is not used in `update_tcss_mux()`. So, this change drops the passing of `rbuf` parameter to `send_pmc*` helpers and instead uses a local `rsp` variable in the respective functions. All the PMC functions used in early_tcss driver return some kind of response. These should be checked to return appropriate response code back to the caller. However, this needs to be done as a separate change. Change-Id: I215af85feed60b6beee17f28e3d65daa9ad4ae69 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/amd/cezanne/chipset.cb: clean up and change some aliasesFelix Held2021-03-041-24/+24
| | | | | | | | | | | | With the aliases some of the comments are redundant. I'm still not sure if the Ethernet controller on the embedded SKUs supports 10G or only 1G. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e432c12f92a622f8ee05be19acb2c304dd74afb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
* vc/amd/fsp/picasso: fix DDI enum name prefixFelix Held2021-03-041-3/+3
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12ec6a3c2704effc1a626181898a9ed7a17f0640 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51239 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne/smihandler: implement S3 entry SMI handlerFelix Held2021-03-041-1/+23
| | | | | | | | | | | | | | Since the support for the GSMI ELOG isn't implemented in the SMI handler yet, the corresponding code isn't added to fch_slp_typ_handler in this patch. BUG=b:181766974 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia27b2486dde1a373607ce895a975e873d9026ba1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/cezanne: add SMU supportFelix Held2021-03-044-0/+45
| | | | | | | | | | BUG=b:181766974 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5b9b4c3d57945ea7c3287cf47f3d9704f42ff24b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* src/drivers/i2c/rx6110sa: Add official ACPI IDWerner Zeh2021-03-042-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | In commit 2609eaaa8f (src/drivers/i2c/rx6110sa: Omit _HID temporarily) the randomly assigned and therefore wrong ACPI ID for RTC RX6110SA was removed. In the meantime Seiko-Epson did a great job and registered an official vendor ID in the ACPI database [1]. Further on, Seiko-Epson has now assigned the unique Product Identifier for the RX6110SA, which is '6110'. The assignment of the Product Identifier is controlled by the vendor and there is no official database where this ID is stored in. It is up to the vendor to make sure that this ID stays unique. This patch adds this new vendor and product ID to the driver. Together with a pending Linux patch this RTC is now useable as ACPI device in Linux. [1] https://uefi.org/ACPI_ID_List?search=SECC Change-Id: I45838162f014a760520692c6dcaae329ad98547d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51176 Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Johannes Hahn <johannes-hahn@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/generic/max98357a: Use depends HAVE_ACPI_TABLESEric Lai2021-03-042-5/+1
| | | | | | | | | | | | Replace if HAVE_ACPI_TABLES statement with depends HAVE_ACPI_TABLES. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie6ebfde49f0f3c205e174c5113feb75444dedba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* drivers/generic/alc1015: add ALC1015 AMP driverEric Lai2021-03-044-0/+83
| | | | | | | | | | | | | | Add ALC1015 AMP support. ALC1015Q-VB Datasheet Rev 0.1 BUG=b:177971830 TEST: ALC1015P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id93845024aa2cded69acc88d594c222f2f821f79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51051 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/volteer/variants/copano: Describe USB ports in devicetreehao_chou2021-03-041-10/+13
| | | | | | | | | | | | | | | | | Modify USB port to match schematics. And assigned USB2 port to type-c use. BUG=b:177481079 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Change-Id: I25412d16df8ad809c05635022c11bd8882d002c5 Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49980 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/rockchip/rk3399/sdram: Add channel to error messageMoritz Fischer2021-03-041-5/+5
| | | | | | | | | | | | When printing error information during DRAM training, be more verbose by printing the channel number. Change-Id: If4109bd0573e3d9f90d699d89350ddbcc48714d3 Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/rockchip/rk3399/sdram: Simplify error conditionMoritz Fischer2021-03-041-1/+1
| | | | | | | | | | | | There is no need for explicit 0 comparison, any return value not equal to 0 is treated as error. Change-Id: I72612af4108a616b6247ee68c8ac2a53242b0853 Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
* vc/amd/fsp/picasso: increase FSPS UPD block size from 0x152 to 0x202Nikolai Vyssotski2021-03-031-2/+2
| | | | | | | | | | | | | | We will need more FSPS UPD space for PEI GOP changes coming. BUG=b:171234996 BRANCH=Zork Cq-Depend: chrome-internal:3609213, chromium:50576 Change-Id: I35d0bb0ee30e04f66882b6103acd9d673d040c07 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/cezanne/chipset.cb: rename alias for SATA controllersFelix Held2021-03-031-2/+2
| | | | | | | | | | | Renoir/Cezanne have two SATA controllers with 2 ports each, so call them sata_0 and sata_1. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ebfd3a85f9b513901f205bc299e92564fa329e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51190 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/zork/var/vilboz: Update WiFi SAR for VilbozFrank Wu2021-03-031-5/+1
| | | | | | | | | | | | | | | | Loading wifi_sar-vilboz-1.hex for vilboz360 LTE sku for the present. BUG=b:177684735, b:176168400 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I477b55d64fd9d33d753b10b2de443041a12d13e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kangheui Won <khwon@chromium.org>
* mb/amd/majolica: Add eSPI supportZheng Bao2021-03-032-0/+13
| | | | | | | | | Change-Id: I3e82a51173f561df560c36528a9b7ec26cf489b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/brya: Add support for 2 new DRAM partsAmanda Huang2021-03-033-0/+6
| | | | | | | | | | | | | | | 1) Micron MT53E1G32D2NP-046 2) Micron MT53E2G32D4NQ-046 BUG=b:181378727 TEST=none Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* util: Add new memory part to LP4x listAmanda Huang2021-03-033-0/+67
| | | | | | | | | | | | | | | | | Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes are derived from data sheets.Also, regenerate the SPD files for ADL SoC using the newly added parts. BUG=b:181378727 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/google/brya: fix BT enumeration issueAamir Bohra2021-03-031-1/+1
| | | | | | | | | | | | | | | Current implementation exposes GPP_F4 cnvi reset pin as reset gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven by SoC. It should not be driven by driver. BUG=b:180875586 Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51178 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/smbus: Add config to use ACPIMaxim Polyakov2021-03-031-0/+7
| | | | | | | | Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44865 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Guard macro parameters in pm.hAngel Pons2021-03-034-9/+9
| | | | | | | | | | Guard against unintended operator precedence and associativity issues. Change-Id: I342682a57fde9942cdf7be10756ee21c10af802a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50917 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Move `gpi_clear_int_cfg()` callAngel Pons2021-03-032-5/+7
| | | | | | | | | | | To allow unifying bootblock.c in follow-ups, move a function call. Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel: Factor out common smmrelocate.cAngel Pons2021-03-0323-1507/+12
| | | | | | | | | | | There are seven identical copies of the same file. One is enough. Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 01:38:55 +0000