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* include: Add SPDX-License-Identifiers to files missing themMartin Roth2022-08-0150-2/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds SPDX-License-Identifiers to all of the files in src/include that are missing them or have unrecognized identifiers. Files that were written specifically for coreboot and don't have license information are licensed GPL-2.0-only, which is the license for the overall coreboot project. Files that were sourced from Linux are similarly GPL-2.0-only. The cpu/power files were committed with source that was licensed as GPL-2.0-or-later, so presumably that's the license for that entire commit. The final file, vbe.h gives a pointer to the BSD-2-Clause license at opensource.org. Change-Id: I3f8fd7848ce11c1a0060e05903fb17a7583b4725 Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Revert "UPSTREAM: soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for ↵Karthikeyan Ramasubramanian2022-08-012-24/+2
| | | | | | | | | | | | | | | | | | | Sabrina" This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035. Reason for revert: Now that PSP supports a soft fuse flag to toggle the verstage serial logs, prevent PSP verstage from writing to the UART. BUG=None TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP verstage logs are not seen twice in the console. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/sabrina: Enable HW Modexp engineKarthikeyan Ramasubramanian2022-08-012-2/+8
| | | | | | | | | | | | | | | | | | HW Modexp engine is verified to be working fine. Any verification failures during PSP verstage are because the firmware body is not read correctly. This might be because of the incorrect SPI ROM mapping. Hence enable the HW modexp engine for keyblock, preamble and firmware body verification. BUG=b:240175446 TEST=Build and boot to OS in Skyrim with PSP verstage using one of the FW slots. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8f6742630a7049354a24053fce28c477e53259e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* drivers/elog: Use format stringMatei Dibu2022-08-011-1/+1
| | | | | | | | | | | | | | | | | | clang shows the warning below: src/drivers/elog/elog.c:171:13: error: format string is not a string literal (potentially insecure) [-Werror,-Wformat-security] elog_debug(msg); ^~~ Found-by: clang (13.0.1) Change-Id: I3f8949f9ce0c4ef4823530c61c503b0883bb5efc Signed-off-by: Matei Dibu <matdibu@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66262 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* soc/qualcomm: Add PCIe supportPrasad Malisetty2022-07-313-0/+956
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe platform driver for Qualcomm platforms. Reference: - linux/drivers/pci/controller/dwc/pcie-qcom.c - Linux driver base commit: 82a823833f4e3769e82cdb4df1bc2234bc65b16c BUG=b:182963902,b:216686574,b:181098581 TEST=Verified on Qualcomm sc7280 development board with NVMe card (Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is getting detected in response to 'storage init' command in depthcharge CLI prompt. Output logs: ->dpch: storage init Initializing NVMe controller 1e0f:0001 Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0 * 0: NVMe Namespace 1 1 devices total Also verified NVMe boot path, that is depthcharge is able to load the kernel image from NVMe storage. Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com> Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53902 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel/fsp: Fix wrong licenseBora Guvendik2022-07-301-28/+9
| | | | | | | | | | | | | | Fix the license in header file. BUG=none BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I025f7c571d09e4cc63a659279e63d17c098c01cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/66253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* mb/hp/z220_series: Improve the port for z220_sff_workstationBill XIE2022-07-302-2/+6
| | | | | | | | | | | | | | | | | | | - Move configs for PCIe ports not present on z220_sff_workstation from the devicetree.cb of base board to the overridetree.cb of z220_cmt_workstation. - Add a note for ME/AMT Flash Override jumper, for it is hard to flash from OEM firmware either internally or externally without closing this jumper. - Add a side note for similar HP Compaq Elite 8300 SFF. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I35d8b97f52a83910a61c12b1f7367ee7a19a9ad7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brask/variants/moli: Add DPTF setting in MoliRaihow Shi2022-07-301-0/+74
| | | | | | | | | | | | | DPTF Policy and temperature sensor values from thermal team. BUG=b:236294162 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Iebcfb74c4bc719e6d8d8d9317435becd912eaf85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* security/vboot: Simplify image signingJakub Czapiga2022-07-301-31/+13
| | | | | | | | | | | | | | futility now supports image truncation and signing of whole images with a single command invocation. Use it for vboot-enabled coreboot images. TEST=Build and run coreboot on google/volteer Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I49eb7e977b635ccb9f6c1b76e53c36e82be1d795 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* arch/x86/acpi: Replace Store() with ASL 2.0 syntaxFelix Singer2022-07-302-26/+26
| | | | | | | | | Change-Id: I30bbd0288475fbefec55ce294e7963df1de6aa6a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* arch/x86/acpi: Replace And() with ASL 2.0 syntaxFelix Singer2022-07-301-3/+3
| | | | | | | | | Change-Id: I21b954ce62259bb77d88775c3086cfac17dd90c7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* arch/x86/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-301-3/+2
| | | | | | | | | | | | Replace `LNotEqual(a, b)` with `a != b`. Change-Id: If0e9fcea680d487c28a965e944b3333bb5a07026 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60696 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/acpi: Replace LLess(a,b) with ASL 2.0 syntaxFelix Singer2022-07-302-8/+8
| | | | | | | | | | | | Replace `LLess(a, b)` with `a < b`. Change-Id: Ief1d069ae0fb19a2179f08c2e9cf416367661e69 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60674 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer2022-07-291-2/+2
| | | | | | | | | | | Replace `Add (a, b, c)` with `c = a + b`. Change-Id: If848d391e5ec33ebfb08515414739dbdd5011e08 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* mb/google/rex: Perform display configuration overrideSubrata Banik2022-07-291-0/+11
| | | | | | | | | | | | | | This patch enables display port configuration as per the Rex schematics. TEST=Able to dump FSP UPD to ensure the override is successful. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e81d037416e46e52cb72344425d6d8725dae192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/google/nissa/var/pujjo: Enable OZ711LV2LN SD card controllerStanley Wu2022-07-291-0/+1
| | | | | | | | | | | | | | Pujjoflex support OZ711LV2LN SD card controller, Select the Bayhub LV2 driver for OZ711LV2LN SD card. BUG=b:215487382 TEST=Build FW and checking SD card work as expected in OS. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I6759fde1eaf24599a1fdb364d6e78f4e4e12f311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/rex: Add LP5 RAM IDsTarun Tuli2022-07-293-0/+6
| | | | | | | | | | | | | | | | | | Create RAM IDs for: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D2DS-026 WT:B 1 (0001) MT62F2G32D4DS-026 WT:B 2 (0010) BUG=b:240289148 TEST=emerge-rex coreboot Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ib24e07bca363984db3484aa500f7d6ea4817e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* soc/mediatek/mt8188: Add SPI supportLiya Li2022-07-293-1/+102
| | | | | | | | | | | | | | | | The gpios and the tick delay register are different between MT8188 and previous MediaTek SoCs, so we need to add this patch to support SPI. TEST=build pass BUG=b:236331724 Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com> Change-Id: I6065b9d285dfd36c191f274f500fdb694920276e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66185 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Create GET_TICK_DLY_REG macro for SPI tick delay settingRex-BC Chen2022-07-296-8/+13
| | | | | | | | | | | | | | | MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which is different from previous SoCs, so we define a macro to get the designated register. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Initialize RTC and clk_buf in romstageRex-BC Chen2022-07-291-0/+4
| | | | | | | | | | | | TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I869c0879d09e00cf66882adb728c9ccb6ac57e03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66183 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add clk_buf support in romstageSong Fan2022-07-291-0/+1
| | | | | | | | | | | | TEST=build pass. BUG=b:233720142 Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com> Change-Id: Ic300b70a38ac204b098ca9ab15cf7045b66fd76d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66182 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add RTC supportSong Fan2022-07-292-0/+94
| | | | | | | | | | | | | | Add RTC header file for SoC-specific settings. Add RTC support in romstage. TEST=build pass. BUG=b:233720142 Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com> Change-Id: I38115ce0c9a4e1c1b2b7c8e6d40f47e99f7f86b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66181 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move common definitions from rtc.h to rtc_reg_common.hRex-BC Chen2022-07-295-528/+163
| | | | | | | | | | | | | | | Move the common definitions to rtc_reg_common.h, so we can reuse those definitions on MT8188. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add AUXADC supportHui Liu2022-07-293-0/+35
| | | | | | | | | | | TEST=get voltage as 340mV for channel 0 in MTK EVB. BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: Idd1edcce6cb62fcf6991bb9342c409150989c5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/66121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Move struct mtk_auxadc_regs to auxadc_common.hRex-BC Chen2022-07-295-44/+11
| | | | | | | | | | | | | | The AUXADC register definitions are the same for all MediaTek SoCs, so we move struct mtk_auxadc_regs to auxadc_common.h. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I48978a93137a7de42f8ea2873be3130cb8f534f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/rex: Enable CNVi BT CoreSubrata Banik2022-07-291-0/+3
| | | | | | | | | | This patch override `CnviBtCore` FSP UPD. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I90c9b360969aada0b0e031d62b48476fac5cee0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/ghost: Enable CS42L42 codecEric Lai2022-07-293-2/+21
| | | | | | | | | | | | | | | Add CS42L42 support in device tree. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=Check cs42l42 driver can probe successfully in kernel. cs42l42 i2c-10134242:00: Cirrus Logic CS42L42, Revision: B1 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I861f47c12f4cebb016a4cfbe225f97d34d55e233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* mb/google/brya/var/ghost: Update all I2C buses speed to fastEric Lai2022-07-291-23/+5
| | | | | | | | | | | | | | | Remove the parameter and set I2C bus speed to fast. Will fill the tuning value after real tuning. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Iba7fe4551959617ecfa49719c1124bf85d624c31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* mb/google/brya: Create gaelin variantRaymond Chung2022-07-295-0/+28
| | | | | | | | | | | | | | | | | | Create the gaelin variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:239514438 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GAELIN Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Change-Id: I7f1ff8690c7c57f8960e004d0490d5cede8667f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* soc/intel/alderlake: Add missing TDP and Power Limits for ADL-SMichał Żygowski2022-07-292-1/+53
| | | | | | | | | | | | | Add TDP and Power Limit settings for ADL-S 8+8 150W, 4+0 and 2+0. The System Agent PCI IDs were not present in older 2.1 revision of DOC #619501. Now that the mapping of these IDs to SKUs is known, fill the missing TDPs and Power Limit settings based on DOC #626343. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I23dd8478e60bcc81a1048f2f6e6717dd281d1a69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* soc/intel/alderlake: Set VccIn Aux Imon IccMax for ADL-S 4+0 and 2+0Michał Żygowski2022-07-291-0/+2
| | | | | | | | | | | | Add missing System Agent PCI IDs for ADL-S 4+0 and 2+0 to configure VccIn Aux Imon IccMax. They were not present in older 2.1 revision of DOC #619501. Based on DOC #619501 rev 2.6. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Idfd57ce9b63db5d5fcc9d4efb8aa27ed7cc6222d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* soc/intel/alderlake/vr_config.c: Add VR params for ADL-SMichał Żygowski2022-07-291-0/+60
| | | | | | | | | | Based on DOC #619501, #634885, #626343. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib50db521e4d127a773f903b45d4bec5c5cc180d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* intel/pmclib: Avoid PMC ABASE read of SLP_TYP and STATUS in ramstageHarsha B R2022-07-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch updates platform_is_resuming() API such that platform resume state is determined from the saved state (CBMEM) instead of checking PMC registers (PM1_STS & PM1_CNT) as they are getting cleared (before/early) ramstage. coreboot sends DISCONNECT IPC command which times out during resume (S3) if system has servoV4 connected on port0. The issue occurs only during the first cycle of resume (S3) test cycle after cold boot due to side effect of platform_is_resuming() API that is not determining the resume (S3) state correctly in ramstage. PM1_STS and PM1_CNT register gets cleared at the start of ramstage. platform_is_resuming() function was checks the cleared register value and fails the condition of resume (S3) resulting in sending DISCONNECT IPC command. Checking the platform resume state from the CBMEM saved state using acpe_get_sleep_type() function helps cross verify the system previous state at the later part of ramstage. localhost ~ # cbmem -c | grep ERROR [ERROR] EC returned error result code 3 [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0x200a7 failed [ERROR] pmc_send_ipc_cmd failed [ERROR] Failed to setup port:0 to initial state [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0x200a7 failed [ERROR] pmc_send_ipc_cmd failed [ERROR] Failed to setup port:1 to initial state [ERROR] GENERIC: 0.0 missing read_resources [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0xd0 failed [ERROR] PMC: Failed sending PCI Enumeration Done Command BUG=b:227289581 TEST=Verified system boots to OS and verified below tests on Redrix (ADL-P) and Nivviks (ADL-N) 1. coreboot doesn't send the DISCONNECT during S3 resume 2. suspend S3 passes with both suzyq and servoV4 connected 3. After S3 resume, system detects the pen drive with Superspeed 4. After system resumes from S3, hot-plug the pen drive, system detects the pen drive Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I353ab49073bc4b5288943e19a75efa04bd809227 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66126 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/drawcia: Enable weida touchscreenShon Wang2022-07-291-0/+14
| | | | | | | | | | | | | | | Add weida touchscreen support for drawcia. BRANCH=dedede TEST=Build and verify that touchscreen works on drawcia. Change-Id: Ic76f3529771c6eeeafef7ca50fc400065aac2211 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65471 Reviewed-by: Ivan Chen <yulunchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* sb/intel/bd82x6x/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-5/+5
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I4e219bea8df64db1d49beb8534f0f37fee0df5b6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* sb/intel/i82801ix/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-4/+4
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: Ifffd21a663739f72a5584e26b79b0627dd532d9e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* sb/intel/i82801jx/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-4/+4
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I3aebd29bba285229979b79867c881018f61e2060 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* soc/intel/common/sata: Add APL and GLK SATA PCI IDsSean Rhodes2022-07-291-0/+2
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0ae8c6624b79ce6c269244bd1435900d4d7f997a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/nissa/var/joxer: Correct i2c address for touchscreenMark Hsieh2022-07-281-1/+1
| | | | | | | | | | | | | set i2c address to 0x14 for Goodix touchscreen BUG=b:239180430 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I11a2d9c684bc511b3942f88f74a2495e796bc3c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/acpi: Add L23 entry/exit sequences during dGPU GCOFFTim Wawrzynczak2022-07-281-0/+2
| | | | | | | | | | | | | | | | | | When the dGPU is entering GCOFF, the link should first be placed into L2/L3 as appropriate for the design, then when exiting, the link should be placed back into L0. This patch fixes that oversight. BUG=b:239719056 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia3bdfe5641216675e06ebe82ffe58bf8c049b26b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Modify GPP_A8 programmingTim Wawrzynczak2022-07-281-1/+1
| | | | | | | | | | | | | | | | The EEs noticed this pin was misbehaving; it was accidentally set to a low output, but should be open-drain (NC). This patch fixes that. BUG=b:237837108 TEST=verified by EEs Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie76a951320c49b9fbc1f23b96f04c9f86ad44d42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Modify GPP_F14 programmingTim Wawrzynczak2022-07-281-0/+2
| | | | | | | | | | | | | | | | | | For some yet unknown reason, when this GPIO is locked, there is an interrupt storm for IRQ #9 apparently caused by GPE 0x66. GPP_F14 is set to GPE 0x64 on the ADL platform, so this doesn't quite make sense. This patch removes the lock and fixes this IRQ storm, but the root cause is not identified yet. BUG=b:236997604 TEST=`grep ' 9:' /proc/interrupts` shows a reasonable value now Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3d1c66fac80a173798ae33e48b1776d9f4fb5eaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/66201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/brya/var/agah: Optimize dGPU GCOFF entryTim Wawrzynczak2022-07-282-4/+1
| | | | | | | | | | | | | | | | | | | | | After staring at lots of scope shots, the EE has determined that a few modifications to the GCOFF sequence can be made: - Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion - Remove delay after ramping down FBVDD This patch implements these minor changes. BUG=b:240199017 TEST=verified by EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Update ASPM settings for dGPUTim Wawrzynczak2022-07-282-5/+1
| | | | | | | | | | | | | | | | | | After some debugging, it has been determined that the ASPM L0s substate is functional, but there is still some problem with ASPM L1 substates, so this patch updates ASPM status for the dGPU from disabled to L0s only. BUG=b:240390998 TEST=tested with nvidia tools Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I584bdbf26eda20246034263446492bf4daf5f3b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/alderlake: Add support for more CPU PCIe RP UPDsTim Wawrzynczak2022-07-281-0/+6
| | | | | | | | | | | | | | | | | | | There are 3 more CPU PCIe RP UPDs that are the current code is not setting, and some boards may want to set these, so this patch adds support to set these UPDs. The default values for any existing boards using these UPDs should not change with this patch. The UPDs are: - CpuPcieRpDetectTimeoutMs - CpuPcieRpAspm - CpuPcieRpSlotImplemented Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id48019f984e8e53ff3ce0c3c23e02dab65112c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66197 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/anahera{4es}: Add H54G68CYRBX248 supportWisley Chen2022-07-286-2/+6
| | | | | | | | | | | | | | Generate SPD id for hynix H54G68CYRBX248 BUG=b:239899929 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I96babe340678ca9b82b06d3193b93a7676f23fef Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix{4es}: Add H54G68CYRBX248 supportWisley Chen2022-07-286-2/+6
| | | | | | | | | | | | | | Generate SPD id for Hynix H54G68CYRBX248 BUG=b:239888704 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I9412b988bcdb0c744e016f3add6dacda8185d6db Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/ghost: Correct CNVi pinsEric Lai2022-07-281-11/+11
| | | | | | | | | | | | | | | | GPP_F0 to GPP_F4 is for CNVi and should be NF1. GPP_F5 is for CNVi CLK_REQ, and should be NF3 CRF_XTAL_CLKREQ. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=CNVi wifi can get probed in kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ice3fde3a457f6f5c058c0a7d3ca2e63775bda96c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* soc/intel/alderlake: Enable LPIT supportJeremy Soller2022-07-282-0/+3
| | | | | | | | | | | Add SLP_S0 residency register and enable LPIT support. Change-Id: I45e1fc9df3e782cdaac810af3189c5797b1fe413 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Set Energy Perf Bias appropriate default valueJeremy Compostella2022-07-281-2/+3
| | | | | | | | | | | | | | | | | | | | | | | The current "normal" EPB (six) setting resulted in the desired out of box power and performance for several CPU generations. However, a power and performance analysis on Alder Lake and Raptor Lake CPUs demonstrates that this value results in undesirable higher uncore power and that seven is a more appropriate value. Note: the Linux kernel "4ecc933b x86: intel_epb: Allow model specific normal EPB value" patch sets the EPB to 7 for Alder Lake. BRANCH=firmware-brya-14505.B BUG=b:239853069 TEST=verify that EPB is set by coreboot Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I5784656903d4c58bedc5063ee3ef310a99711050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66059 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 12:58:12 +0000