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* tree/: Drop default_spi_probe_opcode for NULL caseEdward O'Callaghan2023-03-031-1/+0
| | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => true' as to not need this boilerplate as it implies default behaviour of a supported opcode within the `check_block_eraser()` match supported loop. Ran; ``` $ find . -name '*.[c,h]' -exec sed -i '/.probe_opcode = default_spi_probe_opcode,/d' '{}' \; ``` Change-Id: Id502c5d2596ad1db52faf05723083620e4c52c12 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/70264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* spi: Make 'default_spi_send_command' the default unless definedEdward O'Callaghan2023-02-271-1/+0
| | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => default_spi_send_command' as to not need this explicit specification of 'default'. Therefore drop the explicit need to specify the 'default_spi_send_command' callback function pointer in the spi_master struct. This is a reasonable default for every other driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I63abcb8c64f233cdbf58a149a31051fa648305a2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Thomas Heijligen <src@posteo.de>
* spi: Make 'default_spi_write_aai' the default unless definedEdward O'Callaghan2022-12-211-1/+0
| | | | | | | | | | | | | | | | | | | A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => default_spi_write_aai' as to not need this explicit specification of 'default'. Therefore Drop the explicit need to specify the 'default_spi_write_aai' callback function pointer in the spi_master struct. This is a reasonable default for every other driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I7f14aaea0edcf0c08cea0e9cd27d58152707fb2a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67479 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* drivers/: Make 'fallback_{un}map' the default unless definedEdward O'Callaghan2022-10-081-2/+0
| | | | | | | | | | | | | | | | | | | Drop the explicit need to specify the default 'fallback_{un}map' callback function pointer from the 'programmer_entry' struct. This is a reasonable default for every other driver in the tree with only a select few exceptions [atavia, serprog, dummyflasher and internal]. Thus this simplifies driver development and paves way to remove the 'programmer' global handle. Change-Id: I5ea7bd68f7ae2cd4af9902ef07255ab6ce0bfdb3 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* drivers/: Make 'internal_delay' the default unless definedEdward O'Callaghan2022-09-271-1/+0
| | | | | | | | | | | | | | | | | | | Drop the explicit need to specify the default 'internal_delay' callback function pointer in the programmer_entry struct. This is a reasonable default for every other driver in the tree with only the two exceptions of ch341a_spi.c and serprog.c. Thus this simplifies driver development. Change-Id: I17460bc2c0aebcbb48c8dfa052b260991525cc49 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67391 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi.c: Retype variable `clock_5x` with boolFelix Singer2022-09-081-2/+3
| | | | | | | | | | | | Use the bool type instead of an integer for the variable `clock_5x`, since this represents its purpose much better. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Ie3005f9dcb2dcfe63261c52a36d865d175a0a75c Reviewed-on: https://review.coreboot.org/c/flashrom/+/66895 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree: Port programmers to pass programmer_cfg to extractorsEdward O'Callaghan2022-09-071-7/+7
| | | | | | | | | | | | | | | | | | | | | Ran; ``` $ find -name '*.c' -exec sed -i 's/extract_programmer_param_str(NULL/extract_programmer_param_str(cfg/g' '{}' \; ``` Manually fix i2c_helper_linux.c and other cases after. Treat cases of; - pcidev.c , and - usb_device.c as exceptional to be dealt with in later patches. Change-Id: If7b7987e803d35582dda219652a6fc3ed5729b47 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree: Allow passing programmer_cfg directly to programmerEdward O'Callaghan2022-09-071-1/+1
| | | | | | | | | | | | | | | | | | | | | Modify the type signature of each programmer entry-point xxx_init() functions to allow for the consumption of the programmer parameterisation string data. ``` $ find -name '*.c' -exec sed -i 's/_init(void)/_init(const char *prog_param)/g' '{}' \; $ find -name '*.c' -exec sed -i 's/get_params(/get_params(const char *prog_param, /g' '{}' \; $ find -name '*.c' -exec sed -i 's/const char \*prog_param)/const struct programmer_cfg *cfg)/g' '{}' \; $ find -name '*.c' -exec sed -i 's/const char \*prog_param,/const struct programmer_cfg *cfg,/g' '{}' \; ``` and manually fix up any remaining parts. Change-Id: I8bab51a635b9d3a43e1619a7a32b334f4ce2cdd2 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* tree: Change signature of extract_programmer_param_str()Edward O'Callaghan2022-09-071-7/+7
| | | | | | | | | | | | | | | | | Results can be reproduced with the following invocation; ``` $ find -name '*.c' -exec sed -i 's/extract_programmer_param_str(/extract_programmer_param_str(NULL, /g' '{}' \; ``` This allows for a pointer to the actual programmer parameters to be passed instead of a global. Change-Id: I781a328fa280e0a9601050dd99a75af72c39c899 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
* ft2232_spi.c: Add support for kt-link jtag interfaceJacek Naglak2022-07-181-0/+26
| | | | | | | | | | | | | | | | | | | | Change tested writing, reading and erasing spi flashes pinout: jtag - spi 1 vcc - vcc, wp#, hold# 4 gnd - gnd 5 tdi - si 7 tms - cs# 9 tck - sck 13 tdo - so Connect pins 9 and 12 in EXT connector for 3.3V power. Signed-off-by: Jacek Naglak <jnaglak@tlen.pl> Change-Id: Id58c675bc410ec3ef6d58603d13efc9ca53bb87c Reviewed-on: https://review.coreboot.org/c/flashrom/+/64440 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi: Add function to probe erase command opcode for all spi_masterAarya Chaumal2022-07-111-0/+1
| | | | | | | | | | | | | | | | | | | | Add a field, probe_opcode, to struct spi_master which points to a function returning a bool by checking if a given command is supported by the programmer in use. This is used for getting a whitelist of commands supported by the programmer, as some programmers like ichspi don't support all opcodes. Most programmers use the default function, which just returns true. ICHSPI and dummyflasher use their specialized function. Change-Id: I6852ef92788221f471a859c879f8aff42558d36d Signed-off-by: Aarya Chaumal <aarya.chaumal@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65183 Reviewed-by: Thomas Heijligen <src@posteo.de> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add `str` extension to extract_programmer_param function nameChinmay Lonkar2022-07-021-7/+7
| | | | | | | | | | | | | This patch changes the function name of extract_programmer_param() to extract_programmer_param_str() as this function name will clearly specify that it returns the value of the given parameter as a string. Signed-off-by: Chinmay Lonkar <chinmay20220@gmail.com> Change-Id: Id7b9fff4d3e1de22abd31b8123a1d237cd0f5c97 Reviewed-on: https://review.coreboot.org/c/flashrom/+/65521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* Global cleanup: Fix a few spelling errorsMartin Roth2022-05-031-1/+1
| | | | | | | | | | | | | | | | Just a trivial patch to fix a few errors found by codespell. Here's the command I used: codespell -S subprojects,out \ -L fwe,dout,tast,crate,parms,claus,nt,nd,te,truns,trun Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4e3b277f220fa70dcab21912c30f1d26d9bd8749 Reviewed-on: https://review.coreboot.org/c/flashrom/+/62840 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi.c: Add FTDI FT4233HCharles Parent2022-03-031-0/+5
| | | | | | | | | | | | Change tested to probe, read, write and erase a MT25QU256 through a FT4233H FTDI Change-Id: I73cee8fd2a6613a8fbc26508d99bbe67da2b4f72 Signed-off-by: Charles Parent <charles.parent@orolia2s.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/62480 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi: reintroduce generic GPIOL controlMichael Niewöhner2021-10-041-8/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reintroduces a reworked version of the GPIOL pin control first introduced in commit 3207844 (CB:49637), which was reverted in commit 6518cf3 (CB:55692) due to breakage. This change introduces a new argument `gpiolX` to allow use of the four GPIOL pins either as generic gpios or as additional CS# signal(s). `X` specifies the GPIOL pin (0-3) to be set to one of [HLC] with the following meaning: * H - set the pin as output high * L - set the pin as output low * C - use the pin as additional CS# signal The third value, `C`, aims to replace the parameter `csgpiol`, that is now marked as deprecated and can be removed at some point in the future. `gpiol` and `csgpiol` are mutually exclusive and use of both results in an error. Multiple pins may be set by specifying the parameter multiple times. Documentation was updated/added accordingly. Test: All pin levels/modes have been verified to behave correctly with a logic analyzer. Change-Id: I3989f0f9596c090de52dca67183b1363dae59d3a Signed-off-by: Alan Green <avg@google.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/57810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ft2232_spi: prevent use of reserved pins on some programmersMichael Niewöhner2021-10-011-0/+12
| | | | | | | | | | | | | On some programmers an output buffer needs to be enabled by pulling a gpio high/low. This gpio can not be used for `csgpiol`. Prevent this by printing an error. Change-Id: Ied450fa5ef358153adefec3beabc63a62c9f60cd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/57809 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi: clarify the comment about gpio configurationMichael Niewöhner2021-09-261-2/+5
| | | | | | | | | | | | | The comment explaining gpio levels might be easily misunderstood when the reader misses the word `output`. Add an explicit description of handling of the GPIOL* pins to avoid that and make things even more clear. Change-Id: Iaceec889a65ead8cdde917f61b2a9695d440f781 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/57808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* remove compile guardsThomas Heijligen2021-09-261-3/+0
| | | | | | | | | | | | | The build system handles the decision when to build a file. Extra compile guards for the source files are not necessary. Change-Id: I76a76e05c7a7dd27637325ab1e9d8946fd5f9076 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/57797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* spi_master: Use new API to register shutdown functionAnastasia Klimchuk2021-08-251-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows spi masters to register shutdown function in spi_master struct, which means there is no need to call register_shutdown in init function, since this call is now a part of register_spi_master. As a consequence of using new API, two things are happening here: 1) No resource leakage anymore in case register_shutdown() would fail, 2) Fixed propagation of register_spi_master() return values. Basic testing: when I comment out free(data) in linux_spi_shutdown, test fails with error ../linux_spi.c:235: note: block 0x55a4db276510 allocated here ERROR: linux_spi_init_and_shutdown_test_success leaked 1 block(s) Means, shutdown function is invoked. BUG=b:185191942 TEST= 1) builds and ninja test including CB:56911 2) On ARMv7 device flashrom -p linux_spi -V -> using linux_spi, chip found 3) On x86_64 AMD device flashrom -p internal -V -> this is actually using sb600spi, chip found Change-Id: Ib60300f9ddb295a255d5ef3f8da0e07064207140 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/56103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ft2232_spi: Add FTDI search by description.Harry Johnson2021-07-291-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds to the search-by-serial functionality with search-by-description (product string). This is useful when e.g. one has multiple FTDIs in a system and wants the serial numbers to reflect the system-level serial number, and the description to reflect the subcomponent names. Tested manually by running with both serial and description searches, on a machine with multiple FTDIs plugged in. Ensured that when two devices with the same vid/pid/serial number are plugged in, description can be used to differentiate. Verifed no-description, no-serial, one FTDI plugged in base case works. Original version of this code used the original single "arg" char*, but on further thought, this wasn't worth the readability and functionality losses. The new version with arg2 gets rid of several lines of code, the gotos, and adds the ability to filter by both description and serial simultaneously. Change-Id: Ib4be23247995710900175f5f16e38db577ef08fa Signed-off-by: Harry Johnson <johnsonh@waymo.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/56164 Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi: Revise error messageNico Huber2021-06-251-2/+1
| | | | | | | | | | | | | Reword the message and drop the error string from libftdi. It is already printed in send_buf(). Change-Id: I125ae9ec0d5487fc26d588a7fd6c54da4ebd0d70 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ft2232_spi: Normalize error paths in ft2232_shutdown()Nico Huber2021-06-251-5/+7
| | | | | | | | | | | | | | We missed to `free(spi_data)` on one path. It also seems odd to leak the return code of a locally used library into our common infrastruc- ture, so normalize all error paths to return 1. Change-Id: I5158d06127a9a8934b083e48b69d29c4d5a11831 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ft2232_spi: Revise comments about output pin statesNico Huber2021-06-251-9/+21
| | | | | | | | | | | | | | | | | | | | The meaning of the variables is easy to misunderstand as some states are merely implicit: All output pins that are not set in the `cs_bits` mask will be constantly driven low. This may be sheer coincidence as all programmers that need additional pins driven use active-low signals to enable buffers. While other pins stay low, *all* pins set in the `cs_bits` mask are supposed to be toggled during SPI transactions. Also drop some irritating dead code and try to explain things in a comment. Change-Id: I2b84ede01759c80f69d5ad17e43783d09ecd1107 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Revert "ft2232_spi: Enhance csgpiol parameter for FT2232"Nico Huber2021-06-251-26/+14
| | | | | | | | | | | | | | | | This reverts commit ba6575de82f091b97ea0f2efcf2f79ef3739d64f. Technically, the only thing that is wrong here is the lack of docu- mentation (manpage update). However, as this change was succeeded by a regressing fixup patch, it seems likely that the meaning of the `csgpiol` parameter was just misunderstood and these changes were not what the author intended. Change-Id: I460237b9d275b1cd1d8a069f852d17dea393b14e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Revert "ft2232_spi: Fix broken GPIOL cs_bits state (#126)"Nico Huber2021-06-251-1/+1
| | | | | | | | | | | | | | | | | This reverts commit a43e44b6abbe8381be3f3dd20a430973cf8b8ab5. Nothing was broken. So this breaks everything. Well, actually only the `csgpiol` parameter. But that is very obvious. `csgpiol` was added to use a GPIO pin as /CS. But this change impli- citly hardcoded /CS to ADBUS3. Change-Id: I9ecdfe227585dda74658c16c96a57dd42d1d78b4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Revert "ft2232_spi.c: Generalize GPIOL pin control"Nico Huber2021-06-251-43/+1
| | | | | | | | | | | | | | This reverts commit 3207844ec0b5dc16f9ae9ee45294213dbf6d060b. It used the `cs_bits` variable for its own purpose (not CS) which was only possible because the `cs_bits` semantics were broken earlier. It also lacks an update to the manpage. Change-Id: I4a95317b1cf1fc6df9471d0cfb8a6a8f40964fe3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Revert "ft2232_spi.c: Rename cs_bits to pinlvl"Nico Huber2021-06-251-14/+14
| | | | | | | | | | | | | | | This reverts commit 180079632b15758ca0bbbe5782611bd4573e11d8. The renaming only seemed to match the code because of earlier introduced regressions (see following reverts). For proper support of the `gpiol` feature, we'd likely need both a `cs_bits` and a `pinlvl` variable. Change-Id: Ifa5b2259ccf49ddf729d01176bacd94a95c39925 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ft2232_spi: Drop ft2232_spi_send_command()Nico Huber2021-06-251-90/+1
| | | | | | | | | | | Now that ft2232_spi_send_multicommand() is implemented, we don't need the single-command version anymore. Change-Id: I2e7fa1046e260f490b881a33e02ad73d16f0a30c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ft2232_spi: Don't lower write data chunksizeNico Huber2021-06-251-4/+0
| | | | | | | | | | | | | | | This "chunk size" limits the amount of data that is passed to libusb at once. If we had exceeded the chunk size, libftdi would have split the data into individual, synchronous bulk transfers. But the chunk size was actually chosen to avoid this. So without any known effect, setting the chunk size is useless. Drop it. Change-Id: I779e24dc3f3379a98ddce02c3765062ac3241884 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/55683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ft2232_spi.c: Implement spi_send_multicommand()Simon Buhrow2021-06-251-1/+90
| | | | | | | | | | | | | | | | | | Every ftdi_write_data() call is quite time consuming as the ftdi-chips seems to take always 2-3ms to respond. This leads to what the comment already says: Minimize USB transfers by packing as many commands as possible together. So I packed the WREN command together with the following operation which can be program or erase operation. This saves about 1 minute when programming a 128MBit Flash within a virtualized setup. Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Reviewed-on: https://review.coreboot.org/c/flashrom/+/40477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* programmer_table: move each entry to the associated programmer sourceThomas Heijligen2021-06-101-2/+11
| | | | | | | | | Change-Id: I3d02bd789f0299e936eb86819b3b15b5ea2bb921 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* programmer: Make use of new register_spi_master() APINico Huber2021-05-131-4/+2
| | | | | | | | | | | Pass pointers to dynamically allocated data to register_spi_master(). This way we can avoid some mutable globals. Change-Id: Id7821f1db3284b7b5b3d0abfd878b979c53870a1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* programmer: Smoothen register_spi_master() APINico Huber2021-05-131-1/+1
| | | | | | | | | | | | | It was impossible to register a const struct spi_master that would point to dynamically allocated `data`. Fix that so that we won't have to create more mutable globals. Change-Id: I0c753b3db050fb87d4bbe2301a7ead854f28456f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi.c: Fix typo in commentAngel Pons2021-04-211-1/+1
| | | | | | | | | | his ---> this Change-Id: Ibcc04a1581b3ba0dcd86e6f900c146823ebcd84a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ft2232_spi.c: Refactor singleton states into reentrant patternAnastasia Klimchuk2021-04-151-34/+57
| | | | | | | | | | | | | | | | | | | Move global singleton states into a struct and store within the spi_master data field for the life-time of the driver. This is one of the steps on the way to move spi_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". TEST=builds BUG=b:140394053 Change-Id: I67518a58b4f35e0edaf06ac09c9374bdf06db0df Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* tree: Remove forward-declarations for spi mastersAnastasia Klimchuk2021-02-161-89/+84
| | | | | | | | | | | | | | | | | Reorder functions to avoid forward-declarations. It looks like for most of the spi masters this has already been done before, I covered remaining small ones in one patch. BUG=b:140394053 TEST=builds Change-Id: I23ff6b79d794876f73b327f18784ca7c04c32c84 Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/50711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi.c: Rename cs_bits to pinlvlAlan Green2021-01-241-12/+12
| | | | | | | | | | | | Renames the variable cs_bits to pinlvl, to more accurately reflect its role. pinlvl works in conjunction with pindir to specify GPIO pin state. Signed-off-by: Alan Green <avg@google.com> Change-Id: I53d1ccae8fa870f037b03762bec79fee1b7bad21 Reviewed-on: https://review.coreboot.org/c/flashrom/+/49780 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi.c: Generalize GPIOL pin controlAlan Green2021-01-241-1/+43
| | | | | | | | | | | | | | | | | | Adds a new arg "gpiol" to allow the four FT2232 GPIOL pins to be set to any combination of high, low or high-impedance. The existing arg "csgpiol", is intended to function as an additional "cs" signal, allowing pins to be set high but not low. This patch preserves the csgpiol arg for backward compatibility. In the event that both arguments are specified, gpiol is used. Signed-off-by: Alan Green <avg@google.com> Change-Id: I1f2b3b968577e62e3c5b11bcdf4afe2de6eb84ab Reviewed-on: https://review.coreboot.org/c/flashrom/+/49637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi.c: release I/Os on shutdownAlan Green2021-01-241-0/+25
| | | | | | | | | | | | | | | | | | | | Reset FTDI I/O pins to high-Z (input) when shutting down. This allows other devices to use the SPI bus without having to disconnect the programmer. This change will introduce a backward incompatibility in the case where a user is relying on the state of FTDI outputs post-programming (eg. to disallow another device from driving CS low). However, there are likely more cases where releasing the SPI bus is the correct thing to do. Signed-off-by: Alan Green <avg@google.com> Change-Id: I9fae55e532595752983f55fac2298f81699dbe5b Reviewed-on: https://review.coreboot.org/c/flashrom/+/49632 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi.c: align with Chrome OS flashromNikolai Artemiev2020-08-041-10/+17
| | | | | | | | | | | | | Brings over various changes: - Use DIS_DIV_5 constant - Update some comments - Wrap long lines Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: I24c20e9b5d7e661d0180699bbd0d1447f6bf816f Reviewed-on: https://review.coreboot.org/c/flashrom/+/42796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* const'ify flashctx to align signatures with cros flashromEdward O'Callaghan2020-04-301-2/+2
| | | | | | | | | | | | | | | | The ChromiumOS flashrom fork has since const'ify flashctx in a few places. This aligns the function signatures to match with downstream to ease forward porting patches out of downstream back into mainline flashrom. This patch is minimum viable alignment and so feedback is welcome. Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi.c: Improve handling of static bufferAngel Pons2020-04-251-3/+3
| | | | | | | | | | | | | | | If `buf` became NULL because of an error, subsequent calls to the `ft2232_spi_send_command` function with a smaller buffer size will result in a null pointer dereference. Add an additional null check before using `buf` to prevent that. Moreover, use `size_t` for the `bufsize` and `oldbufsize` variables, as it's what `realloc` uses. Change-Id: Idc4237ddca94c42ce2a930e6d00fd2d14e4f125c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39975 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi.c: change the chunksize from 256 to 270el-coderon2020-04-081-1/+1
| | | | | | | | | | | | | | | This is to really make use of page write time advantage. Because the Chunksize must be 256Byte raw data plus the address and cmd bytes. For details check: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/message/W2HULJTDPHWPBZY6MLM6TGT7RTHSGHON/ Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Change-Id: Iac067a23025e9df053ab9cd4e82a98de70046c18 Reviewed-on: https://review.coreboot.org/c/flashrom/+/39632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi: Fix broken GPIOL cs_bits state (#126)sibradzic2020-03-091-1/+1
| | | | | | | | | | | | | This only sets 3rd CS# bit be asserted during read/write operations. Tested and confirmed working on 4232H & PicoTap ft2232 programmers against MX25R6435F & S25FL128S chips. Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Change-Id: Ia0ac14b9a52f251306887500dae3e57d73322157 Reviewed-on: https://review.coreboot.org/c/flashrom/+/38898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ft2232_spi: Enhance csgpiol parameter for FT2232sibradzic2020-03-091-14/+26
| | | | | | | | | | | | | | | | | | | | | This allows multiple 'csgpiol' bits to be set to active state at the same time. Previously, only one GPIOL could be activated. I have an use-case such that FT4232H is wired to two different SPI chips, and in order to select one of them two GPIOLs have to be set. Now, one can enable any particular GPIOL, for example: csgpiol=01 would activate GPIOL0 and GPIOL1 at the same time. The change is backward-compatible with previous csgpiol formatting. Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Change-Id: I645ddaa9852e9995bd2a6764862fda2b2ef0c26b Reviewed-on: https://review.coreboot.org/c/flashrom/+/38705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi: Add support for Tin Can Tools Flyswatter/Flyswatter 2Russ Dill2019-12-011-0/+6
| | | | | | | | | | | | | | | | The Tin Can Tools Flyswatter and Flyswatter 2 have a FT2232H with a JTAG interface wired to port A. The buffers that drive the JTAG pins need to be enabled with an nOE signal from the FT2232H ADBUS6 and ADBUS7 pins. Flyswatter has an ARM-14 JTAG interface and Flyswatter 2 has an ARM-20 JTAG interface. Change-Id: I56b1fb76dcda32bb02980cd54a2853506bfc9dfd Signed-off-by: Russ Dill <Russ.Dill@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi: Drop spi_controller typeNico Huber2019-06-271-1/+0
| | | | | | | | | | Not needed anymore. Drop it fast before it encourages anyone to violate layers again! Change-Id: I8eda93b429e3ebaef79e22aba76be62987e496f4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33651 Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi.c: Remove unneeded 'else'Elyes HAOUAS2019-06-211-6/+4
| | | | | | | | | | 'else' is not needed after a 'break' or 'return'. Change-Id: Ia4762d0c0601d56528de56658b869b62fbe5b263 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ft2232_spi: add an ability to use GPIO for chip selectionSergey Alirzaev2018-10-081-0/+17
| | | | | | | | Change-Id: I6db05619e0d69ad18549c8556ef69225337b1532 Signed-off-by: Sergey Alirzaev <zl29ah@gmail.com> Reviewed-on: https://review.coreboot.org/28911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-4/+0
| | | | | | | | Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-02 22:17:08 +0000