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path: root/drivers/clk/renesas
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* clk: renesas: r8a779g0: Add PWM clockGeert Uytterhoeven2022-10-261-0/+1
* clk: renesas: r8a779g0: Add SCIF clocksGeert Uytterhoeven2022-10-261-0/+4
* Merge tag 'renesas-clk-fixes-for-v6.1-tag1'Geert Uytterhoeven2022-10-261-4/+9
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| * clk: renesas: r8a779g0: Fix HSCIF parent clocksGeert Uytterhoeven2022-10-261-4/+4
| * clk: renesas: r8a779g0: Add SASYNCPER clocksGeert Uytterhoeven2022-10-181-0/+5
* | clk: renesas: r9a07g044: Add MTU3a clock and reset entryBiju Das2022-10-171-1/+4
* | clk: renesas: r8a779g0: Add INTC-EX clockGeert Uytterhoeven2022-10-171-0/+1
* | clk: renesas: r8a779g0: Add MSIOF clocksGeert Uytterhoeven2022-10-171-0/+6
* | clk: renesas: r8a779g0: Add SYS-DMAC clocksGeert Uytterhoeven2022-10-171-0/+2
* | clk: renesas: r8a779f0: Add Ethernet Switch clocksYoshihiro Shimoda2022-10-171-0/+2
* | clk: renesas: rzg2l: Fix typo in function nameLad Prabhakar2022-10-171-3/+3
* | clk: renesas: rzg2l: Support sd clk mux round operationBiju Das2022-10-171-1/+1
|/
* clk: renesas: r8a779g0: Add EtherAVB clocksGeert Uytterhoeven2022-09-181-0/+3
* clk: renesas: r8a779g0: Add PFC/GPIO clocksGeert Uytterhoeven2022-09-181-0/+4
* clk: renesas: r8a779g0: Add I2C clocksGeert Uytterhoeven2022-09-181-0/+6
* clk: renesas: r8a779g0: Add watchdog clockGeert Uytterhoeven2022-09-181-0/+1
* clk: renesas: r8a779f0: Add MSIOF clocksWolfram Sang2022-08-291-0/+4
* clk: renesas: r9a09g011: Add IIC clock and reset entriesPhil Edworthy2022-08-291-0/+4
* clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_infoBiju Das2022-08-221-0/+2
* clk: renesas: r8a779f0: Add TMU and parent SASYNC clocksWolfram Sang2022-08-221-0/+10
* clk: renesas: r8a779f0: Add CMT clocksWolfram Sang2022-08-151-0/+4
* clk: renesas: r8a779f0: Add SDH0 clockWolfram Sang2022-08-151-1/+2
* clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_configAndi Kleen2022-07-051-1/+1
* clk: renesas: r9a07g043: Add support for RZ/Five SoCLad Prabhakar2022-07-051-0/+32
* clk: renesas: r8a779f0: Add HSCIF clocksWolfram Sang2022-06-171-0/+4
* clk: renesas: r8a779f0: Add PCIe clocksYoshihiro Shimoda2022-06-171-0/+2
* clk: renesas: r8a779f0: Add Z0 and Z1 clock supportGeert Uytterhoeven2022-06-171-0/+2
* clk: renesas: rza1: Remove struct rz_cpgGeert Uytterhoeven2022-06-131-18/+15
* clk: renesas: r8a7779: Remove struct r8a7779_cpgGeert Uytterhoeven2022-06-131-18/+9
* clk: renesas: r8a7778: Remove struct r8a7778_cpgGeert Uytterhoeven2022-06-131-22/+9
* clk: renesas: sh73a0: Remove sh73a0_cpg.regGeert Uytterhoeven2022-06-131-13/+13
* clk: renesas: r8a7740: Remove r8a7740_cpg.regGeert Uytterhoeven2022-06-131-10/+10
* clk: renesas: r8a73a4: Remove r8a73a4_cpg.regGeert Uytterhoeven2022-06-131-11/+11
* clk: renesas: r8a779f0: Add SDHI0 clockWolfram Sang2022-06-131-0/+1
* clk: renesas: r8a779f0: Add thermal clockWolfram Sang2022-06-131-0/+1
* clk: renesas: rzg2l: Fix reset status functionBiju Das2022-06-071-1/+1
* clk: renesas: r9a06g032: Fix UART clkgrp bitselRalph Siemsen2022-06-061-4/+4
* clk: renesas: r9a06g032: Drop some unused fieldsRalph Siemsen2022-06-061-13/+11
* clk: renesas: r9a09g011: Add WDT clock and reset entriesPhil Edworthy2022-06-061-0/+3
* clk: renesas: r9a09g011: Add PFC clock and reset entriesPhil Edworthy2022-06-061-0/+2
* clk: renesas: r9a07g044: Add POEG clock and reset entriesBiju Das2022-06-061-1/+13
* clk: renesas: r9a07g044: Add GPT clock and reset entryBiju Das2022-06-061-1/+4
* Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2022-05-291-1/+39
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| * clk: renesas: r9a06g032: Probe possible childrenMiquel Raynal2022-05-191-0/+5
| * clk: renesas: r9a06g032: Export function to set dmamuxMiquel Raynal2022-05-191-1/+34
* | clk: renesas: r9a09g011: Add eth clock and reset entriesPhil Edworthy2022-05-061-5/+9
* | clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy2022-05-065-0/+181
* | clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy2022-05-052-3/+17
* | clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy2022-05-054-1/+16
* | clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy2022-05-053-31/+19
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 08:27:11 +0000