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path: root/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
Commit message (Expand)AuthorAgeFilesLines
* drm/amd/display: Improve x86 and dmub ips handshakeDuncan Ma2023-09-261-0/+2
* drm/amd/display: Add IPS control flagSung Joon Kim2023-09-201-0/+1
* drm/amd/display: fix some non-initialized register mask and settingCharlene Liu2023-09-111-2/+4
* drm/amd/display: Add DCN35 CLK_MGRQingqing Zhuo2023-08-301-0/+1
* drm/amd/display: Enable dc mode clock switching for DCN32xAlvin Lee2023-06-231-0/+1
* drm/amd/display: Filter out AC mode frequencies on DC mode systemsAustin Zheng2023-06-091-0/+1
* drm/amd/display: On clock init, maintain DISPCLK freqAlvin Lee2023-04-111-0/+3
* drm/amd/display: Acquire FCLK DPM levels on DCN32Dillon Varone2022-10-101-1/+14
* drm/amd/display: Correct dram channel width for dcn314Duncan Ma2022-09-131-0/+1
* drm/amd/display: Fix __floatunsidf undefined for 32 bit compilationRodrigo Siqueira2022-06-301-1/+1
* drm/amd/display: Get VCO frequency from registersRodrigo Siqueira2022-06-211-0/+3
* drm/amd/display: add CLKMGR changes for DCN32/321Aurabindo Pillai2022-06-031-0/+2
* drm/amd/display: revert Blank eDP on disable/enable drvLeung, Martin2022-06-011-0/+1
* drm/amd/display: update dcn315 clk table readDmytro Laktyushkin2022-04-251-0/+1
* drm/amd/display: implement dc_mode_memclkMartin Leung2021-12-141-0/+7
* drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCNAlex Deucher2021-06-221-2/+0
* drm/amd/display: Add DCN3.1 clock manager supportNicholas Kazlauskas2021-06-041-0/+3
* drm/amd/display: Disable MALL when SMU not presentChris Park2021-04-091-0/+3
* drm/amd/display: hide VGH asic specific structsDmytro Laktyushkin2021-04-091-9/+0
* drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher2020-11-041-25/+1
* drm/amd/display: Add dcn3.01 support to DC (v2)Roman Li2020-10-051-0/+33
* drm/amd/display: Send DISPLAY_OFF after power down on bootSung Lee2020-08-261-0/+2
* drm/amd/display: Request PHYCLK adjustment on PHY enable/disableJoshua Aberback2020-07-081-0/+3
* drm/amd/display: add support for per-state dummy-pstate latencyJun Lei2020-07-011-0/+6
* drm/amd/display: Add DCN3 CLK_MGRBhawanpreet Lakha2020-07-011-0/+69
* drm/amd/display: Add wm ranges to clk_mgrSung Lee2020-02-061-0/+2
* drm/amd/display: fix dprefclk and ss percentage reading on RNEric Yang2019-12-051-0/+1
* drm/amd/display: update sr and pstate latencies for RenoirEric Yang2019-12-051-0/+2
* drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_1 flagBhawanpreet Lakha2019-11-131-6/+0
* drm/amd/display: move wm ranges reporting to end of init hwEric Yang2019-10-251-0/+1
* drm/amd/display: move dispclk vco freq to clk mgr baseDmytro Laktyushkin2019-10-251-1/+1
* drm/amd/display: add renoir specific watermark range and clk helperDmytro Laktyushkin2019-10-101-1/+2
* drm/amd/display: exit PSR during detectionEric Yang2019-10-101-0/+5
* drm/amd/display: add explicit comparator as default optimization checkJun Lei2019-10-101-0/+3
* drm/amd/display: Add Renoir clock managerBhawanpreet Lakha2019-08-291-0/+125
* drm/amd/display: add set and get clock for testing purposesCharlene Liu2019-07-181-0/+7
* drm/amd/display: Fix null-deref on vega20 with xgmiRoman Li2019-06-201-2/+0
* drm/amd/display: Refactor clk_mgr functionsEric Yang2019-05-311-0/+5
* drm/amd/display: make clk mgr soc specificEric Yang2019-05-311-10/+22
* drm/amd/display: Set dispclk and dprefclock directlyEric Yang2019-05-241-1/+7
* drm/amd/display: Create clock funcsEryk Brol2019-03-271-0/+2
* drm/amd/display: rename dccg to clk_mgrDmytro Laktyushkin2018-11-051-0/+47
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