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path: root/src/soc/amd/cezanne/include/soc/southbridge.h
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* soc/amd/*/i2c: factor out common I2C pad configurationFelix Held2022-02-031-27/+0
* soc/amd/*/i2c: introduce and use MISC_I2C_PAD_CTRL(bus) macroFelix Held2022-02-031-0/+1
* soc/amd/*/i2c: drop unused mainboard_i2c_overrideFelix Held2022-02-031-3/+0
* soc/amd/cezanne/fch: disable 48MHz output in S0i3Felix Held2021-12-201-0/+1
* soc/amd/cezanne: add missing PM_ACPI_* bit definitionsFelix Held2021-11-301-0/+16
* soc/amd/cezanne,picasso/include/southbridge: use bitwise or in definesFelix Held2021-11-101-3/+3
* soc/amd/cezanne,picasso/include/southbridge: fix typo in defineFelix Held2021-11-091-1/+1
* src/soc/amd/cezanne: enable clock gatingJulian Schroeder2021-10-131-0/+11
* soc/amd/common/block/espi_util: Refactor eSPI SetupKarthikeyan Ramasubramanian2021-10-131-1/+0
* soc/amd/cezanne/include/southbridge: add some more PM register definesFelix Held2021-10-111-0/+4
* soc/amd/cezanne/fch: implement and use fch_clk_output_48MhzFelix Held2021-08-301-0/+2
* soc/amd/cezanne: Init eSPI early if requiredMartin Roth2021-06-231-0/+1
* soc/amd/cezanne: factor out AOAC offset definesFelix Held2021-06-161-14/+0
* soc/amd/cezanne,picasso: add AOAC offset define for the eMMC controllerFelix Held2021-06-161-0/+1
* soc/amd/cezanne: remove warm reset flag codeFelix Held2021-06-111-3/+0
* soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settingsFelix Held2021-05-191-0/+15
* soc/amd: move PM_RST_CTRL1 register definition to common acpimmio headerFelix Held2021-03-291-3/+0
* mb/google/guybrush: disable KBRSTENKangheui Won2021-03-241-0/+1
* soc/amd/cezanne: Get I2C specific code for cezanneZheng Bao2021-03-221-0/+30
* soc/amd/cezanne: select soc-specific ACPI functionalityFelix Held2021-02-111-0/+4
* soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_portsFelix Held2021-02-101-0/+4
* soc/amd/cezanne: Enable early LPC support in bootblock stageZheng Bao2021-02-091-0/+15
* soc/amd/cezanne/fch: add ACPI I/O port setupFelix Held2021-02-051-0/+30
* soc/amd/cezanne: remove UART2/3 AOAC device offsetsFelix Held2021-02-031-2/+0
* soc/amd/cezanne: add empty ramstage FCH supportFelix Held2021-01-291-2/+5
* soc/amd/cezanne: add AOAC supportFelix Held2021-01-141-0/+17
* soc/amd/cezanne: add console UART supportFelix Held2021-01-141-0/+2
* soc/amd/cezanne: Add SMI supportZheng Bao2020-12-181-0/+1
* soc/amd/cezanne: add 0xcf9 resetFelix Held2020-12-111-0/+7
* soc/amd/cezanne: add basic early FCH initialization to bootblockFelix Held2020-12-091-0/+3
* soc/amd/cezanne: add common SMBus code to buildFelix Held2020-12-091-0/+8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-18 01:52:58 +0000